Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43462127	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10177147

1

T1

3651

T2

6759

T3

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52910577	1			T1	7343		T2	26848		T3	89
values[0x0]	363479	1			T1	7		T2	94		T3	37
values[0x1]	365218	1			T1	10		T2	64		T3	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31001715	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22637559

1

T1

4392

T2

12655

T3

67

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	231834	1			T1	25		T2	124		T4	3
valid_sources[0x01]	199013	1			T1	35		T2	120		T5	70
valid_sources[0x02]	208520	1			T1	33		T2	79		T4	2
valid_sources[0x03]	210711	1			T1	41		T2	122		T5	65
valid_sources[0x04]	202419	1			T1	35		T2	102		T4	2
valid_sources[0x05]	187941	1			T1	25		T2	106		T4	1
valid_sources[0x06]	473875	1			T1	27		T2	95		T4	2
valid_sources[0x07]	203700	1			T1	27		T2	105		T4	4
valid_sources[0x08]	187453	1			T1	20		T2	101		T4	1
valid_sources[0x09]	195737	1			T1	25		T2	111		T4	2
valid_sources[0x0a]	191634	1			T1	34		T2	119		T4	1
valid_sources[0x0b]	190343	1			T1	20		T2	106		T5	62
valid_sources[0x0c]	184279	1			T1	17		T2	108		T5	57
valid_sources[0x0d]	206822	1			T1	30		T2	93		T4	2
valid_sources[0x0e]	194955	1			T1	26		T2	107		T4	2
valid_sources[0x0f]	183323	1			T1	28		T2	107		T5	41
valid_sources[0x10]	209663	1			T1	36		T2	93		T4	3
valid_sources[0x11]	187070	1			T1	24		T2	97		T5	35
valid_sources[0x12]	176864	1			T1	37		T2	104		T5	62
valid_sources[0x13]	200494	1			T1	21		T2	89		T4	1
valid_sources[0x14]	201932	1			T1	22		T2	114		T5	46
valid_sources[0x15]	186987	1			T1	12		T2	107		T5	53
valid_sources[0x16]	204637	1			T1	37		T2	106		T5	41
valid_sources[0x17]	186793	1			T1	27		T2	111		T5	59
valid_sources[0x18]	250421	1			T1	17		T2	85		T5	54
valid_sources[0x19]	205507	1			T1	29		T2	95		T4	2
valid_sources[0x1a]	191873	1			T1	28		T2	110		T5	48
valid_sources[0x1b]	272479	1			T1	21		T2	107		T4	3
valid_sources[0x1c]	210099	1			T1	14		T2	79		T5	41
valid_sources[0x1d]	203975	1			T1	24		T2	82		T5	53
valid_sources[0x1e]	200299	1			T1	33		T2	106		T4	1
valid_sources[0x1f]	175671	1			T1	28		T2	90		T4	2
valid_sources[0x20]	209120	1			T1	48		T2	107		T4	1
valid_sources[0x21]	179851	1			T1	28		T2	110		T5	50
valid_sources[0x22]	186694	1			T1	29		T2	116		T4	2
valid_sources[0x23]	176685	1			T1	24		T2	104		T5	62
valid_sources[0x24]	209189	1			T1	22		T2	100		T4	1
valid_sources[0x25]	198170	1			T1	20		T2	120		T4	1
valid_sources[0x26]	223585	1			T1	23		T2	103		T5	46
valid_sources[0x27]	295855	1			T1	27		T2	95		T4	1
valid_sources[0x28]	208607	1			T1	30		T2	119		T5	42
valid_sources[0x29]	201386	1			T1	38		T2	110		T4	1
valid_sources[0x2a]	186645	1			T1	21		T2	118		T4	1
valid_sources[0x2b]	184747	1			T1	21		T2	108		T4	1
valid_sources[0x2c]	194263	1			T1	27		T2	124		T4	1
valid_sources[0x2d]	204355	1			T1	11		T2	94		T5	45
valid_sources[0x2e]	178954	1			T1	27		T2	116		T4	2
valid_sources[0x2f]	205152	1			T1	27		T2	110		T4	2
valid_sources[0x30]	184846	1			T1	23		T2	117		T5	65
valid_sources[0x31]	322615	1			T1	33		T2	121		T4	2
valid_sources[0x32]	193709	1			T1	32		T2	92		T4	2
valid_sources[0x33]	183865	1			T1	34		T2	140		T5	57
valid_sources[0x34]	198275	1			T1	21		T2	136		T4	1
valid_sources[0x35]	183191	1			T1	25		T2	96		T4	3
valid_sources[0x36]	219220	1			T1	27		T2	99		T4	4
valid_sources[0x37]	212580	1			T1	17		T2	104		T4	1
valid_sources[0x38]	208623	1			T1	21		T2	97		T5	37
valid_sources[0x39]	202141	1			T1	28		T2	117		T4	1
valid_sources[0x3a]	204155	1			T1	26		T2	114		T4	1
valid_sources[0x3b]	192883	1			T1	33		T2	90		T5	43
valid_sources[0x3c]	192682	1			T1	49		T2	100		T5	56
valid_sources[0x3d]	190145	1			T1	26		T2	108		T5	25
valid_sources[0x3e]	191702	1			T1	25		T2	110		T4	2
valid_sources[0x3f]	211968	1			T1	25		T2	117		T5	62
valid_sources[0x40]	189922	1			T1	29		T2	100		T5	31
valid_sources[0x41]	193716	1			T1	53		T2	142		T4	1
valid_sources[0x42]	179886	1			T1	30		T2	82		T5	43
valid_sources[0x43]	196049	1			T1	33		T2	107		T4	2
valid_sources[0x44]	200246	1			T1	33		T2	88		T4	1
valid_sources[0x45]	554798	1			T1	42		T2	132		T5	62
valid_sources[0x46]	202019	1			T1	17		T2	99		T4	2
valid_sources[0x47]	200885	1			T1	36		T2	86		T5	58
valid_sources[0x48]	183473	1			T1	21		T2	116		T5	56
valid_sources[0x49]	232907	1			T1	30		T2	104		T4	3
valid_sources[0x4a]	206524	1			T1	38		T2	98		T4	1
valid_sources[0x4b]	224232	1			T1	23		T2	85		T4	2
valid_sources[0x4c]	185054	1			T1	29		T2	112		T5	58
valid_sources[0x4d]	216123	1			T1	14		T2	129		T4	1
valid_sources[0x4e]	198514	1			T1	40		T2	95		T5	45
valid_sources[0x4f]	212091	1			T1	16		T2	91		T4	1
valid_sources[0x50]	192049	1			T1	20		T2	82		T4	1
valid_sources[0x51]	194894	1			T1	32		T2	111		T5	34
valid_sources[0x52]	193896	1			T1	34		T2	97		T4	1
valid_sources[0x53]	213459	1			T1	28		T2	111		T4	1
valid_sources[0x54]	190941	1			T1	32		T2	114		T4	1
valid_sources[0x55]	187105	1			T1	42		T2	124		T4	1
valid_sources[0x56]	197319	1			T1	27		T2	115		T4	1
valid_sources[0x57]	193798	1			T1	31		T2	95		T4	1
valid_sources[0x58]	184975	1			T1	47		T2	105		T5	61
valid_sources[0x59]	202831	1			T1	26		T2	85		T5	47
valid_sources[0x5a]	197926	1			T1	29		T2	119		T4	1
valid_sources[0x5b]	177404	1			T1	25		T2	106		T5	46
valid_sources[0x5c]	215667	1			T1	19		T2	110		T5	48
valid_sources[0x5d]	211073	1			T1	26		T2	119		T5	45
valid_sources[0x5e]	185828	1			T1	29		T2	131		T5	66
valid_sources[0x5f]	197104	1			T1	33		T2	89		T4	1
valid_sources[0x60]	177057	1			T1	34		T2	95		T4	1
valid_sources[0x61]	203297	1			T1	31		T2	78		T5	59
valid_sources[0x62]	189451	1			T1	29		T2	120		T4	1
valid_sources[0x63]	204912	1			T1	22		T2	120		T4	2
valid_sources[0x64]	191183	1			T1	22		T2	99		T5	34
valid_sources[0x65]	171722	1			T1	27		T2	95		T4	1
valid_sources[0x66]	189241	1			T1	26		T2	102		T5	55
valid_sources[0x67]	185304	1			T1	28		T2	121		T5	56
valid_sources[0x68]	195291	1			T1	25		T2	96		T4	2
valid_sources[0x69]	227098	1			T1	24		T2	86		T4	1
valid_sources[0x6a]	176033	1			T1	28		T2	121		T4	2
valid_sources[0x6b]	191819	1			T1	24		T2	91		T4	2
valid_sources[0x6c]	188006	1			T1	34		T2	98		T5	61
valid_sources[0x6d]	181595	1			T1	33		T2	104		T4	1
valid_sources[0x6e]	214184	1			T1	23		T2	91		T4	1
valid_sources[0x6f]	214787	1			T1	32		T2	77		T5	58
valid_sources[0x70]	190417	1			T1	25		T2	96		T4	1
valid_sources[0x71]	178046	1			T1	26		T2	98		T4	4
valid_sources[0x72]	188490	1			T1	24		T2	108		T4	3
valid_sources[0x73]	209519	1			T1	26		T2	121		T4	1
valid_sources[0x74]	182146	1			T1	23		T2	93		T4	1
valid_sources[0x75]	219923	1			T1	43		T2	98		T4	1
valid_sources[0x76]	178047	1			T1	27		T2	96		T5	47
valid_sources[0x77]	292217	1			T1	34		T2	88		T5	37
valid_sources[0x78]	192422	1			T1	27		T2	115		T5	62
valid_sources[0x79]	196251	1			T1	37		T2	137		T4	1
valid_sources[0x7a]	199555	1			T1	30		T2	92		T4	1
valid_sources[0x7b]	199616	1			T1	24		T2	110		T5	64
valid_sources[0x7c]	219051	1			T1	25		T2	89		T4	1
valid_sources[0x7d]	188899	1			T1	22		T2	79		T4	2
valid_sources[0x7e]	200541	1			T1	31		T2	103		T4	1
valid_sources[0x7f]	194098	1			T1	29		T2	101		T4	1
valid_sources[0x80]	202030	1			T1	29		T2	130		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9823668

1

T1

3639

T2

6698

T3

2

values[0x0]

all_enables

biggest_size

203973

1

T1

5

T2

47

T3

14

values[0x1]

all_enables

biggest_size

149506

1

T1

7

T2

14

T3

12