Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	354669697	0	0	0
ctrl_rd_A	354669697	1666	0	0
host_fifo_config_rd_A	354669697	4555	0	0
host_nack_handler_timeout_rd_A	354669697	908	0	0
host_timeout_ctrl_rd_A	354669697	773	0	0
intr_enable_rd_A	354669697	2803	0	0
ovrd_rd_A	354669697	1393	0	0
target_fifo_config_rd_A	354669697	874	0	0
target_id_rd_A	354669697	1146	0	0
target_timeout_ctrl_rd_A	354669697	871	0	0
timeout_ctrl_rd_A	354669697	1047	0	0
timing0_rd_A	354669697	935	0	0
timing1_rd_A	354669697	929	0	0
timing2_rd_A	354669697	851	0	0
timing3_rd_A	354669697	998	0	0
timing4_rd_A	354669697	957	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	1666	0	0
T87	6277	52	0	0
T88	14767	328	0	0
T89	6364	49	0	0
T90	1281	19	0	0
T91	1749	9	0	0
T92	6954	75	0	0
T93	2116	41	0	0
T94	4322	16	0	0
T95	11724	51	0	0
T96	7927	24	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	4555	0	0
T97	461708	181	0	0
T98	0	219	0	0
T99	0	98	0	0
T100	0	182	0	0
T101	0	150	0	0
T102	0	103	0	0
T103	0	73	0	0
T104	0	204	0	0
T105	0	115	0	0
T106	0	205	0	0
T107	58331	0	0	0
T108	225200	0	0	0
T109	44536	0	0	0
T110	11713	0	0	0
T111	8341	0	0	0
T112	39470	0	0	0
T113	266919	0	0	0
T114	5735	0	0	0
T115	119332	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	908	0	0
T87	6277	66	0	0
T88	14767	86	0	0
T89	6364	81	0	0
T90	1281	4	0	0
T92	6954	125	0	0
T93	2116	15	0	0
T94	4322	35	0	0
T95	11724	18	0	0
T96	7927	18	0	0
T116	2426	6	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	773	0	0
T87	6277	78	0	0
T88	14767	68	0	0
T89	6364	56	0	0
T90	1281	4	0	0
T91	1749	3	0	0
T92	6954	139	0	0
T93	2116	9	0	0
T94	4322	44	0	0
T116	2426	12	0	0
T117	4336	17	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	2803	0	0
T100	549232	48	0	0
T118	0	26	0	0
T119	0	18	0	0
T120	0	15	0	0
T121	0	24	0	0
T122	0	3	0	0
T123	0	20	0	0
T124	0	3	0	0
T125	0	21	0	0
T126	0	11	0	0
T127	12671	0	0	0
T128	139318	0	0	0
T129	2810	0	0	0
T130	40440	0	0	0
T131	181079	0	0	0
T132	10464	0	0	0
T133	66568	0	0	0
T134	202134	0	0	0
T135	92497	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	1393	0	0
T87	0	53	0	0
T88	0	126	0	0
T136	2807	26	0	0
T137	0	51	0	0
T138	0	66	0	0
T139	0	21	0	0
T140	0	35	0	0
T141	0	50	0	0
T142	0	17	0	0
T143	0	26	0	0
T144	72570	0	0	0
T145	1043	0	0	0
T146	122885	0	0	0
T147	11698	0	0	0
T148	4353	0	0	0
T149	942483	0	0	0
T150	242323	0	0	0
T151	34423	0	0	0
T152	26874	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	874	0	0
T87	6277	60	0	0
T88	14767	76	0	0
T89	6364	52	0	0
T90	1281	6	0	0
T91	1749	4	0	0
T92	6954	119	0	0
T93	2116	5	0	0
T94	4322	10	0	0
T116	2426	8	0	0
T117	4336	13	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	1146	0	0
T87	6277	55	0	0
T88	14767	180	0	0
T89	6364	55	0	0
T90	1281	1	0	0
T92	6954	100	0	0
T93	2116	7	0	0
T94	4322	20	0	0
T95	11724	2	0	0
T96	7927	19	0	0
T116	2426	2	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	871	0	0
T87	6277	40	0	0
T88	14767	81	0	0
T89	6364	58	0	0
T90	1281	3	0	0
T91	1749	5	0	0
T92	6954	114	0	0
T93	2116	11	0	0
T94	4322	21	0	0
T95	11724	40	0	0
T96	7927	35	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	1047	0	0
T87	6277	66	0	0
T88	14767	164	0	0
T89	6364	55	0	0
T90	1281	4	0	0
T91	1749	22	0	0
T92	6954	131	0	0
T93	2116	12	0	0
T94	4322	6	0	0
T95	11724	19	0	0
T117	4336	11	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	935	0	0
T87	6277	82	0	0
T88	14767	106	0	0
T89	6364	46	0	0
T90	1281	5	0	0
T91	1749	5	0	0
T92	6954	118	0	0
T93	2116	11	0	0
T94	4322	23	0	0
T116	2426	11	0	0
T117	4336	4	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	929	0	0
T87	6277	52	0	0
T88	14767	102	0	0
T89	6364	72	0	0
T92	6954	130	0	0
T93	2116	10	0	0
T94	4322	41	0	0
T95	11724	9	0	0
T96	7927	15	0	0
T153	3138	3	0	0
T154	15050	80	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	851	0	0
T87	6277	58	0	0
T88	14767	102	0	0
T89	6364	52	0	0
T90	1281	5	0	0
T91	1749	3	0	0
T92	6954	142	0	0
T93	2116	5	0	0
T94	4322	15	0	0
T95	11724	6	0	0
T117	4336	3	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	998	0	0
T87	6277	79	0	0
T88	14767	118	0	0
T89	6364	57	0	0
T90	1281	4	0	0
T91	1749	2	0	0
T92	6954	114	0	0
T93	2116	13	0	0
T94	4322	47	0	0
T95	11724	23	0	0
T116	2426	10	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	354669697	957	0	0
T87	6277	61	0	0
T88	14767	114	0	0
T89	6364	100	0	0
T92	6954	116	0	0
T93	2116	7	0	0
T94	4322	37	0	0
T95	11724	12	0	0
T96	7927	32	0	0
T116	2426	1	0	0
T153	3138	21	0	0