Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.59	92.59	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	92.59	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	4	23	85.19

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	4	23	85.19	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

160738

1

T2

561

T7

159

T10

242

ack

14618

1

T2

5

T4

41

T7

26

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	614	1			T2	3		T7	1		T29	1
high	36028	1			T2	119		T4	8		T7	35
med	65010	1			T2	221		T4	3		T7	76
sml	73060	1			T2	220		T4	30		T7	71
all_zero	644	1			T2	3		T7	2		T10	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87389

1

T2

278

T4

20

T7

81

auto[1]

87967

1

T2

288

T4

21

T7

104

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120044

1

T2

364

T4

29

T7

141

auto[1]

55312

1

T2

202

T4

12

T7

44

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167652

1

T2

565

T4

15

T7

173

auto[1]

7704

1

T2

1

T4

26

T7

12

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165424

1

T2

561

T4

26

T7

160

auto[1]

9932

1

T2

5

T4

15

T7

25

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166418

1

T2

563

T4

27

T7

161

auto[1]

8938

1

T2

3

T4

14

T7

24

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87389

1

T2

278

T4

20

T7

81

auto[1]

87967

1

T2

288

T4

21

T7

104

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120044

1

T2

364

T4

29

T7

141

auto[1]

55312

1

T2

202

T4

12

T7

44

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167652

1

T2

565

T4

15

T7

173

auto[1]

7704

1

T2

1

T4

26

T7

12

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165424

1

T2

561

T4

26

T7

160

auto[1]

9932

1

T2

5

T4

15

T7

25

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166418

1

T2

563

T4

27

T7

161

auto[1]

8938

1

T2

3

T4

14

T7

24

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	4	23	85.19	2
Automatically Generated Cross Bins	15	2	13	86.67	2
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[ack]	0	1	1
[all_zero]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[ack]	0	1	1

Covered bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T106

1

T240

1

T241

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T62

1

T242

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

270

1

T7

1

T10

4

T66

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

156

1

T10

1

T61

1

T145

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

113

1

T48

1

T61

1

T62

3

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

519

1

T7

3

T10

1

T29

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

287

1

T7

1

T10

1

T62

10

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

245

1

T10

3

T29

1

T61

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

527

1

T10

5

T48

2

T66

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

253

1

T10

2

T29

1

T66

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

272

1

T7

3

T66

1

T61

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

11

1

T62

1

T106

1

T109

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

5

1

T243

1

T244

1

T245

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	50889	1			T2	180		T7	42		T10	63
write_address_byte	9932	1			T2	5		T4	15		T7	25
read_with_ack	2304	1			T4	12		T29	2		T32	1
read_with_nack	5400	1			T2	1		T4	14		T7	12
stop_byte	8938	1			T2	3		T4	14		T7	24
write_address_byte_nak	4849	1			T2	2		T7	17		T10	25
data_byte_nack	160738	1			T2	561		T7	159		T10	242
stop_byte_nack	5302	1			T2	1		T7	17		T10	24
nakok_byte_nack	80604	1			T2	286		T7	90		T10	120
nakok_addr_byte_nack	2461	1			T2	1		T7	10		T10	11