Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44100444	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10548613

1

T1

13

T2

6640

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53921395	1			T1	3		T2	71996		T3	16
values[0x0]	363284	1			T1	8		T2	499		T3	8
values[0x1]	364378	1			T1	9		T2	518		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31447968	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

23201089

1

T1

16

T2

27743

T3

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	251270	1			T2	314		T4	32		T5	6
valid_sources[0x01]	225904	1			T2	262		T4	53		T5	3
valid_sources[0x02]	191493	1			T2	309		T4	52		T6	2
valid_sources[0x03]	204299	1			T2	488		T4	53		T6	3
valid_sources[0x04]	196087	1			T2	421		T4	37		T5	2
valid_sources[0x05]	209345	1			T2	321		T4	61		T5	3
valid_sources[0x06]	323904	1			T2	248		T4	40		T5	2
valid_sources[0x07]	210053	1			T2	235		T4	51		T5	5
valid_sources[0x08]	197362	1			T2	158		T4	54		T5	12
valid_sources[0x09]	187519	1			T2	384		T4	35		T5	5
valid_sources[0x0a]	191927	1			T2	377		T4	36		T5	2
valid_sources[0x0b]	189374	1			T2	114		T4	45		T5	5
valid_sources[0x0c]	242809	1			T2	246		T4	58		T5	2
valid_sources[0x0d]	207490	1			T2	427		T4	48		T5	7
valid_sources[0x0e]	215989	1			T2	239		T3	1		T4	34
valid_sources[0x0f]	201342	1			T2	252		T4	50		T5	7
valid_sources[0x10]	224653	1			T2	186		T4	42		T5	2
valid_sources[0x11]	204815	1			T2	251		T4	35		T5	7
valid_sources[0x12]	199792	1			T2	300		T4	38		T6	2
valid_sources[0x13]	204854	1			T2	330		T4	57		T5	7
valid_sources[0x14]	193159	1			T2	251		T4	37		T5	2
valid_sources[0x15]	221113	1			T1	2		T2	245		T4	45
valid_sources[0x16]	192697	1			T2	290		T4	47		T5	2
valid_sources[0x17]	205330	1			T2	194		T4	31		T5	8
valid_sources[0x18]	187186	1			T2	217		T4	39		T6	5
valid_sources[0x19]	186677	1			T2	248		T4	34		T5	4
valid_sources[0x1a]	200171	1			T2	225		T4	32		T5	6
valid_sources[0x1b]	197770	1			T2	258		T4	56		T6	1
valid_sources[0x1c]	208907	1			T2	244		T3	1		T4	69
valid_sources[0x1d]	203486	1			T2	305		T4	51		T5	6
valid_sources[0x1e]	206359	1			T2	178		T4	52		T5	7
valid_sources[0x1f]	206751	1			T2	309		T4	41		T5	7
valid_sources[0x20]	197761	1			T2	206		T4	60		T5	1
valid_sources[0x21]	344646	1			T2	334		T4	46		T5	6
valid_sources[0x22]	217724	1			T2	358		T4	42		T5	6
valid_sources[0x23]	189465	1			T2	246		T4	39		T5	15
valid_sources[0x24]	295534	1			T2	442		T4	62		T5	2
valid_sources[0x25]	192872	1			T2	310		T3	1		T4	48
valid_sources[0x26]	228452	1			T2	326		T4	49		T5	1
valid_sources[0x27]	206483	1			T2	365		T4	36		T5	3
valid_sources[0x28]	196864	1			T2	217		T4	35		T5	5
valid_sources[0x29]	200764	1			T2	256		T4	36		T5	4
valid_sources[0x2a]	198903	1			T1	3		T2	161		T4	34
valid_sources[0x2b]	197115	1			T2	118		T4	44		T5	6
valid_sources[0x2c]	188723	1			T1	1		T2	220		T4	57
valid_sources[0x2d]	228831	1			T2	158		T4	36		T5	2
valid_sources[0x2e]	207002	1			T2	307		T4	45		T5	6
valid_sources[0x2f]	177683	1			T2	188		T3	1		T4	38
valid_sources[0x30]	194020	1			T2	258		T4	46		T5	7
valid_sources[0x31]	184196	1			T2	267		T4	38		T5	2
valid_sources[0x32]	187582	1			T2	362		T4	39		T5	2
valid_sources[0x33]	193390	1			T2	348		T4	45		T5	1
valid_sources[0x34]	378869	1			T2	433		T4	44		T5	4
valid_sources[0x35]	269947	1			T2	335		T4	40		T5	3
valid_sources[0x36]	218722	1			T2	229		T3	1		T4	50
valid_sources[0x37]	202774	1			T2	169		T4	50		T5	3
valid_sources[0x38]	216744	1			T2	259		T4	36		T5	8
valid_sources[0x39]	211411	1			T2	275		T4	57		T5	2
valid_sources[0x3a]	229442	1			T2	370		T4	34		T6	5
valid_sources[0x3b]	265172	1			T2	395		T4	37		T5	6
valid_sources[0x3c]	210345	1			T2	272		T4	25		T5	4
valid_sources[0x3d]	198942	1			T2	454		T4	55		T5	5
valid_sources[0x3e]	201368	1			T2	294		T4	56		T5	2
valid_sources[0x3f]	206638	1			T2	278		T4	62		T5	6
valid_sources[0x40]	201494	1			T2	284		T4	62		T5	10
valid_sources[0x41]	203633	1			T2	300		T4	46		T5	4
valid_sources[0x42]	206831	1			T2	292		T4	40		T5	2
valid_sources[0x43]	203808	1			T2	293		T4	49		T5	8
valid_sources[0x44]	193611	1			T2	329		T4	43		T5	9
valid_sources[0x45]	208590	1			T2	250		T4	50		T5	4
valid_sources[0x46]	192115	1			T2	237		T4	50		T6	6
valid_sources[0x47]	196961	1			T2	229		T3	1		T4	23
valid_sources[0x48]	191237	1			T2	234		T4	52		T5	14
valid_sources[0x49]	201394	1			T2	132		T4	38		T5	4
valid_sources[0x4a]	194388	1			T2	189		T4	48		T5	2
valid_sources[0x4b]	201176	1			T2	352		T4	40		T5	11
valid_sources[0x4c]	210009	1			T2	284		T4	41		T5	2
valid_sources[0x4d]	227646	1			T2	312		T4	39		T5	13
valid_sources[0x4e]	201014	1			T2	440		T4	49		T5	7
valid_sources[0x4f]	228147	1			T2	193		T4	55		T6	4
valid_sources[0x50]	240890	1			T2	267		T4	45		T6	2
valid_sources[0x51]	208421	1			T2	257		T4	45		T5	10
valid_sources[0x52]	201178	1			T2	221		T4	37		T6	3
valid_sources[0x53]	219105	1			T2	390		T4	52		T5	8
valid_sources[0x54]	202692	1			T2	461		T4	38		T6	5
valid_sources[0x55]	182129	1			T2	320		T4	49		T5	6
valid_sources[0x56]	188599	1			T2	320		T4	49		T5	2
valid_sources[0x57]	207515	1			T2	362		T4	37		T5	10
valid_sources[0x58]	206138	1			T2	292		T4	51		T5	3
valid_sources[0x59]	224981	1			T2	216		T4	53		T5	1
valid_sources[0x5a]	200853	1			T2	263		T4	51		T5	11
valid_sources[0x5b]	200198	1			T2	261		T4	39		T5	3
valid_sources[0x5c]	202947	1			T2	296		T4	36		T5	3
valid_sources[0x5d]	208465	1			T2	245		T4	50		T6	6
valid_sources[0x5e]	207556	1			T2	272		T4	41		T5	3
valid_sources[0x5f]	210193	1			T2	292		T4	43		T5	4
valid_sources[0x60]	222782	1			T2	353		T4	64		T5	6
valid_sources[0x61]	197403	1			T2	338		T4	37		T5	6
valid_sources[0x62]	192581	1			T2	383		T4	47		T6	5
valid_sources[0x63]	207899	1			T2	294		T4	52		T5	4
valid_sources[0x64]	204153	1			T2	260		T4	50		T5	9
valid_sources[0x65]	213010	1			T2	196		T4	49		T6	5
valid_sources[0x66]	203302	1			T2	254		T4	43		T5	6
valid_sources[0x67]	195713	1			T2	345		T4	41		T5	4
valid_sources[0x68]	194703	1			T2	357		T4	38		T6	6
valid_sources[0x69]	199025	1			T2	242		T4	46		T5	4
valid_sources[0x6a]	201868	1			T2	299		T4	37		T5	9
valid_sources[0x6b]	514079	1			T2	299		T4	57		T5	4
valid_sources[0x6c]	200882	1			T2	229		T4	39		T5	3
valid_sources[0x6d]	185413	1			T2	248		T4	52		T5	9
valid_sources[0x6e]	212308	1			T2	132		T4	42		T5	3
valid_sources[0x6f]	193821	1			T2	349		T4	55		T5	10
valid_sources[0x70]	202266	1			T2	307		T4	52		T5	2
valid_sources[0x71]	191417	1			T2	201		T4	38		T5	5
valid_sources[0x72]	192954	1			T2	411		T4	44		T6	6
valid_sources[0x73]	217005	1			T2	407		T4	60		T5	3
valid_sources[0x74]	301507	1			T2	141		T4	41		T5	2
valid_sources[0x75]	194097	1			T2	245		T4	45		T5	6
valid_sources[0x76]	197562	1			T2	438		T4	39		T5	7
valid_sources[0x77]	207787	1			T2	440		T3	1		T4	62
valid_sources[0x78]	208106	1			T2	103		T3	1		T4	32
valid_sources[0x79]	197819	1			T2	463		T4	49		T5	2
valid_sources[0x7a]	202941	1			T2	205		T4	32		T5	5
valid_sources[0x7b]	196957	1			T2	316		T3	1		T4	55
valid_sources[0x7c]	207186	1			T2	280		T3	1		T4	37
valid_sources[0x7d]	218074	1			T2	319		T3	1		T4	45
valid_sources[0x7e]	193401	1			T2	190		T4	55		T5	6
valid_sources[0x7f]	196730	1			T2	199		T4	43		T5	7
valid_sources[0x80]	196917	1			T2	290		T4	45		T5	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10194073

1

T1

1

T2

6260

T3

11

values[0x0]

all_enables

biggest_size

204255

1

T1

6

T2

238

T3

5

values[0x1]

all_enables

biggest_size

150285

1

T1

6

T2

142

T3

2