Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	369069111	0	0	0
ctrl_rd_A	369069111	2236	0	0
host_fifo_config_rd_A	369069111	4869	0	0
host_nack_handler_timeout_rd_A	369069111	1092	0	0
host_timeout_ctrl_rd_A	369069111	818	0	0
intr_enable_rd_A	369069111	3261	0	0
ovrd_rd_A	369069111	1725	0	0
target_fifo_config_rd_A	369069111	1019	0	0
target_id_rd_A	369069111	1300	0	0
target_timeout_ctrl_rd_A	369069111	924	0	0
timeout_ctrl_rd_A	369069111	1017	0	0
timing0_rd_A	369069111	995	0	0
timing1_rd_A	369069111	1028	0	0
timing2_rd_A	369069111	989	0	0
timing3_rd_A	369069111	921	0	0
timing4_rd_A	369069111	940	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	2236	0	0
T93	2310	15	0	0
T94	8558	166	0	0
T95	14498	340	0	0
T96	13259	37	0	0
T97	3623	7	0	0
T98	3376	49	0	0
T99	7087	85	0	0
T100	7659	9	0	0
T101	1215	12	0	0
T102	2150	30	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	4869	0	0
T16	133913	0	0	0
T36	6674	0	0	0
T37	7294	0	0	0
T82	0	132	0	0
T103	507892	183	0	0
T104	0	153	0	0
T105	0	200	0	0
T106	0	131	0	0
T107	0	238	0	0
T108	0	103	0	0
T109	0	430	0	0
T110	0	148	0	0
T111	0	142	0	0
T112	148343	0	0	0
T113	138450	0	0	0
T114	322410	0	0	0
T115	20261	0	0	0
T116	11112	0	0	0
T117	47597	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	1092	0	0
T93	2310	9	0	0
T94	8558	46	0	0
T95	14498	138	0	0
T96	13259	49	0	0
T97	3623	33	0	0
T98	3376	18	0	0
T99	7087	8	0	0
T100	7659	25	0	0
T101	1215	1	0	0
T118	1978	16	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	818	0	0
T94	8558	45	0	0
T95	14498	98	0	0
T96	13259	40	0	0
T98	3376	16	0	0
T99	7087	29	0	0
T100	7659	17	0	0
T102	2150	6	0	0
T118	1978	1	0	0
T119	6601	19	0	0
T120	3547	29	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	3261	0	0
T82	0	11	0	0
T93	0	18	0	0
T94	0	354	0	0
T95	0	485	0	0
T106	127343	63	0	0
T121	0	59	0	0
T122	0	11	0	0
T123	0	17	0	0
T124	0	26	0	0
T125	0	11	0	0
T126	10481	0	0	0
T127	131252	0	0	0
T128	97095	0	0	0
T129	13470	0	0	0
T130	18997	0	0	0
T131	99934	0	0	0
T132	82235	0	0	0
T133	160613	0	0	0
T134	370111	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	1725	0	0
T3	2215	34	0	0
T4	117039	0	0	0
T5	93716	0	0	0
T6	83949	0	0	0
T7	64692	0	0	0
T8	17886	0	0	0
T9	1681	0	0	0
T10	97016	0	0	0
T27	96177	0	0	0
T28	1870	0	0	0
T88	0	58	0	0
T135	0	59	0	0
T136	0	32	0	0
T137	0	70	0	0
T138	0	55	0	0
T139	0	87	0	0
T140	0	65	0	0
T141	0	59	0	0
T142	0	38	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	1019	0	0
T93	2310	8	0	0
T94	8558	47	0	0
T95	14498	109	0	0
T96	13259	43	0	0
T97	3623	4	0	0
T98	3376	19	0	0
T99	7087	36	0	0
T100	7659	22	0	0
T102	2150	25	0	0
T118	1978	5	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	1300	0	0
T94	8558	101	0	0
T95	14498	147	0	0
T96	13259	20	0	0
T97	3623	7	0	0
T98	3376	22	0	0
T99	7087	45	0	0
T100	7659	15	0	0
T101	1215	12	0	0
T102	2150	23	0	0
T118	1978	10	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	924	0	0
T93	2310	9	0	0
T94	8558	57	0	0
T95	14498	102	0	0
T96	13259	22	0	0
T97	3623	8	0	0
T98	3376	22	0	0
T99	7087	61	0	0
T100	7659	15	0	0
T102	2150	8	0	0
T118	1978	6	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	1017	0	0
T94	8558	85	0	0
T95	14498	93	0	0
T96	13259	65	0	0
T98	3376	27	0	0
T99	7087	38	0	0
T100	7659	1	0	0
T101	1215	2	0	0
T102	2150	10	0	0
T118	1978	11	0	0
T119	6601	40	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	995	0	0
T94	8558	47	0	0
T95	14498	132	0	0
T96	13259	23	0	0
T97	3623	12	0	0
T98	3376	19	0	0
T99	7087	37	0	0
T100	7659	22	0	0
T101	1215	7	0	0
T118	1978	8	0	0
T119	6601	26	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	1028	0	0
T93	2310	2	0	0
T94	8558	51	0	0
T95	14498	107	0	0
T96	13259	12	0	0
T97	3623	1	0	0
T98	3376	25	0	0
T99	7087	25	0	0
T100	7659	58	0	0
T101	1215	5	0	0
T118	1978	7	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	989	0	0
T93	2310	7	0	0
T94	8558	63	0	0
T95	14498	115	0	0
T96	13259	36	0	0
T97	3623	4	0	0
T98	3376	13	0	0
T99	7087	58	0	0
T100	7659	37	0	0
T101	1215	7	0	0
T118	1978	8	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	921	0	0
T94	8558	44	0	0
T95	14498	90	0	0
T96	13259	25	0	0
T97	3623	13	0	0
T98	3376	26	0	0
T99	7087	36	0	0
T100	7659	11	0	0
T101	1215	14	0	0
T102	2150	8	0	0
T118	1978	14	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369069111	940	0	0
T94	8558	42	0	0
T95	14498	145	0	0
T96	13259	19	0	0
T97	3623	8	0	0
T98	3376	14	0	0
T99	7087	32	0	0
T100	7659	33	0	0
T102	2150	17	0	0
T119	6601	23	0	0
T120	3547	19	0	0