Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

154946

1

T1

232

T5

454

T9

79

ack

14392

1

T1

40

T4

49

T5

9

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	615	1			T5	2		T24	2		T33	3
high	34590	1			T1	50		T4	5		T5	94
med	62674	1			T1	103		T4	8		T5	194
sml	70796	1			T1	119		T4	36		T5	172
all_zero	663	1			T5	1		T24	3		T63	3

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84649

1

T1

141

T4

24

T5

231

auto[1]

84689

1

T1

131

T4

25

T5

232

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116955

1

T1

200

T4

35

T5

317

auto[1]

52383

1

T1

72

T4

14

T5

146

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161827

1

T1

255

T4

18

T5

460

auto[1]

7511

1

T1

17

T4

31

T5

3

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159514

1

T1

237

T4

31

T5

456

auto[1]

9824

1

T1

35

T4

18

T5

7

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160468

1

T1

238

T4

32

T5

459

auto[1]

8870

1

T1

34

T4

17

T5

4

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84649

1

T1

141

T4

24

T5

231

auto[1]

84689

1

T1

131

T4

25

T5

232

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116955

1

T1

200

T4

35

T5

317

auto[1]

52383

1

T1

72

T4

14

T5

146

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161827

1

T1

255

T4

18

T5

460

auto[1]

7511

1

T1

17

T4

31

T5

3

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159514

1

T1

237

T4

31

T5

456

auto[1]

9824

1

T1

35

T4

18

T5

7

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160468

1

T1

238

T4

32

T5

459

auto[1]

8870

1

T1

34

T4

17

T5

4

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T290

1

T291

1

T292

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T293

1

T294

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T295

1

T50

1

T45

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

257

1

T1

3

T193

2

T296

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

129

1

T193

3

T296

2

T76

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

117

1

T1

1

T24

3

T33

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

558

1

T1

6

T5

1

T24

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

275

1

T24

4

T63

1

T33

5

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

265

1

T1

2

T24

1

T63

2

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

506

1

T1

3

T5

1

T24

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

251

1

T1

1

T5

1

T24

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

255

1

T1

1

T5

1

T24

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

10

1

T290

1

T61

1

T297

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

6

1

T291

1

T106

1

T45

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T175

1

T77

1

T298

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	49653	1			T1	70		T5	146		T9	25
write_address_byte	9824	1			T1	35		T4	18		T5	7
read_with_ack	2168	1			T4	14		T5	1		T59	18
read_with_nack	5343	1			T1	17		T4	17		T5	2
stop_byte	8870	1			T1	34		T4	17		T5	4
write_address_byte_nak	4791	1			T1	27		T5	4		T24	20
data_byte_nack	154946	1			T1	232		T5	454		T9	79
stop_byte_nack	5297	1			T1	27		T5	3		T9	1
nakok_byte_nack	77492	1			T1	107		T5	227		T9	37
nakok_addr_byte_nack	2392	1			T1	14		T5	1		T24	12