Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46565781	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12253566

1

T1

6201

T2

181

T3

47

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	58088341	1			T1	46373		T2	17640		T3	62
values[0x0]	364740	1			T1	388		T2	246		T3	57
values[0x1]	366266	1			T1	448		T2	211		T3	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33247914	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

25571433

1

T1

19063

T2

6821

T3

81

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	218007	1			T1	188		T2	66		T4	86
valid_sources[0x01]	209115	1			T1	182		T2	93		T4	55
valid_sources[0x02]	193380	1			T1	207		T2	72		T4	65
valid_sources[0x03]	217027	1			T1	136		T2	73		T4	77
valid_sources[0x04]	214859	1			T1	154		T2	62		T4	59
valid_sources[0x05]	206339	1			T1	170		T2	72		T4	63
valid_sources[0x06]	217228	1			T1	213		T2	61		T4	63
valid_sources[0x07]	212320	1			T1	205		T2	62		T3	2
valid_sources[0x08]	227193	1			T1	160		T2	75		T4	58
valid_sources[0x09]	212666	1			T1	140		T2	79		T4	76
valid_sources[0x0a]	212326	1			T1	171		T2	57		T4	72
valid_sources[0x0b]	213367	1			T1	168		T2	78		T4	79
valid_sources[0x0c]	487515	1			T1	157		T2	70		T4	49
valid_sources[0x0d]	209339	1			T1	196		T2	61		T4	64
valid_sources[0x0e]	195144	1			T1	191		T2	66		T4	65
valid_sources[0x0f]	231755	1			T1	205		T2	62		T4	63
valid_sources[0x10]	228766	1			T1	226		T2	77		T4	70
valid_sources[0x11]	214908	1			T1	141		T2	62		T4	65
valid_sources[0x12]	199661	1			T1	176		T2	72		T4	71
valid_sources[0x13]	217035	1			T1	242		T2	80		T4	82
valid_sources[0x14]	196158	1			T1	156		T2	77		T4	57
valid_sources[0x15]	464903	1			T1	182		T2	58		T4	83
valid_sources[0x16]	209758	1			T1	203		T2	60		T4	54
valid_sources[0x17]	672562	1			T1	190		T2	67		T4	65
valid_sources[0x18]	209040	1			T1	136		T2	69		T4	73
valid_sources[0x19]	202703	1			T1	150		T2	67		T3	1
valid_sources[0x1a]	222184	1			T1	191		T2	50		T4	56
valid_sources[0x1b]	225693	1			T1	179		T2	64		T4	72
valid_sources[0x1c]	215720	1			T1	252		T2	81		T4	76
valid_sources[0x1d]	236308	1			T1	215		T2	74		T4	75
valid_sources[0x1e]	215164	1			T1	178		T2	91		T4	55
valid_sources[0x1f]	211576	1			T1	151		T2	84		T4	62
valid_sources[0x20]	204059	1			T1	160		T2	66		T4	70
valid_sources[0x21]	196763	1			T1	183		T2	77		T4	79
valid_sources[0x22]	226402	1			T1	177		T2	74		T4	66
valid_sources[0x23]	202293	1			T1	217		T2	74		T4	72
valid_sources[0x24]	212673	1			T1	146		T2	78		T4	66
valid_sources[0x25]	202636	1			T1	181		T2	74		T4	58
valid_sources[0x26]	207979	1			T1	137		T2	84		T4	56
valid_sources[0x27]	203363	1			T1	215		T2	73		T4	79
valid_sources[0x28]	228987	1			T1	243		T2	70		T4	51
valid_sources[0x29]	212069	1			T1	229		T2	70		T4	63
valid_sources[0x2a]	206509	1			T1	220		T2	73		T4	67
valid_sources[0x2b]	206001	1			T1	180		T2	76		T4	72
valid_sources[0x2c]	219016	1			T1	187		T2	60		T3	59
valid_sources[0x2d]	204670	1			T1	197		T2	68		T4	75
valid_sources[0x2e]	200522	1			T1	167		T2	82		T4	67
valid_sources[0x2f]	209109	1			T1	181		T2	59		T4	61
valid_sources[0x30]	318982	1			T1	174		T2	73		T4	52
valid_sources[0x31]	197703	1			T1	237		T2	74		T4	69
valid_sources[0x32]	192823	1			T1	208		T2	67		T4	85
valid_sources[0x33]	291078	1			T1	161		T2	58		T4	60
valid_sources[0x34]	214220	1			T1	199		T2	80		T4	67
valid_sources[0x35]	211546	1			T1	207		T2	83		T4	74
valid_sources[0x36]	207913	1			T1	192		T2	81		T4	51
valid_sources[0x37]	188686	1			T1	154		T2	81		T4	69
valid_sources[0x38]	200993	1			T1	164		T2	74		T4	79
valid_sources[0x39]	213691	1			T1	175		T2	58		T4	69
valid_sources[0x3a]	193553	1			T1	165		T2	65		T4	58
valid_sources[0x3b]	209545	1			T1	186		T2	68		T4	62
valid_sources[0x3c]	204230	1			T1	225		T2	73		T4	64
valid_sources[0x3d]	207820	1			T1	195		T2	91		T4	59
valid_sources[0x3e]	204965	1			T1	210		T2	68		T4	76
valid_sources[0x3f]	223037	1			T1	196		T2	65		T4	75
valid_sources[0x40]	194007	1			T1	153		T2	71		T4	64
valid_sources[0x41]	209920	1			T1	157		T2	72		T4	64
valid_sources[0x42]	215060	1			T1	160		T2	54		T4	62
valid_sources[0x43]	203429	1			T1	170		T2	81		T4	65
valid_sources[0x44]	222774	1			T1	143		T2	84		T4	59
valid_sources[0x45]	195006	1			T1	284		T2	59		T4	68
valid_sources[0x46]	206301	1			T1	113		T2	73		T4	59
valid_sources[0x47]	217878	1			T1	234		T2	87		T4	55
valid_sources[0x48]	208254	1			T1	215		T2	58		T4	58
valid_sources[0x49]	203845	1			T1	248		T2	60		T4	57
valid_sources[0x4a]	220005	1			T1	121		T2	76		T4	65
valid_sources[0x4b]	203356	1			T1	254		T2	92		T4	56
valid_sources[0x4c]	205345	1			T1	216		T2	67		T4	56
valid_sources[0x4d]	200401	1			T1	167		T2	84		T4	65
valid_sources[0x4e]	212684	1			T1	227		T2	64		T4	61
valid_sources[0x4f]	207533	1			T1	151		T2	65		T4	67
valid_sources[0x50]	220799	1			T1	190		T2	68		T4	77
valid_sources[0x51]	211221	1			T1	171		T2	74		T4	67
valid_sources[0x52]	230642	1			T1	129		T2	65		T4	72
valid_sources[0x53]	200593	1			T1	111		T2	77		T4	71
valid_sources[0x54]	201177	1			T1	280		T2	71		T4	73
valid_sources[0x55]	282314	1			T1	210		T2	74		T4	66
valid_sources[0x56]	227758	1			T1	158		T2	62		T4	65
valid_sources[0x57]	226141	1			T1	161		T2	75		T4	56
valid_sources[0x58]	200707	1			T1	138		T2	51		T4	73
valid_sources[0x59]	204553	1			T1	249		T2	66		T4	64
valid_sources[0x5a]	311824	1			T1	192		T2	77		T4	64
valid_sources[0x5b]	333100	1			T1	150		T2	59		T4	63
valid_sources[0x5c]	214672	1			T1	183		T2	75		T4	63
valid_sources[0x5d]	206777	1			T1	154		T2	49		T4	66
valid_sources[0x5e]	200343	1			T1	239		T2	60		T4	72
valid_sources[0x5f]	224045	1			T1	219		T2	72		T4	73
valid_sources[0x60]	204788	1			T1	138		T2	65		T4	66
valid_sources[0x61]	189797	1			T1	218		T2	67		T4	63
valid_sources[0x62]	851490	1			T1	125		T2	79		T4	53
valid_sources[0x63]	215871	1			T1	139		T2	62		T4	53
valid_sources[0x64]	195816	1			T1	118		T2	59		T4	65
valid_sources[0x65]	228140	1			T1	117		T2	87		T4	67
valid_sources[0x66]	202444	1			T1	227		T2	73		T4	55
valid_sources[0x67]	210691	1			T1	244		T2	72		T4	68
valid_sources[0x68]	197097	1			T1	249		T2	69		T4	73
valid_sources[0x69]	203895	1			T1	152		T2	70		T4	57
valid_sources[0x6a]	212370	1			T1	228		T2	55		T4	53
valid_sources[0x6b]	200138	1			T1	179		T2	69		T4	68
valid_sources[0x6c]	202237	1			T1	238		T2	87		T4	74
valid_sources[0x6d]	201404	1			T1	186		T2	69		T4	61
valid_sources[0x6e]	210679	1			T1	151		T2	76		T4	63
valid_sources[0x6f]	218906	1			T1	208		T2	84		T4	68
valid_sources[0x70]	230869	1			T1	149		T2	74		T4	65
valid_sources[0x71]	246246	1			T1	143		T2	72		T4	86
valid_sources[0x72]	206710	1			T1	209		T2	85		T4	70
valid_sources[0x73]	200369	1			T1	254		T2	63		T4	55
valid_sources[0x74]	211390	1			T1	145		T2	66		T4	64
valid_sources[0x75]	196978	1			T1	289		T2	80		T4	60
valid_sources[0x76]	200217	1			T1	167		T2	77		T4	55
valid_sources[0x77]	249041	1			T1	167		T2	56		T4	52
valid_sources[0x78]	221521	1			T1	152		T2	77		T4	67
valid_sources[0x79]	208483	1			T1	139		T2	75		T4	64
valid_sources[0x7a]	200750	1			T1	160		T2	76		T4	58
valid_sources[0x7b]	207555	1			T1	204		T2	70		T4	70
valid_sources[0x7c]	939483	1			T1	240		T2	78		T4	81
valid_sources[0x7d]	244485	1			T1	228		T2	52		T4	63
valid_sources[0x7e]	196987	1			T1	265		T2	71		T4	62
valid_sources[0x7f]	209776	1			T1	259		T2	79		T4	69
valid_sources[0x80]	204935	1			T1	166		T2	54		T4	68

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

11899780

1

T1

5686

T2

28

T3

14

values[0x0]

all_enables

biggest_size

204497

1

T1

267

T2

106

T3

24

values[0x1]

all_enables

biggest_size

149289

1

T1

248

T2

47

T3

9