Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

156103

1

T6

161

T30

1

T42

8

ack

14249

1

T3

53

T6

18

T7

27

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	662	1			T85	1		T232	1		T56	1
high	35015	1			T3	6		T6	59		T7	1
med	63212	1			T3	6		T6	53		T7	3
sml	70767	1			T3	41		T6	67		T7	23
all_zero	696	1			T35	1		T43	1		T56	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84762

1

T3

29

T6

96

T7

9

auto[1]

85590

1

T3

24

T6

83

T7

18

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117142

1

T3

37

T6

122

T7

17

auto[1]

53210

1

T3

16

T6

57

T7

10

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162789

1

T3

19

T6

179

T7

9

auto[1]

7563

1

T3

34

T7

18

T31

10

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160645

1

T3

34

T6

161

T7

18

auto[1]

9707

1

T3

19

T6

18

T7

9

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161601

1

T3

35

T6

161

T7

19

auto[1]

8751

1

T3

18

T6

18

T7

8

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84762

1

T3

29

T6

96

T7

9

auto[1]

85590

1

T3

24

T6

83

T7

18

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117142

1

T3

37

T6

122

T7

17

auto[1]

53210

1

T3

16

T6

57

T7

10

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162789

1

T3

19

T6

179

T7

9

auto[1]

7563

1

T3

34

T7

18

T31

10

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160645

1

T3

34

T6

161

T7

18

auto[1]

9707

1

T3

19

T6

18

T7

9

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161601

1

T3

35

T6

161

T7

19

auto[1]

8751

1

T3

18

T6

18

T7

8

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

3

1

T77

1

T280

1

T281

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T50

1

T250

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T282

1

T283

1

T284

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

283

1

T85

1

T39

1

T56

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

105

1

T72

1

T73

1

T37

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

163

1

T56

1

T72

1

T73

4

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

525

1

T85

3

T36

1

T232

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

259

1

T85

1

T232

1

T56

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

243

1

T85

1

T232

1

T56

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

469

1

T85

4

T232

1

T56

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

246

1

T43

1

T85

1

T232

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

277

1

T85

3

T56

1

T73

3

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

11

1

T73

1

T37

1

T77

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

5

1

T56

1

T109

1

T127

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T110

1

T285

1

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	49786	1			T6	56		T43	61		T46	7
write_address_byte	9707	1			T3	19		T6	18		T7	9
read_with_ack	2266	1			T3	16		T7	10		T42	5
read_with_nack	5297	1			T3	18		T7	8		T31	10
stop_byte	8751	1			T3	18		T6	18		T7	8
write_address_byte_nak	4731	1			T42	2		T43	3		T85	19
data_byte_nack	156103	1			T6	161		T30	1		T42	8
stop_byte_nack	5212	1			T6	18		T30	1		T42	1
nakok_byte_nack	78469	1			T6	77		T30	1		T42	3
nakok_addr_byte_nack	2346	1			T42	1		T43	1		T85	7