Group : i2c_env_pkg::i2c_operating_mode_cg
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Group : i2c_env_pkg::i2c_operating_mode_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
46.43 46.43 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.openting_mode_cg 46.43 1 100 1 64 64




Group Instance : i2c_env_pkg.openting_mode_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
46.43 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.openting_mode_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 5 9 64.29
Crosses 14 10 4 28.57


Variables for Group Instance i2c_env_pkg.openting_mode_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_ip_mode 2 0 2 100.00 100 1 1 0
cp_scl_frequency 6 5 1 16.67 100 1 1 0
cp_tb_mode 2 0 2 100.00 100 1 1 0
ip_mode 2 0 2 100.00 100 1 1 2
tb_mode 2 0 2 100.00 100 1 1 2


Crosses for Group Instance i2c_env_pkg.openting_mode_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_mode_cross 2 0 2 100.00 100 1 1 0
cp_ip_mode_x_frequency 12 10 2 16.67 100 1 1 0


Summary for Variable cp_ip_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_ip_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
target 633 1 T4 1 T5 1 T9 1
host 1564 1 T1 1 T3 1 T6 1



Summary for Variable cp_scl_frequency

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 5 1 16.67


User Defined Bins for cp_scl_frequency

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
fast_plus_mode[0] 0 1 1
fast_plus_mode[1] 0 1 1
fast_mode[0] 0 1 1
fast_mode[1] 0 1 1
standard_mode[1] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
standard_mode[0] 2197 1 T1 1 T3 1 T4 1



Summary for Variable cp_tb_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_tb_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
target 1564 1 T1 1 T3 1 T6 1
host 633 1 T4 1 T5 1 T9 1



Summary for Variable ip_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for ip_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 633 1 T4 1 T5 1 T9 1
auto[1] 1564 1 T1 1 T3 1 T6 1



Summary for Variable tb_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for tb_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1564 1 T1 1 T3 1 T6 1
auto[1] 633 1 T4 1 T5 1 T9 1



Summary for Cross cp_mode_cross

Samples crossed: ip_mode tb_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 2 0 2 100.00


User Defined Cross Bins for cp_mode_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
both_host 0 Excluded
both_target 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
dut_host_tb_target 1564 1 T1 1 T3 1 T6 1
dut_target_tb_host 633 1 T4 1 T5 1 T9 1



Summary for Cross cp_ip_mode_x_frequency

Samples crossed: cp_ip_mode cp_scl_frequency
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 12 10 2 16.67 10


Automatically Generated Cross Bins for cp_ip_mode_x_frequency

Element holes
cp_ip_modecp_scl_frequencyCOUNTAT LEASTNUMBERSTATUS
* [fast_plus_mode[0] , fast_plus_mode[1] , fast_mode[0] , fast_mode[1]] -- -- 8
* [standard_mode[1]] -- -- 2


Covered bins
cp_ip_modecp_scl_frequencyCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
target standard_mode[0] 633 1 T4 1 T5 1 T9 1
host standard_mode[0] 1564 1 T1 1 T3 1 T6 1

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