Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44921332	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10607861

1

T1

12

T2

3

T3

7366

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54778543	1			T1	29		T2	1		T3	25570
values[0x0]	374623	1			T1	12		T2	3		T3	541
values[0x1]	376027	1			T1	15		T2	1		T3	516

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32055839	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

23473354

1

T1

25

T2

3

T3

12904

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	176331	1			T3	172		T4	4		T5	88
valid_sources[0x01]	198134	1			T3	190		T4	5		T5	76
valid_sources[0x02]	206279	1			T3	79		T4	8		T5	88
valid_sources[0x03]	302530	1			T3	34		T4	19		T5	50
valid_sources[0x04]	198595	1			T3	179		T4	7		T5	97
valid_sources[0x05]	198759	1			T3	181		T4	1		T5	110
valid_sources[0x06]	357709	1			T3	273		T4	5		T5	96
valid_sources[0x07]	194475	1			T3	35		T4	4		T5	67
valid_sources[0x08]	196949	1			T3	133		T4	2		T5	84
valid_sources[0x09]	216172	1			T3	99		T4	12		T5	81
valid_sources[0x0a]	190328	1			T3	72		T4	2		T5	68
valid_sources[0x0b]	187835	1			T3	58		T4	2		T5	61
valid_sources[0x0c]	203150	1			T3	30		T4	7		T5	75
valid_sources[0x0d]	198886	1			T3	144		T4	4		T5	108
valid_sources[0x0e]	195590	1			T3	148		T4	3		T5	85
valid_sources[0x0f]	215689	1			T3	81		T4	4		T5	60
valid_sources[0x10]	202481	1			T3	123		T5	96		T6	55
valid_sources[0x11]	432468	1			T3	138		T4	3		T5	84
valid_sources[0x12]	208183	1			T3	65		T4	12		T5	96
valid_sources[0x13]	195058	1			T3	29		T4	14		T5	76
valid_sources[0x14]	178085	1			T2	2		T3	131		T4	5
valid_sources[0x15]	209974	1			T3	41		T4	7		T5	59
valid_sources[0x16]	181029	1			T3	97		T4	5		T5	63
valid_sources[0x17]	189201	1			T3	142		T4	1		T5	74
valid_sources[0x18]	593729	1			T3	133		T4	6		T5	126
valid_sources[0x19]	199793	1			T3	109		T4	9		T5	62
valid_sources[0x1a]	188896	1			T3	104		T4	15		T5	83
valid_sources[0x1b]	199021	1			T3	136		T4	4		T5	77
valid_sources[0x1c]	190269	1			T3	82		T4	2		T5	100
valid_sources[0x1d]	197863	1			T3	121		T4	3		T5	81
valid_sources[0x1e]	184352	1			T3	159		T4	14		T5	90
valid_sources[0x1f]	226559	1			T3	88		T4	3		T5	74
valid_sources[0x20]	198512	1			T3	120		T4	4		T5	75
valid_sources[0x21]	205205	1			T3	191		T4	1		T5	97
valid_sources[0x22]	198012	1			T3	159		T4	8		T5	95
valid_sources[0x23]	192737	1			T3	95		T4	7		T5	87
valid_sources[0x24]	195549	1			T3	130		T4	7		T5	92
valid_sources[0x25]	194098	1			T3	97		T4	1		T5	103
valid_sources[0x26]	204885	1			T3	57		T4	24		T5	69
valid_sources[0x27]	497447	1			T3	165		T4	2		T5	78
valid_sources[0x28]	229424	1			T3	97		T4	6		T5	74
valid_sources[0x29]	210570	1			T3	111		T4	1		T5	67
valid_sources[0x2a]	202088	1			T3	87		T4	3		T5	105
valid_sources[0x2b]	197614	1			T3	70		T4	3		T5	78
valid_sources[0x2c]	212672	1			T3	60		T4	2		T5	59
valid_sources[0x2d]	206263	1			T3	43		T4	6		T5	103
valid_sources[0x2e]	193037	1			T3	87		T4	1		T5	82
valid_sources[0x2f]	211983	1			T3	203		T4	1		T5	82
valid_sources[0x30]	206945	1			T3	86		T4	7		T5	99
valid_sources[0x31]	191101	1			T3	106		T4	8		T5	77
valid_sources[0x32]	205014	1			T3	77		T5	107		T6	23
valid_sources[0x33]	212938	1			T3	54		T4	6		T5	54
valid_sources[0x34]	197067	1			T3	184		T4	2		T5	81
valid_sources[0x35]	197977	1			T3	106		T4	7		T5	88
valid_sources[0x36]	198286	1			T3	77		T4	9		T5	103
valid_sources[0x37]	204565	1			T3	142		T4	5		T5	95
valid_sources[0x38]	423398	1			T3	138		T4	4		T5	54
valid_sources[0x39]	198195	1			T3	105		T5	81		T6	101
valid_sources[0x3a]	227402	1			T3	53		T4	10		T5	97
valid_sources[0x3b]	192419	1			T3	72		T4	2		T5	82
valid_sources[0x3c]	201998	1			T3	64		T4	8		T5	65
valid_sources[0x3d]	212041	1			T3	211		T4	1		T5	110
valid_sources[0x3e]	208826	1			T3	151		T5	82		T6	47
valid_sources[0x3f]	213432	1			T3	155		T5	71		T6	73
valid_sources[0x40]	646775	1			T3	166		T4	12		T5	98
valid_sources[0x41]	188302	1			T3	77		T4	2		T5	39
valid_sources[0x42]	207698	1			T3	93		T4	8		T5	97
valid_sources[0x43]	200065	1			T3	72		T4	3		T5	104
valid_sources[0x44]	195690	1			T3	29		T4	5		T5	80
valid_sources[0x45]	200189	1			T3	67		T4	7		T5	83
valid_sources[0x46]	211192	1			T3	114		T4	12		T5	69
valid_sources[0x47]	196792	1			T3	32		T4	1		T5	86
valid_sources[0x48]	187512	1			T3	105		T4	8		T5	66
valid_sources[0x49]	195397	1			T3	65		T5	84		T6	23
valid_sources[0x4a]	569960	1			T3	64		T4	4		T5	86
valid_sources[0x4b]	195923	1			T3	116		T4	1		T5	81
valid_sources[0x4c]	183569	1			T3	164		T4	4		T5	93
valid_sources[0x4d]	188530	1			T3	196		T4	7		T5	80
valid_sources[0x4e]	208289	1			T3	157		T4	2		T5	71
valid_sources[0x4f]	227857	1			T3	41		T4	7		T5	63
valid_sources[0x50]	205088	1			T3	111		T4	7		T5	62
valid_sources[0x51]	248019	1			T3	122		T4	4		T5	67
valid_sources[0x52]	196417	1			T3	146		T4	2		T5	84
valid_sources[0x53]	219142	1			T3	72		T4	5		T5	83
valid_sources[0x54]	191519	1			T3	42		T4	4		T5	62
valid_sources[0x55]	201188	1			T3	69		T4	1		T5	131
valid_sources[0x56]	185279	1			T3	85		T4	8		T5	86
valid_sources[0x57]	197593	1			T3	96		T4	12		T5	126
valid_sources[0x58]	201652	1			T3	70		T4	3		T5	80
valid_sources[0x59]	200354	1			T3	45		T4	1		T5	59
valid_sources[0x5a]	231097	1			T3	71		T4	4		T5	90
valid_sources[0x5b]	205018	1			T3	114		T4	12		T5	104
valid_sources[0x5c]	215657	1			T3	158		T4	2		T5	80
valid_sources[0x5d]	202157	1			T3	120		T4	4		T5	66
valid_sources[0x5e]	262706	1			T3	119		T4	4		T5	60
valid_sources[0x5f]	179103	1			T3	105		T4	5		T5	81
valid_sources[0x60]	194987	1			T3	89		T4	7		T5	125
valid_sources[0x61]	207502	1			T3	67		T4	2		T5	126
valid_sources[0x62]	200909	1			T3	116		T4	9		T5	69
valid_sources[0x63]	205730	1			T3	165		T4	3		T5	74
valid_sources[0x64]	215774	1			T3	43		T4	6		T5	70
valid_sources[0x65]	208136	1			T3	72		T4	6		T5	87
valid_sources[0x66]	206916	1			T3	22		T4	6		T5	59
valid_sources[0x67]	202091	1			T3	98		T4	3		T5	72
valid_sources[0x68]	278222	1			T3	66		T4	11		T5	71
valid_sources[0x69]	221235	1			T3	137		T4	9		T5	65
valid_sources[0x6a]	201577	1			T3	133		T4	7		T5	89
valid_sources[0x6b]	197708	1			T3	112		T4	2		T5	92
valid_sources[0x6c]	186445	1			T3	75		T4	7		T5	116
valid_sources[0x6d]	197030	1			T3	80		T4	6		T5	73
valid_sources[0x6e]	194105	1			T3	57		T4	2		T5	103
valid_sources[0x6f]	197946	1			T3	88		T4	15		T5	72
valid_sources[0x70]	198513	1			T3	60		T4	1		T5	85
valid_sources[0x71]	193806	1			T3	106		T4	6		T5	91
valid_sources[0x72]	191033	1			T3	120		T4	4		T5	85
valid_sources[0x73]	188866	1			T3	96		T4	1		T5	88
valid_sources[0x74]	196776	1			T3	116		T5	48		T6	49
valid_sources[0x75]	200189	1			T3	58		T4	7		T5	74
valid_sources[0x76]	237911	1			T3	93		T4	5		T5	80
valid_sources[0x77]	188301	1			T3	160		T4	8		T5	86
valid_sources[0x78]	200265	1			T3	161		T4	8		T5	99
valid_sources[0x79]	221278	1			T3	120		T4	5		T5	74
valid_sources[0x7a]	272358	1			T3	103		T4	6		T5	55
valid_sources[0x7b]	200378	1			T3	121		T4	3		T5	96
valid_sources[0x7c]	183651	1			T3	95		T4	3		T5	74
valid_sources[0x7d]	200367	1			T3	136		T5	83		T6	55
valid_sources[0x7e]	250474	1			T3	128		T4	6		T5	48
valid_sources[0x7f]	195839	1			T3	48		T4	7		T5	80
valid_sources[0x80]	190141	1			T3	79		T4	4		T5	87

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10247448

1

T1

1

T3

6708

T4

198

values[0x0]

all_enables

biggest_size

208626

1

T1

8

T2

3

T3

357

values[0x1]

all_enables

biggest_size

151787

1

T1

3

T3

301

T4

53