Unified Coverage Report :: Group :: i2c_env_pkg::i2c_b2b_txn_cg

Group : i2c_env_pkg::i2c_b2b_txn_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	87.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.b2b_txn_target_cg	75.00	1	100	1	64	64
i2c_env_pkg.b2b_txn_host_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.b2b_txn_target_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_target_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	2	6	75.00

Variables for Group Instance i2c_env_pkg.b2b_txn_target_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	2	6	75.00	100	1	1	0

---

Group Instance : i2c_env_pkg.b2b_txn_host_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_host_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_host_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	2	6	75.00

User Defined Bins for B2B_txn_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
write_after_read_same_addr	0	1	1
read_after_write_same_addr	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	29	1			T71	1		T291	1		T292	1
b2b_read_same_addr	232	1			T5	1		T9	1		T24	1
write_after_read_different_addr	51	1			T4	1		T9	1		T16	1
read_after_write_different_addr	47	1			T13	1		T92	1		T293	2
b2b_write_different_addr	41	1			T27	1		T249	2		T294	1
b2b_write_same_addr	231	1			T26	1		T28	1		T86	1

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	3364	1			T3	13		T6	9		T7	6
b2b_read_same_addr	285	1			T42	1		T35	1		T43	1
write_after_read_different_addr	3323	1			T3	10		T6	4		T7	7
write_after_read_same_addr	52	1			T295	2		T187	1		T37	1
read_after_write_different_addr	3318	1			T3	10		T6	4		T7	6
read_after_write_same_addr	46	1			T7	1		T46	1		T56	1
b2b_write_different_addr	3267	1			T3	19		T7	6		T31	7
b2b_write_same_addr	255	1			T39	1		T40	1		T72	2