Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	385119232	0	0	0
ctrl_rd_A	385119232	2070	0	0
host_fifo_config_rd_A	385119232	5379	0	0
host_nack_handler_timeout_rd_A	385119232	1224	0	0
host_timeout_ctrl_rd_A	385119232	1167	0	0
intr_enable_rd_A	385119232	3321	0	0
ovrd_rd_A	385119232	1875	0	0
target_fifo_config_rd_A	385119232	1284	0	0
target_id_rd_A	385119232	1521	0	0
target_timeout_ctrl_rd_A	385119232	1295	0	0
timeout_ctrl_rd_A	385119232	1267	0	0
timing0_rd_A	385119232	1207	0	0
timing1_rd_A	385119232	1286	0	0
timing2_rd_A	385119232	1323	0	0
timing3_rd_A	385119232	1325	0	0
timing4_rd_A	385119232	1160	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	2070	0	0
T95	1697	2	0	0
T96	1977	5	0	0
T97	2984	28	0	0
T98	3431	4	0	0
T99	1548	8	0	0
T100	4143	25	0	0
T101	2960	13	0	0
T102	14059	405	0	0
T103	8973	183	0	0
T104	2480	35	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	5379	0	0
T60	834981	0	0	0
T105	282578	121	0	0
T106	261454	60	0	0
T107	0	130	0	0
T108	0	107	0	0
T109	0	90	0	0
T110	0	292	0	0
T111	0	328	0	0
T112	0	143	0	0
T113	0	132	0	0
T114	0	123	0	0
T115	52133	0	0	0
T116	101906	0	0	0
T117	14225	0	0	0
T118	7927	0	0	0
T119	21745	0	0	0
T120	815534	0	0	0
T121	88796	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	1224	0	0
T95	1697	9	0	0
T97	2984	17	0	0
T98	3431	11	0	0
T99	1548	1	0	0
T100	4143	47	0	0
T101	2960	6	0	0
T102	14059	100	0	0
T122	1199	3	0	0
T123	1898	3	0	0
T124	2253	10	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	1167	0	0
T95	1697	6	0	0
T96	1977	6	0	0
T97	2984	2	0	0
T98	3431	6	0	0
T100	4143	34	0	0
T101	2960	3	0	0
T102	14059	69	0	0
T122	1199	2	0	0
T123	1898	6	0	0
T124	2253	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	3321	0	0
T47	118790	0	0	0
T54	0	26	0	0
T55	0	39	0	0
T78	0	21	0	0
T108	122488	7	0	0
T110	0	11	0	0
T125	0	14	0	0
T126	0	25	0	0
T127	0	26	0	0
T128	0	4	0	0
T129	0	21	0	0
T130	151457	0	0	0
T131	106426	0	0	0
T132	120079	0	0	0
T133	8208	0	0	0
T134	9435	0	0	0
T135	204995	0	0	0
T136	103648	0	0	0
T137	23634	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	1875	0	0
T88	2998	63	0	0
T138	0	57	0	0
T139	0	43	0	0
T140	0	26	0	0
T141	0	40	0	0
T142	0	44	0	0
T143	0	47	0	0
T144	0	31	0	0
T145	0	11	0	0
T146	0	71	0	0
T147	12448	0	0	0
T148	12907	0	0	0
T149	211805	0	0	0
T150	302312	0	0	0
T151	109792	0	0	0
T152	79443	0	0	0
T153	182552	0	0	0
T154	395122	0	0	0
T155	42576	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	1284	0	0
T95	1697	10	0	0
T96	1977	1	0	0
T97	2984	9	0	0
T98	3431	2	0	0
T101	2960	20	0	0
T102	14059	124	0	0
T103	8973	56	0	0
T122	1199	9	0	0
T123	1898	9	0	0
T124	2253	1	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	1521	0	0
T95	1697	6	0	0
T96	1977	3	0	0
T97	2984	35	0	0
T100	4143	25	0	0
T101	2960	35	0	0
T102	14059	193	0	0
T103	8973	64	0	0
T122	1199	2	0	0
T123	1898	14	0	0
T124	2253	6	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	1295	0	0
T95	1697	12	0	0
T96	1977	7	0	0
T97	2984	16	0	0
T98	3431	1	0	0
T99	1548	10	0	0
T100	4143	43	0	0
T101	2960	3	0	0
T122	1199	8	0	0
T123	1898	9	0	0
T124	2253	7	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	1267	0	0
T95	1697	9	0	0
T96	1977	6	0	0
T97	2984	22	0	0
T99	1548	4	0	0
T100	4143	6	0	0
T101	2960	11	0	0
T102	14059	138	0	0
T103	8973	52	0	0
T123	1898	8	0	0
T124	2253	3	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	1207	0	0
T95	1697	8	0	0
T96	1977	9	0	0
T98	3431	4	0	0
T100	4143	24	0	0
T101	2960	10	0	0
T102	14059	132	0	0
T103	8973	55	0	0
T122	1199	4	0	0
T123	1898	4	0	0
T124	2253	9	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	1286	0	0
T95	1697	14	0	0
T96	1977	6	0	0
T97	2984	13	0	0
T99	1548	2	0	0
T100	4143	12	0	0
T101	2960	16	0	0
T102	14059	116	0	0
T122	1199	2	0	0
T123	1898	10	0	0
T124	2253	8	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	1323	0	0
T95	1697	8	0	0
T96	1977	3	0	0
T97	2984	17	0	0
T98	3431	6	0	0
T100	4143	50	0	0
T101	2960	8	0	0
T102	14059	125	0	0
T122	1199	8	0	0
T123	1898	16	0	0
T124	2253	7	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	1325	0	0
T95	1697	4	0	0
T96	1977	2	0	0
T97	2984	16	0	0
T98	3431	5	0	0
T100	4143	40	0	0
T101	2960	5	0	0
T102	14059	107	0	0
T122	1199	10	0	0
T123	1898	3	0	0
T124	2253	3	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385119232	1160	0	0
T95	1697	1	0	0
T96	1977	5	0	0
T97	2984	10	0	0
T99	1548	1	0	0
T100	4143	13	0	0
T101	2960	7	0	0
T102	14059	87	0	0
T122	1199	3	0	0
T123	1898	11	0	0
T124	2253	1	0	0