Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
81.01 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 60 15 45 75.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 15 0 15 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 60 15 45 75.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 357 1 T1 8 T6 1 T11 5
all_values[1] 357 1 T1 8 T6 1 T11 5
all_values[2] 357 1 T1 8 T6 1 T11 5
all_values[3] 357 1 T1 8 T6 1 T11 5
all_values[4] 357 1 T1 8 T6 1 T11 5
all_values[5] 357 1 T1 8 T6 1 T11 5
all_values[6] 357 1 T1 8 T6 1 T11 5
all_values[7] 357 1 T1 8 T6 1 T11 5
all_values[8] 357 1 T1 8 T6 1 T11 5
all_values[9] 357 1 T1 8 T6 1 T11 5
all_values[10] 357 1 T1 8 T6 1 T11 5
all_values[11] 357 1 T1 8 T6 1 T11 5
all_values[12] 357 1 T1 8 T6 1 T11 5
all_values[13] 357 1 T1 8 T6 1 T11 5
all_values[14] 357 1 T1 8 T6 1 T11 5



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3440 1 T1 56 T6 15 T11 52
auto[1] 1915 1 T1 64 T11 23 T8 48



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1117 1 T1 10 T6 15 T11 26
auto[1] 4238 1 T1 110 T11 49 T8 96



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 60 15 45 75.00 15


Automatically Generated Cross Bins for intr_cg_cc

Element holes
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] [auto[0]] -- -- 15


Covered bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] 81 1 T6 1 T11 1 T14 1
all_values[0] auto[0] auto[1] 161 1 T1 6 T11 3 T8 4
all_values[0] auto[1] auto[1] 115 1 T1 2 T11 1 T8 4
all_values[1] auto[0] auto[0] 79 1 T1 2 T6 1 T10 2
all_values[1] auto[0] auto[1] 149 1 T1 3 T11 4 T8 4
all_values[1] auto[1] auto[1] 129 1 T1 3 T11 1 T8 4
all_values[2] auto[0] auto[0] 71 1 T1 4 T6 1 T11 2
all_values[2] auto[0] auto[1] 174 1 T1 3 T11 2 T8 3
all_values[2] auto[1] auto[1] 112 1 T1 1 T11 1 T8 1
all_values[3] auto[0] auto[0] 69 1 T6 1 T11 1 T8 3
all_values[3] auto[0] auto[1] 156 1 T1 5 T11 1 T8 1
all_values[3] auto[1] auto[1] 132 1 T1 3 T11 3 T8 4
all_values[4] auto[0] auto[0] 86 1 T1 1 T6 1 T8 3
all_values[4] auto[0] auto[1] 143 1 T1 4 T11 4 T8 3
all_values[4] auto[1] auto[1] 128 1 T1 3 T11 1 T8 2
all_values[5] auto[0] auto[0] 68 1 T6 1 T11 5 T10 1
all_values[5] auto[0] auto[1] 139 1 T1 1 T8 2 T10 4
all_values[5] auto[1] auto[1] 150 1 T1 7 T8 6 T10 3
all_values[6] auto[0] auto[0] 82 1 T6 1 T11 5 T8 1
all_values[6] auto[0] auto[1] 167 1 T1 3 T8 4 T10 6
all_values[6] auto[1] auto[1] 108 1 T1 5 T8 3 T12 4
all_values[7] auto[0] auto[0] 78 1 T6 1 T10 4 T14 1
all_values[7] auto[0] auto[1] 146 1 T1 1 T11 1 T8 4
all_values[7] auto[1] auto[1] 133 1 T1 7 T11 4 T8 4
all_values[8] auto[0] auto[0] 60 1 T6 1 T8 8 T10 1
all_values[8] auto[0] auto[1] 147 1 T1 1 T11 1 T10 3
all_values[8] auto[1] auto[1] 150 1 T1 7 T11 4 T10 4
all_values[9] auto[0] auto[0] 64 1 T6 1 T11 2 T8 2
all_values[9] auto[0] auto[1] 160 1 T1 3 T11 3 T8 2
all_values[9] auto[1] auto[1] 133 1 T1 5 T8 4 T10 5
all_values[10] auto[0] auto[0] 90 1 T1 2 T6 1 T11 5
all_values[10] auto[0] auto[1] 151 1 T1 3 T8 5 T10 2
all_values[10] auto[1] auto[1] 116 1 T1 3 T8 3 T10 1
all_values[11] auto[0] auto[0] 70 1 T1 1 T6 1 T8 1
all_values[11] auto[0] auto[1] 177 1 T1 5 T11 3 T8 5
all_values[11] auto[1] auto[1] 110 1 T1 2 T11 2 T8 2
all_values[12] auto[0] auto[0] 84 1 T6 1 T8 1 T14 1
all_values[12] auto[0] auto[1] 162 1 T1 4 T11 3 T8 5
all_values[12] auto[1] auto[1] 111 1 T1 4 T11 2 T8 2
all_values[13] auto[0] auto[0] 71 1 T6 1 T11 5 T14 1
all_values[13] auto[0] auto[1] 149 1 T1 2 T8 2 T10 5
all_values[13] auto[1] auto[1] 137 1 T1 6 T8 6 T10 3
all_values[14] auto[0] auto[0] 64 1 T6 1 T8 1 T14 1
all_values[14] auto[0] auto[1] 142 1 T1 2 T11 1 T8 4
all_values[14] auto[1] auto[1] 151 1 T1 6 T11 4 T8 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%