Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
52.65 40.66 40.72 90.72 0.00 42.98 99.68 53.79


Total tests in report: 164
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
45.30 45.30 39.00 39.00 36.54 36.54 90.57 90.57 0.00 0.00 41.77 41.77 91.40 91.40 17.79 17.79 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.395266333
50.27 4.98 40.20 1.19 38.80 2.26 93.55 2.98 0.00 0.00 42.91 1.13 91.72 0.32 44.74 26.95 /workspace/coverage/cover_reg_top/2.i2c_intr_test.3365881448
51.73 1.46 40.66 0.46 39.10 0.30 96.03 2.48 0.00 0.00 42.98 0.07 96.82 5.10 46.53 1.79 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3755149745
52.40 0.67 40.66 0.00 39.33 0.23 97.02 0.99 0.00 0.00 42.98 0.00 96.82 0.00 50.00 3.47 /workspace/coverage/cover_reg_top/20.i2c_intr_test.352119608
52.77 0.37 40.66 0.00 39.48 0.15 97.02 0.00 0.00 0.00 42.98 0.00 99.04 2.23 50.21 0.21 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.423893285
52.97 0.20 40.66 0.00 40.27 0.79 97.02 0.00 0.00 0.00 42.98 0.00 99.04 0.00 50.84 0.63 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3281527543
53.09 0.12 40.66 0.00 40.27 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.64 51.05 0.21 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1357305979
53.20 0.11 40.66 0.00 40.27 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 51.79 0.74 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3944463943
53.29 0.09 40.66 0.00 40.27 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 52.42 0.63 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3935923074
53.35 0.06 40.66 0.00 40.27 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 52.84 0.42 /workspace/coverage/cover_reg_top/16.i2c_intr_test.2716882702
53.40 0.05 40.66 0.00 40.27 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.16 0.32 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3022063900
53.44 0.04 40.66 0.00 40.35 0.08 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.37 0.21 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2817963171
53.47 0.03 40.66 0.00 40.35 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.58 0.21 /workspace/coverage/cover_reg_top/12.i2c_intr_test.3027344251
53.50 0.03 40.66 0.00 40.35 0.00 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.79 0.21 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2176119456
53.52 0.02 40.66 0.00 40.50 0.15 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.79 0.00 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1818731012
53.53 0.01 40.66 0.00 40.57 0.08 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.79 0.00 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4027511437
53.54 0.01 40.66 0.00 40.65 0.08 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.79 0.00 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1950848724
53.55 0.01 40.66 0.00 40.72 0.08 97.02 0.00 0.00 0.00 42.98 0.00 99.68 0.00 53.79 0.00 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2130904813

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2786350669
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.164446759
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.710771506
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4258374510
/workspace/coverage/cover_reg_top/0.i2c_intr_test.1661807888
/workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2959848107
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.3336117653
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3844545677
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.800410317
/workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1578596350
/workspace/coverage/cover_reg_top/1.i2c_csr_rw.2952487248
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.274654497
/workspace/coverage/cover_reg_top/1.i2c_tl_errors.3911486743
/workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2225733580
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1748530948
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.3186741630
/workspace/coverage/cover_reg_top/10.i2c_intr_test.409951683
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.367600120
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.1800829926
/workspace/coverage/cover_reg_top/11.i2c_intr_test.787532293
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1957234517
/workspace/coverage/cover_reg_top/11.i2c_tl_errors.1827525524
/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2266159279
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1706150807
/workspace/coverage/cover_reg_top/12.i2c_csr_rw.2594319266
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3628816490
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.1476762597
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1135632401
/workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.250223672
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.1479378934
/workspace/coverage/cover_reg_top/13.i2c_intr_test.1320056748
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.542370540
/workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1793444047
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2701963487
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.3195459740
/workspace/coverage/cover_reg_top/14.i2c_intr_test.4088718642
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.4152068344
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.1883946139
/workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1909028271
/workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.949933781
/workspace/coverage/cover_reg_top/15.i2c_csr_rw.1128179302
/workspace/coverage/cover_reg_top/15.i2c_intr_test.3039711404
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.852446635
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.1307372159
/workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3038435657
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2974467673
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.294753250
/workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1184003185
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.2403922430
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.4069134626
/workspace/coverage/cover_reg_top/17.i2c_csr_rw.3579906678
/workspace/coverage/cover_reg_top/17.i2c_intr_test.4268334387
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.495011532
/workspace/coverage/cover_reg_top/17.i2c_tl_errors.3637272433
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2147497845
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.325730288
/workspace/coverage/cover_reg_top/18.i2c_intr_test.733042553
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.310606949
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.1950932019
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.293638300
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2130567169
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.196022058
/workspace/coverage/cover_reg_top/19.i2c_intr_test.1727345561
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.891172909
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.2605068916
/workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2450780056
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1812370146
/workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.103493273
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2517487979
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3061031520
/workspace/coverage/cover_reg_top/2.i2c_tl_errors.1504824159
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2508513596
/workspace/coverage/cover_reg_top/21.i2c_intr_test.18215884
/workspace/coverage/cover_reg_top/22.i2c_intr_test.1685434713
/workspace/coverage/cover_reg_top/23.i2c_intr_test.4145764092
/workspace/coverage/cover_reg_top/24.i2c_intr_test.1716456134
/workspace/coverage/cover_reg_top/25.i2c_intr_test.357352384
/workspace/coverage/cover_reg_top/26.i2c_intr_test.1377460171
/workspace/coverage/cover_reg_top/28.i2c_intr_test.1821781238
/workspace/coverage/cover_reg_top/29.i2c_intr_test.3560892688
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1140779681
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1201752248
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1003129794
/workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.512688607
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.703260273
/workspace/coverage/cover_reg_top/3.i2c_intr_test.3411522189
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1716875001
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.640752291
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3683752753
/workspace/coverage/cover_reg_top/30.i2c_intr_test.3548520572
/workspace/coverage/cover_reg_top/31.i2c_intr_test.1160555149
/workspace/coverage/cover_reg_top/32.i2c_intr_test.3843975792
/workspace/coverage/cover_reg_top/33.i2c_intr_test.16192979
/workspace/coverage/cover_reg_top/34.i2c_intr_test.96983631
/workspace/coverage/cover_reg_top/35.i2c_intr_test.4173637648
/workspace/coverage/cover_reg_top/36.i2c_intr_test.1130167814
/workspace/coverage/cover_reg_top/37.i2c_intr_test.1506875111
/workspace/coverage/cover_reg_top/38.i2c_intr_test.351949445
/workspace/coverage/cover_reg_top/39.i2c_intr_test.1122018669
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.85144824
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3100100857
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.4246742567
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.370560958
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.2903776178
/workspace/coverage/cover_reg_top/4.i2c_intr_test.2248117886
/workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2151125180
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.2112185209
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3983389650
/workspace/coverage/cover_reg_top/40.i2c_intr_test.92501835
/workspace/coverage/cover_reg_top/41.i2c_intr_test.4103508340
/workspace/coverage/cover_reg_top/42.i2c_intr_test.319435850
/workspace/coverage/cover_reg_top/43.i2c_intr_test.3035925500
/workspace/coverage/cover_reg_top/44.i2c_intr_test.1570240433
/workspace/coverage/cover_reg_top/45.i2c_intr_test.143996630
/workspace/coverage/cover_reg_top/46.i2c_intr_test.3404202086
/workspace/coverage/cover_reg_top/47.i2c_intr_test.4174475062
/workspace/coverage/cover_reg_top/48.i2c_intr_test.1425623994
/workspace/coverage/cover_reg_top/49.i2c_intr_test.2989238922
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3413146850
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.1309959840
/workspace/coverage/cover_reg_top/5.i2c_intr_test.2300507599
/workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1635073265
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.928941463
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2131277343
/workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3717842884
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.3717289293
/workspace/coverage/cover_reg_top/6.i2c_intr_test.1457263319
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2943822168
/workspace/coverage/cover_reg_top/6.i2c_tl_errors.2569614866
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2009759632
/workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.730200960
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.3189496083
/workspace/coverage/cover_reg_top/7.i2c_intr_test.121606756
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.2578480937
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3244256120
/workspace/coverage/cover_reg_top/8.i2c_csr_rw.26932632
/workspace/coverage/cover_reg_top/8.i2c_intr_test.2669662327
/workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3600963637
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.2453125838
/workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.424184545
/workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1689125326
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.3433751404
/workspace/coverage/cover_reg_top/9.i2c_intr_test.4002065978
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2779899824
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.936461679
/workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1780382951



Total test records in report: 164
tests.html | tests1.html | tests2.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/30.i2c_intr_test.3548520572 Jul 01 04:28:32 PM PDT 24 Jul 01 04:28:38 PM PDT 24 18619394 ps
T2 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.423893285 Jul 01 04:28:06 PM PDT 24 Jul 01 04:28:19 PM PDT 24 66650811 ps
T3 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3038435657 Jul 01 04:28:17 PM PDT 24 Jul 01 04:28:24 PM PDT 24 446576096 ps
T7 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2779899824 Jul 01 04:28:14 PM PDT 24 Jul 01 04:28:23 PM PDT 24 70520015 ps
T6 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.640752291 Jul 01 04:28:48 PM PDT 24 Jul 01 04:29:04 PM PDT 24 99476718 ps
T13 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1635073265 Jul 01 04:28:24 PM PDT 24 Jul 01 04:28:30 PM PDT 24 20856560 ps
T11 /workspace/coverage/cover_reg_top/48.i2c_intr_test.1425623994 Jul 01 04:29:04 PM PDT 24 Jul 01 04:29:16 PM PDT 24 65025086 ps
T8 /workspace/coverage/cover_reg_top/2.i2c_intr_test.3365881448 Jul 01 04:28:08 PM PDT 24 Jul 01 04:28:18 PM PDT 24 20392361 ps
T4 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.395266333 Jul 01 04:28:34 PM PDT 24 Jul 01 04:28:42 PM PDT 24 334504649 ps
T10 /workspace/coverage/cover_reg_top/20.i2c_intr_test.352119608 Jul 01 04:28:44 PM PDT 24 Jul 01 04:28:55 PM PDT 24 58441407 ps
T14 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1950932019 Jul 01 04:28:33 PM PDT 24 Jul 01 04:28:41 PM PDT 24 153188976 ps
T21 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1201752248 Jul 01 04:28:06 PM PDT 24 Jul 01 04:28:21 PM PDT 24 671002734 ps
T12 /workspace/coverage/cover_reg_top/7.i2c_intr_test.121606756 Jul 01 04:28:34 PM PDT 24 Jul 01 04:28:41 PM PDT 24 60568442 ps
T9 /workspace/coverage/cover_reg_top/28.i2c_intr_test.1821781238 Jul 01 04:28:43 PM PDT 24 Jul 01 04:28:54 PM PDT 24 18220651 ps
T67 /workspace/coverage/cover_reg_top/47.i2c_intr_test.4174475062 Jul 01 04:28:50 PM PDT 24 Jul 01 04:29:05 PM PDT 24 16299753 ps
T68 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2176119456 Jul 01 04:28:30 PM PDT 24 Jul 01 04:28:35 PM PDT 24 38318535 ps
T5 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1818731012 Jul 01 04:28:28 PM PDT 24 Jul 01 04:28:35 PM PDT 24 589910330 ps
T15 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2974467673 Jul 01 04:28:33 PM PDT 24 Jul 01 04:28:39 PM PDT 24 148841815 ps
T16 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3281527543 Jul 01 04:28:24 PM PDT 24 Jul 01 04:28:31 PM PDT 24 197862774 ps
T74 /workspace/coverage/cover_reg_top/17.i2c_intr_test.4268334387 Jul 01 04:28:23 PM PDT 24 Jul 01 04:28:29 PM PDT 24 17336610 ps
T22 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2147497845 Jul 01 04:28:39 PM PDT 24 Jul 01 04:28:47 PM PDT 24 56577453 ps
T52 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1570240433 Jul 01 04:28:29 PM PDT 24 Jul 01 04:28:34 PM PDT 24 49978641 ps
T25 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1716875001 Jul 01 04:28:07 PM PDT 24 Jul 01 04:28:18 PM PDT 24 36258999 ps
T17 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1909028271 Jul 01 04:28:23 PM PDT 24 Jul 01 04:28:31 PM PDT 24 166372514 ps
T49 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.4152068344 Jul 01 04:28:43 PM PDT 24 Jul 01 04:28:55 PM PDT 24 247089007 ps
T69 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3944463943 Jul 01 04:28:28 PM PDT 24 Jul 01 04:28:33 PM PDT 24 62563083 ps
T26 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2903776178 Jul 01 04:28:09 PM PDT 24 Jul 01 04:28:20 PM PDT 24 105556223 ps
T27 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.542370540 Jul 01 04:28:41 PM PDT 24 Jul 01 04:28:50 PM PDT 24 58321723 ps
T23 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1689125326 Jul 01 04:28:40 PM PDT 24 Jul 01 04:28:48 PM PDT 24 33421595 ps
T50 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3935923074 Jul 01 04:28:13 PM PDT 24 Jul 01 04:28:22 PM PDT 24 73362919 ps
T18 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3755149745 Jul 01 04:28:34 PM PDT 24 Jul 01 04:28:41 PM PDT 24 122903248 ps
T51 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1184003185 Jul 01 04:28:34 PM PDT 24 Jul 01 04:28:41 PM PDT 24 52384577 ps
T24 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1793444047 Jul 01 04:28:29 PM PDT 24 Jul 01 04:28:35 PM PDT 24 86866379 ps
T19 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1827525524 Jul 01 04:28:34 PM PDT 24 Jul 01 04:28:43 PM PDT 24 486794905 ps
T70 /workspace/coverage/cover_reg_top/13.i2c_intr_test.1320056748 Jul 01 04:28:25 PM PDT 24 Jul 01 04:28:30 PM PDT 24 31630997 ps
T20 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4027511437 Jul 01 04:28:37 PM PDT 24 Jul 01 04:28:45 PM PDT 24 47541340 ps
T73 /workspace/coverage/cover_reg_top/16.i2c_intr_test.2716882702 Jul 01 04:28:18 PM PDT 24 Jul 01 04:28:24 PM PDT 24 14385359 ps
T76 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2130567169 Jul 01 04:28:30 PM PDT 24 Jul 01 04:28:35 PM PDT 24 29237955 ps
T28 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3717289293 Jul 01 04:28:40 PM PDT 24 Jul 01 04:28:47 PM PDT 24 19996932 ps
T71 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1506875111 Jul 01 04:28:49 PM PDT 24 Jul 01 04:29:03 PM PDT 24 113937893 ps
T29 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.852446635 Jul 01 04:28:38 PM PDT 24 Jul 01 04:28:45 PM PDT 24 33168986 ps
T77 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.928941463 Jul 01 04:28:32 PM PDT 24 Jul 01 04:28:39 PM PDT 24 73270948 ps
T56 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1950848724 Jul 01 04:28:17 PM PDT 24 Jul 01 04:28:25 PM PDT 24 286810203 ps
T78 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3195459740 Jul 01 04:28:34 PM PDT 24 Jul 01 04:28:41 PM PDT 24 166454835 ps
T30 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.4246742567 Jul 01 04:28:27 PM PDT 24 Jul 01 04:28:33 PM PDT 24 24702404 ps
T38 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2009759632 Jul 01 04:28:33 PM PDT 24 Jul 01 04:28:40 PM PDT 24 1401863891 ps
T39 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1780382951 Jul 01 04:28:23 PM PDT 24 Jul 01 04:28:30 PM PDT 24 80714286 ps
T40 /workspace/coverage/cover_reg_top/5.i2c_intr_test.2300507599 Jul 01 04:28:22 PM PDT 24 Jul 01 04:28:27 PM PDT 24 32939931 ps
T41 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3100100857 Jul 01 04:28:27 PM PDT 24 Jul 01 04:28:36 PM PDT 24 1176024166 ps
T42 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.730200960 Jul 01 04:28:37 PM PDT 24 Jul 01 04:28:44 PM PDT 24 160152480 ps
T31 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.85144824 Jul 01 04:28:16 PM PDT 24 Jul 01 04:28:24 PM PDT 24 86604899 ps
T43 /workspace/coverage/cover_reg_top/38.i2c_intr_test.351949445 Jul 01 04:28:39 PM PDT 24 Jul 01 04:28:47 PM PDT 24 27557605 ps
T32 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1309959840 Jul 01 04:28:19 PM PDT 24 Jul 01 04:28:26 PM PDT 24 28975848 ps
T44 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1003129794 Jul 01 04:28:28 PM PDT 24 Jul 01 04:28:34 PM PDT 24 26961708 ps
T79 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2151125180 Jul 01 04:28:32 PM PDT 24 Jul 01 04:28:38 PM PDT 24 172508419 ps
T80 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3186741630 Jul 01 04:28:29 PM PDT 24 Jul 01 04:28:34 PM PDT 24 49655630 ps
T58 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.424184545 Jul 01 04:28:33 PM PDT 24 Jul 01 04:28:40 PM PDT 24 78370504 ps
T81 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2959848107 Jul 01 04:28:03 PM PDT 24 Jul 01 04:28:14 PM PDT 24 39281113 ps
T82 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1457263319 Jul 01 04:28:42 PM PDT 24 Jul 01 04:28:52 PM PDT 24 34106456 ps
T83 /workspace/coverage/cover_reg_top/3.i2c_intr_test.3411522189 Jul 01 04:28:20 PM PDT 24 Jul 01 04:28:26 PM PDT 24 44723995 ps
T75 /workspace/coverage/cover_reg_top/33.i2c_intr_test.16192979 Jul 01 04:28:33 PM PDT 24 Jul 01 04:28:40 PM PDT 24 19473553 ps
T84 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.891172909 Jul 01 04:28:37 PM PDT 24 Jul 01 04:28:44 PM PDT 24 84472515 ps
T85 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3413146850 Jul 01 04:28:22 PM PDT 24 Jul 01 04:28:28 PM PDT 24 128034061 ps
T33 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1479378934 Jul 01 04:28:38 PM PDT 24 Jul 01 04:28:45 PM PDT 24 83059977 ps
T86 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.949933781 Jul 01 04:28:31 PM PDT 24 Jul 01 04:28:38 PM PDT 24 120118631 ps
T87 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3717842884 Jul 01 04:28:05 PM PDT 24 Jul 01 04:28:16 PM PDT 24 36224551 ps
T88 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3189496083 Jul 01 04:28:21 PM PDT 24 Jul 01 04:28:27 PM PDT 24 23950529 ps
T55 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2130904813 Jul 01 04:28:27 PM PDT 24 Jul 01 04:28:34 PM PDT 24 284572348 ps
T34 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2517487979 Jul 01 04:28:05 PM PDT 24 Jul 01 04:28:16 PM PDT 24 37581583 ps
T89 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.274654497 Jul 01 04:28:18 PM PDT 24 Jul 01 04:28:29 PM PDT 24 56507677 ps
T90 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2578480937 Jul 01 04:28:25 PM PDT 24 Jul 01 04:28:31 PM PDT 24 83004658 ps
T65 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1957234517 Jul 01 04:28:26 PM PDT 24 Jul 01 04:28:37 PM PDT 24 34018879 ps
T91 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3433751404 Jul 01 04:28:34 PM PDT 24 Jul 01 04:28:42 PM PDT 24 801439669 ps
T92 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.936461679 Jul 01 04:28:29 PM PDT 24 Jul 01 04:28:36 PM PDT 24 103992429 ps
T72 /workspace/coverage/cover_reg_top/14.i2c_intr_test.4088718642 Jul 01 04:28:43 PM PDT 24 Jul 01 04:28:53 PM PDT 24 20937496 ps
T93 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.703260273 Jul 01 04:28:11 PM PDT 24 Jul 01 04:28:21 PM PDT 24 20137559 ps
T94 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3061031520 Jul 01 04:28:21 PM PDT 24 Jul 01 04:28:27 PM PDT 24 44742500 ps
T95 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3637272433 Jul 01 04:28:47 PM PDT 24 Jul 01 04:29:01 PM PDT 24 186352831 ps
T96 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1504824159 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:12 PM PDT 24 799686890 ps
T97 /workspace/coverage/cover_reg_top/8.i2c_intr_test.2669662327 Jul 01 04:28:37 PM PDT 24 Jul 01 04:28:43 PM PDT 24 25795421 ps
T98 /workspace/coverage/cover_reg_top/11.i2c_intr_test.787532293 Jul 01 04:28:32 PM PDT 24 Jul 01 04:28:39 PM PDT 24 19680081 ps
T99 /workspace/coverage/cover_reg_top/41.i2c_intr_test.4103508340 Jul 01 04:28:39 PM PDT 24 Jul 01 04:28:47 PM PDT 24 18241577 ps
T100 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2701963487 Jul 01 04:28:20 PM PDT 24 Jul 01 04:28:26 PM PDT 24 51972994 ps
T35 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1128179302 Jul 01 04:28:17 PM PDT 24 Jul 01 04:28:24 PM PDT 24 20277774 ps
T101 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.294753250 Jul 01 04:28:32 PM PDT 24 Jul 01 04:28:39 PM PDT 24 51974603 ps
T102 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.512688607 Jul 01 04:28:31 PM PDT 24 Jul 01 04:28:37 PM PDT 24 179790545 ps
T53 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.310606949 Jul 01 04:28:39 PM PDT 24 Jul 01 04:28:46 PM PDT 24 131575967 ps
T103 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1130167814 Jul 01 04:28:47 PM PDT 24 Jul 01 04:29:00 PM PDT 24 18327042 ps
T61 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2225733580 Jul 01 04:28:04 PM PDT 24 Jul 01 04:28:16 PM PDT 24 534184063 ps
T104 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3600963637 Jul 01 04:28:35 PM PDT 24 Jul 01 04:28:42 PM PDT 24 94367792 ps
T57 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3683752753 Jul 01 04:28:27 PM PDT 24 Jul 01 04:28:34 PM PDT 24 854939401 ps
T105 /workspace/coverage/cover_reg_top/34.i2c_intr_test.96983631 Jul 01 04:28:45 PM PDT 24 Jul 01 04:28:57 PM PDT 24 43264413 ps
T106 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3911486743 Jul 01 04:28:14 PM PDT 24 Jul 01 04:28:23 PM PDT 24 198724901 ps
T54 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2508513596 Jul 01 04:28:27 PM PDT 24 Jul 01 04:28:33 PM PDT 24 336846598 ps
T107 /workspace/coverage/cover_reg_top/42.i2c_intr_test.319435850 Jul 01 04:28:40 PM PDT 24 Jul 01 04:28:48 PM PDT 24 30570305 ps
T108 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3560892688 Jul 01 04:28:31 PM PDT 24 Jul 01 04:28:37 PM PDT 24 73451168 ps
T109 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3336117653 Jul 01 04:28:47 PM PDT 24 Jul 01 04:29:02 PM PDT 24 85926177 ps
T110 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1122018669 Jul 01 04:28:30 PM PDT 24 Jul 01 04:28:36 PM PDT 24 30228792 ps
T111 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3579906678 Jul 01 04:28:29 PM PDT 24 Jul 01 04:28:34 PM PDT 24 53155786 ps
T112 /workspace/coverage/cover_reg_top/49.i2c_intr_test.2989238922 Jul 01 04:28:32 PM PDT 24 Jul 01 04:28:38 PM PDT 24 33566840 ps
T59 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2817963171 Jul 01 04:28:42 PM PDT 24 Jul 01 04:28:53 PM PDT 24 129953159 ps
T113 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2952487248 Jul 01 04:28:03 PM PDT 24 Jul 01 04:28:13 PM PDT 24 78219367 ps
T60 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2131277343 Jul 01 04:28:17 PM PDT 24 Jul 01 04:28:26 PM PDT 24 248291411 ps
T114 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3628816490 Jul 01 04:28:17 PM PDT 24 Jul 01 04:28:25 PM PDT 24 62703916 ps
T115 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2943822168 Jul 01 04:28:19 PM PDT 24 Jul 01 04:28:26 PM PDT 24 98420762 ps
T116 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.250223672 Jul 01 04:28:32 PM PDT 24 Jul 01 04:28:38 PM PDT 24 92187155 ps
T63 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.4069134626 Jul 01 04:28:32 PM PDT 24 Jul 01 04:28:39 PM PDT 24 78135634 ps
T36 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2450780056 Jul 01 04:28:30 PM PDT 24 Jul 01 04:28:37 PM PDT 24 1128697747 ps
T117 /workspace/coverage/cover_reg_top/43.i2c_intr_test.3035925500 Jul 01 04:28:46 PM PDT 24 Jul 01 04:28:59 PM PDT 24 17136246 ps
T118 /workspace/coverage/cover_reg_top/12.i2c_intr_test.3027344251 Jul 01 04:28:22 PM PDT 24 Jul 01 04:28:28 PM PDT 24 61709518 ps
T119 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1135632401 Jul 01 04:28:31 PM PDT 24 Jul 01 04:28:38 PM PDT 24 53962888 ps
T120 /workspace/coverage/cover_reg_top/22.i2c_intr_test.1685434713 Jul 01 04:28:40 PM PDT 24 Jul 01 04:28:48 PM PDT 24 31406348 ps
T121 /workspace/coverage/cover_reg_top/24.i2c_intr_test.1716456134 Jul 01 04:28:33 PM PDT 24 Jul 01 04:28:39 PM PDT 24 39923377 ps
T122 /workspace/coverage/cover_reg_top/25.i2c_intr_test.357352384 Jul 01 04:28:33 PM PDT 24 Jul 01 04:28:40 PM PDT 24 78280120 ps
T123 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1706150807 Jul 01 04:28:20 PM PDT 24 Jul 01 04:28:26 PM PDT 24 25610336 ps
T124 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2605068916 Jul 01 04:28:34 PM PDT 24 Jul 01 04:28:43 PM PDT 24 552153280 ps
T66 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.495011532 Jul 01 04:28:46 PM PDT 24 Jul 01 04:28:58 PM PDT 24 34724635 ps
T125 /workspace/coverage/cover_reg_top/45.i2c_intr_test.143996630 Jul 01 04:28:22 PM PDT 24 Jul 01 04:28:27 PM PDT 24 34511198 ps
T126 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1307372159 Jul 01 04:28:33 PM PDT 24 Jul 01 04:28:42 PM PDT 24 111134502 ps
T127 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1140779681 Jul 01 04:28:26 PM PDT 24 Jul 01 04:28:32 PM PDT 24 106269322 ps
T37 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.196022058 Jul 01 04:28:41 PM PDT 24 Jul 01 04:28:50 PM PDT 24 26819183 ps
T64 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3022063900 Jul 01 04:28:30 PM PDT 24 Jul 01 04:28:36 PM PDT 24 219305896 ps
T128 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2569614866 Jul 01 04:28:26 PM PDT 24 Jul 01 04:28:31 PM PDT 24 49898036 ps
T129 /workspace/coverage/cover_reg_top/9.i2c_intr_test.4002065978 Jul 01 04:28:36 PM PDT 24 Jul 01 04:28:43 PM PDT 24 18347600 ps
T45 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2786350669 Jul 01 04:28:07 PM PDT 24 Jul 01 04:28:19 PM PDT 24 621146757 ps
T130 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1578596350 Jul 01 04:28:05 PM PDT 24 Jul 01 04:28:15 PM PDT 24 28712418 ps
T131 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.367600120 Jul 01 04:28:14 PM PDT 24 Jul 01 04:28:22 PM PDT 24 57651309 ps
T132 /workspace/coverage/cover_reg_top/40.i2c_intr_test.92501835 Jul 01 04:28:34 PM PDT 24 Jul 01 04:28:41 PM PDT 24 43162738 ps
T133 /workspace/coverage/cover_reg_top/23.i2c_intr_test.4145764092 Jul 01 04:28:42 PM PDT 24 Jul 01 04:28:51 PM PDT 24 49206526 ps
T134 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.293638300 Jul 01 04:28:22 PM PDT 24 Jul 01 04:28:28 PM PDT 24 600210626 ps
T135 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3244256120 Jul 01 04:28:37 PM PDT 24 Jul 01 04:28:44 PM PDT 24 261023153 ps
T136 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1883946139 Jul 01 04:28:28 PM PDT 24 Jul 01 04:28:35 PM PDT 24 572701055 ps
T137 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2594319266 Jul 01 04:28:42 PM PDT 24 Jul 01 04:28:52 PM PDT 24 40121847 ps
T138 /workspace/coverage/cover_reg_top/32.i2c_intr_test.3843975792 Jul 01 04:28:45 PM PDT 24 Jul 01 04:28:59 PM PDT 24 87590314 ps
T46 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.710771506 Jul 01 04:28:05 PM PDT 24 Jul 01 04:28:16 PM PDT 24 17133322 ps
T139 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1661807888 Jul 01 04:28:06 PM PDT 24 Jul 01 04:28:16 PM PDT 24 28298828 ps
T140 /workspace/coverage/cover_reg_top/21.i2c_intr_test.18215884 Jul 01 04:28:37 PM PDT 24 Jul 01 04:28:43 PM PDT 24 68361632 ps
T141 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.370560958 Jul 01 04:28:48 PM PDT 24 Jul 01 04:29:03 PM PDT 24 28196733 ps
T142 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1800829926 Jul 01 04:28:30 PM PDT 24 Jul 01 04:28:36 PM PDT 24 54741208 ps
T143 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.26932632 Jul 01 04:28:24 PM PDT 24 Jul 01 04:28:30 PM PDT 24 51745934 ps
T144 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3844545677 Jul 01 04:28:12 PM PDT 24 Jul 01 04:28:22 PM PDT 24 81387557 ps
T47 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1812370146 Jul 01 04:28:51 PM PDT 24 Jul 01 04:29:06 PM PDT 24 24201063 ps
T145 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2266159279 Jul 01 04:28:20 PM PDT 24 Jul 01 04:28:28 PM PDT 24 532140796 ps
T146 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.164446759 Jul 01 04:28:33 PM PDT 24 Jul 01 04:28:41 PM PDT 24 75990529 ps
T147 /workspace/coverage/cover_reg_top/15.i2c_intr_test.3039711404 Jul 01 04:28:35 PM PDT 24 Jul 01 04:28:42 PM PDT 24 76709898 ps
T62 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3983389650 Jul 01 04:28:14 PM PDT 24 Jul 01 04:28:24 PM PDT 24 83001580 ps
T148 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2112185209 Jul 01 04:28:32 PM PDT 24 Jul 01 04:28:38 PM PDT 24 32362543 ps
T149 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.800410317 Jul 01 04:28:21 PM PDT 24 Jul 01 04:28:30 PM PDT 24 463998759 ps
T150 /workspace/coverage/cover_reg_top/10.i2c_intr_test.409951683 Jul 01 04:28:21 PM PDT 24 Jul 01 04:28:26 PM PDT 24 35177063 ps
T151 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.325730288 Jul 01 04:28:40 PM PDT 24 Jul 01 04:28:48 PM PDT 24 20593125 ps
T152 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.103493273 Jul 01 04:28:21 PM PDT 24 Jul 01 04:28:32 PM PDT 24 43669590 ps
T153 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2453125838 Jul 01 04:28:46 PM PDT 24 Jul 01 04:28:59 PM PDT 24 504235843 ps
T154 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4258374510 Jul 01 04:28:05 PM PDT 24 Jul 01 04:28:16 PM PDT 24 77095323 ps
T155 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1476762597 Jul 01 04:28:25 PM PDT 24 Jul 01 04:28:31 PM PDT 24 56747194 ps
T156 /workspace/coverage/cover_reg_top/18.i2c_intr_test.733042553 Jul 01 04:28:47 PM PDT 24 Jul 01 04:29:01 PM PDT 24 15372095 ps
T157 /workspace/coverage/cover_reg_top/31.i2c_intr_test.1160555149 Jul 01 04:28:26 PM PDT 24 Jul 01 04:28:31 PM PDT 24 80079255 ps
T158 /workspace/coverage/cover_reg_top/26.i2c_intr_test.1377460171 Jul 01 04:28:32 PM PDT 24 Jul 01 04:28:38 PM PDT 24 18468481 ps
T159 /workspace/coverage/cover_reg_top/46.i2c_intr_test.3404202086 Jul 01 04:28:49 PM PDT 24 Jul 01 04:29:03 PM PDT 24 28377596 ps
T160 /workspace/coverage/cover_reg_top/4.i2c_intr_test.2248117886 Jul 01 04:28:15 PM PDT 24 Jul 01 04:28:23 PM PDT 24 19028810 ps
T48 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1357305979 Jul 01 04:28:40 PM PDT 24 Jul 01 04:28:48 PM PDT 24 35905580 ps
T161 /workspace/coverage/cover_reg_top/35.i2c_intr_test.4173637648 Jul 01 04:28:26 PM PDT 24 Jul 01 04:28:31 PM PDT 24 17657809 ps
T162 /workspace/coverage/cover_reg_top/19.i2c_intr_test.1727345561 Jul 01 04:28:32 PM PDT 24 Jul 01 04:28:38 PM PDT 24 32524466 ps
T163 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2403922430 Jul 01 04:28:43 PM PDT 24 Jul 01 04:28:54 PM PDT 24 45062667 ps
T164 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1748530948 Jul 01 04:28:20 PM PDT 24 Jul 01 04:28:27 PM PDT 24 23415267 ps

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.395266333
Short name T4
Test name
Test status
Simulation time 334504649 ps
CPU time 2.36 seconds
Started Jul 01 04:28:34 PM PDT 24
Finished Jul 01 04:28:42 PM PDT 24
Peak memory 204572 kb
Host smart-df0e1a09-fd2d-48a9-bb54-3f3b9a7cf505
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395266333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.395266333
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3365881448
Short name T8
Test name
Test status
Simulation time 20392361 ps
CPU time 0.67 seconds
Started Jul 01 04:28:08 PM PDT 24
Finished Jul 01 04:28:18 PM PDT 24
Peak memory 204208 kb
Host smart-6229e51d-8ce4-4001-a19c-81a094334844
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365881448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3365881448
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3755149745
Short name T18
Test name
Test status
Simulation time 122903248 ps
CPU time 0.98 seconds
Started Jul 01 04:28:34 PM PDT 24
Finished Jul 01 04:28:41 PM PDT 24
Peak memory 204376 kb
Host smart-80351181-3ee4-4523-aa01-d7044686388f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755149745 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3755149745
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.352119608
Short name T10
Test name
Test status
Simulation time 58441407 ps
CPU time 0.71 seconds
Started Jul 01 04:28:44 PM PDT 24
Finished Jul 01 04:28:55 PM PDT 24
Peak memory 204172 kb
Host smart-85b358b7-ae9b-43ff-a268-e2288e3954c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352119608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.352119608
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.423893285
Short name T2
Test name
Test status
Simulation time 66650811 ps
CPU time 0.77 seconds
Started Jul 01 04:28:06 PM PDT 24
Finished Jul 01 04:28:19 PM PDT 24
Peak memory 204288 kb
Host smart-235089de-122b-44b6-b8c4-83a50422ed96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423893285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.423893285
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3281527543
Short name T16
Test name
Test status
Simulation time 197862774 ps
CPU time 2.07 seconds
Started Jul 01 04:28:24 PM PDT 24
Finished Jul 01 04:28:31 PM PDT 24
Peak memory 204468 kb
Host smart-6692c17e-13f9-42bb-8564-487dc4e1c507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281527543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3281527543
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1357305979
Short name T48
Test name
Test status
Simulation time 35905580 ps
CPU time 0.82 seconds
Started Jul 01 04:28:40 PM PDT 24
Finished Jul 01 04:28:48 PM PDT 24
Peak memory 204616 kb
Host smart-48ed5781-ee3b-4275-8b89-54c09e375cf1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357305979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1357305979
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3944463943
Short name T69
Test name
Test status
Simulation time 62563083 ps
CPU time 0.69 seconds
Started Jul 01 04:28:28 PM PDT 24
Finished Jul 01 04:28:33 PM PDT 24
Peak memory 204200 kb
Host smart-21c367cf-7eb5-4bbe-a4e2-a8b14450cf83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944463943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3944463943
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3935923074
Short name T50
Test name
Test status
Simulation time 73362919 ps
CPU time 1.28 seconds
Started Jul 01 04:28:13 PM PDT 24
Finished Jul 01 04:28:22 PM PDT 24
Peak memory 204444 kb
Host smart-75e6caf9-c24a-4a1c-8e77-621c98d6176b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935923074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.3935923074
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.2716882702
Short name T73
Test name
Test status
Simulation time 14385359 ps
CPU time 0.65 seconds
Started Jul 01 04:28:18 PM PDT 24
Finished Jul 01 04:28:24 PM PDT 24
Peak memory 204244 kb
Host smart-84be90a4-c87d-41c5-a5ee-5e80236d8e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716882702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2716882702
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3022063900
Short name T64
Test name
Test status
Simulation time 219305896 ps
CPU time 1.16 seconds
Started Jul 01 04:28:30 PM PDT 24
Finished Jul 01 04:28:36 PM PDT 24
Peak memory 204328 kb
Host smart-9415997d-5e81-4caa-9c62-d2d3128dcce3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022063900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3022063900
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2817963171
Short name T59
Test name
Test status
Simulation time 129953159 ps
CPU time 2.24 seconds
Started Jul 01 04:28:42 PM PDT 24
Finished Jul 01 04:28:53 PM PDT 24
Peak memory 204376 kb
Host smart-60886ad8-b5e2-4ea3-9f4a-3040f4bbc8bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817963171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2817963171
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.3027344251
Short name T118
Test name
Test status
Simulation time 61709518 ps
CPU time 0.68 seconds
Started Jul 01 04:28:22 PM PDT 24
Finished Jul 01 04:28:28 PM PDT 24
Peak memory 204212 kb
Host smart-ec4976e0-e155-42ed-8df7-11d0547d212d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027344251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3027344251
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.2176119456
Short name T68
Test name
Test status
Simulation time 38318535 ps
CPU time 0.7 seconds
Started Jul 01 04:28:30 PM PDT 24
Finished Jul 01 04:28:35 PM PDT 24
Peak memory 204208 kb
Host smart-09db1fc2-bcc8-492c-ba21-2c3a5126ad98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176119456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2176119456
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1818731012
Short name T5
Test name
Test status
Simulation time 589910330 ps
CPU time 2.48 seconds
Started Jul 01 04:28:28 PM PDT 24
Finished Jul 01 04:28:35 PM PDT 24
Peak memory 204344 kb
Host smart-130ac093-2c90-46d2-8107-8d1045da86c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818731012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1818731012
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4027511437
Short name T20
Test name
Test status
Simulation time 47541340 ps
CPU time 2.3 seconds
Started Jul 01 04:28:37 PM PDT 24
Finished Jul 01 04:28:45 PM PDT 24
Peak memory 204408 kb
Host smart-b9694260-ab10-45c3-95e8-a757000cfd9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027511437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.4027511437
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1950848724
Short name T56
Test name
Test status
Simulation time 286810203 ps
CPU time 2.17 seconds
Started Jul 01 04:28:17 PM PDT 24
Finished Jul 01 04:28:25 PM PDT 24
Peak memory 204352 kb
Host smart-1025f273-6239-4559-b5a2-84f053910b97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950848724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1950848724
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2130904813
Short name T55
Test name
Test status
Simulation time 284572348 ps
CPU time 1.6 seconds
Started Jul 01 04:28:27 PM PDT 24
Finished Jul 01 04:28:34 PM PDT 24
Peak memory 204528 kb
Host smart-9791010e-017a-4694-a23f-238315f02d04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130904813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2130904813
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2786350669
Short name T45
Test name
Test status
Simulation time 621146757 ps
CPU time 2.04 seconds
Started Jul 01 04:28:07 PM PDT 24
Finished Jul 01 04:28:19 PM PDT 24
Peak memory 204380 kb
Host smart-8674fcd3-b90b-4401-aac0-8a9eaab1cc36
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786350669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2786350669
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.164446759
Short name T146
Test name
Test status
Simulation time 75990529 ps
CPU time 3.11 seconds
Started Jul 01 04:28:33 PM PDT 24
Finished Jul 01 04:28:41 PM PDT 24
Peak memory 204388 kb
Host smart-9a0cbd79-bb10-43c3-988b-ba5393dbad8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164446759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.164446759
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.710771506
Short name T46
Test name
Test status
Simulation time 17133322 ps
CPU time 0.65 seconds
Started Jul 01 04:28:05 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 204256 kb
Host smart-6614ba1c-78e7-4d97-bf7d-b1f42b3ff28b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710771506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.710771506
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4258374510
Short name T154
Test name
Test status
Simulation time 77095323 ps
CPU time 0.81 seconds
Started Jul 01 04:28:05 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 204368 kb
Host smart-1f7b957b-d4b7-4856-b67f-8542fe961e39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258374510 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.4258374510
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1661807888
Short name T139
Test name
Test status
Simulation time 28298828 ps
CPU time 0.68 seconds
Started Jul 01 04:28:06 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 204196 kb
Host smart-dec90f66-0f3a-4e96-b71d-5bb37626ddd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661807888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1661807888
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2959848107
Short name T81
Test name
Test status
Simulation time 39281113 ps
CPU time 0.89 seconds
Started Jul 01 04:28:03 PM PDT 24
Finished Jul 01 04:28:14 PM PDT 24
Peak memory 204288 kb
Host smart-afb62245-5732-482d-9c60-79d288e381c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959848107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2959848107
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3336117653
Short name T109
Test name
Test status
Simulation time 85926177 ps
CPU time 2.22 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:02 PM PDT 24
Peak memory 204560 kb
Host smart-59907118-9bf8-40ef-9e08-2d69d7b7c18e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336117653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3336117653
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3844545677
Short name T144
Test name
Test status
Simulation time 81387557 ps
CPU time 1.4 seconds
Started Jul 01 04:28:12 PM PDT 24
Finished Jul 01 04:28:22 PM PDT 24
Peak memory 204376 kb
Host smart-2d995b4e-8613-4078-9963-8c149570cd40
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844545677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3844545677
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.800410317
Short name T149
Test name
Test status
Simulation time 463998759 ps
CPU time 3.39 seconds
Started Jul 01 04:28:21 PM PDT 24
Finished Jul 01 04:28:30 PM PDT 24
Peak memory 204432 kb
Host smart-d3fbd765-d871-4553-ae96-7cc3c4280f58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800410317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.800410317
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1578596350
Short name T130
Test name
Test status
Simulation time 28712418 ps
CPU time 0.85 seconds
Started Jul 01 04:28:05 PM PDT 24
Finished Jul 01 04:28:15 PM PDT 24
Peak memory 204316 kb
Host smart-190bc7ae-d8ed-4492-b083-200586f90820
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578596350 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1578596350
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2952487248
Short name T113
Test name
Test status
Simulation time 78219367 ps
CPU time 0.75 seconds
Started Jul 01 04:28:03 PM PDT 24
Finished Jul 01 04:28:13 PM PDT 24
Peak memory 204300 kb
Host smart-33522b0c-251d-4ebf-8caa-7c62bf565ce2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952487248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2952487248
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.274654497
Short name T89
Test name
Test status
Simulation time 56507677 ps
CPU time 0.85 seconds
Started Jul 01 04:28:18 PM PDT 24
Finished Jul 01 04:28:29 PM PDT 24
Peak memory 204300 kb
Host smart-6a1a95e7-497a-4ec2-b6fb-98caaf5a921c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274654497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.274654497
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3911486743
Short name T106
Test name
Test status
Simulation time 198724901 ps
CPU time 1.74 seconds
Started Jul 01 04:28:14 PM PDT 24
Finished Jul 01 04:28:23 PM PDT 24
Peak memory 204460 kb
Host smart-561adcd1-331e-4bd8-a459-345bb2037310
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911486743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3911486743
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2225733580
Short name T61
Test name
Test status
Simulation time 534184063 ps
CPU time 2.29 seconds
Started Jul 01 04:28:04 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 204432 kb
Host smart-817bf922-051e-4ed7-a8c3-9fbed06056fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225733580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2225733580
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1748530948
Short name T164
Test name
Test status
Simulation time 23415267 ps
CPU time 0.93 seconds
Started Jul 01 04:28:20 PM PDT 24
Finished Jul 01 04:28:27 PM PDT 24
Peak memory 204368 kb
Host smart-87427cae-c5c5-45e3-98d4-e276184c393a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748530948 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1748530948
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3186741630
Short name T80
Test name
Test status
Simulation time 49655630 ps
CPU time 0.75 seconds
Started Jul 01 04:28:29 PM PDT 24
Finished Jul 01 04:28:34 PM PDT 24
Peak memory 204452 kb
Host smart-8708c6aa-8ceb-4ccd-8cc1-65735ba66162
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186741630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3186741630
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.409951683
Short name T150
Test name
Test status
Simulation time 35177063 ps
CPU time 0.67 seconds
Started Jul 01 04:28:21 PM PDT 24
Finished Jul 01 04:28:26 PM PDT 24
Peak memory 204208 kb
Host smart-74d92034-5077-4059-aa0e-e6cb0a3496cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409951683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.409951683
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.367600120
Short name T131
Test name
Test status
Simulation time 57651309 ps
CPU time 0.75 seconds
Started Jul 01 04:28:14 PM PDT 24
Finished Jul 01 04:28:22 PM PDT 24
Peak memory 204332 kb
Host smart-cccbf3af-4bad-4a95-ba63-73f0e1a00bb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367600120 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.367600120
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1800829926
Short name T142
Test name
Test status
Simulation time 54741208 ps
CPU time 0.89 seconds
Started Jul 01 04:28:30 PM PDT 24
Finished Jul 01 04:28:36 PM PDT 24
Peak memory 204556 kb
Host smart-e20da83b-0fe6-42b0-b17d-3315682515e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800829926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1800829926
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.787532293
Short name T98
Test name
Test status
Simulation time 19680081 ps
CPU time 0.68 seconds
Started Jul 01 04:28:32 PM PDT 24
Finished Jul 01 04:28:39 PM PDT 24
Peak memory 204168 kb
Host smart-d302f5e2-98ed-478b-a06d-5c459c88b2cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787532293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.787532293
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1957234517
Short name T65
Test name
Test status
Simulation time 34018879 ps
CPU time 0.91 seconds
Started Jul 01 04:28:26 PM PDT 24
Finished Jul 01 04:28:37 PM PDT 24
Peak memory 204248 kb
Host smart-23840817-2383-4074-8b18-b56e54ab3725
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957234517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1957234517
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1827525524
Short name T19
Test name
Test status
Simulation time 486794905 ps
CPU time 2.7 seconds
Started Jul 01 04:28:34 PM PDT 24
Finished Jul 01 04:28:43 PM PDT 24
Peak memory 212844 kb
Host smart-a646a3e1-b9d4-446a-ba20-b0848bcb4ffa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827525524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1827525524
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2266159279
Short name T145
Test name
Test status
Simulation time 532140796 ps
CPU time 2.35 seconds
Started Jul 01 04:28:20 PM PDT 24
Finished Jul 01 04:28:28 PM PDT 24
Peak memory 204344 kb
Host smart-f345bbef-bf9e-4d94-9656-620a3382470f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266159279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2266159279
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1706150807
Short name T123
Test name
Test status
Simulation time 25610336 ps
CPU time 0.84 seconds
Started Jul 01 04:28:20 PM PDT 24
Finished Jul 01 04:28:26 PM PDT 24
Peak memory 204596 kb
Host smart-05a1876d-9c98-4469-98b4-434f6af273a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706150807 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1706150807
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2594319266
Short name T137
Test name
Test status
Simulation time 40121847 ps
CPU time 0.76 seconds
Started Jul 01 04:28:42 PM PDT 24
Finished Jul 01 04:28:52 PM PDT 24
Peak memory 204264 kb
Host smart-28523f21-f87c-4856-ae67-f919175c35f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594319266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2594319266
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3628816490
Short name T114
Test name
Test status
Simulation time 62703916 ps
CPU time 1.19 seconds
Started Jul 01 04:28:17 PM PDT 24
Finished Jul 01 04:28:25 PM PDT 24
Peak memory 204564 kb
Host smart-b91855ea-2fbf-451d-99b9-6d87f1eacefa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628816490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3628816490
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1476762597
Short name T155
Test name
Test status
Simulation time 56747194 ps
CPU time 1.92 seconds
Started Jul 01 04:28:25 PM PDT 24
Finished Jul 01 04:28:31 PM PDT 24
Peak memory 204480 kb
Host smart-d001c4fa-0242-4bd8-9bf8-92c0e21c7fbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476762597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1476762597
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1135632401
Short name T119
Test name
Test status
Simulation time 53962888 ps
CPU time 1.37 seconds
Started Jul 01 04:28:31 PM PDT 24
Finished Jul 01 04:28:38 PM PDT 24
Peak memory 204380 kb
Host smart-722e00c9-dc83-4711-8d0d-07b0f06f31b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135632401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1135632401
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.250223672
Short name T116
Test name
Test status
Simulation time 92187155 ps
CPU time 1.34 seconds
Started Jul 01 04:28:32 PM PDT 24
Finished Jul 01 04:28:38 PM PDT 24
Peak memory 204692 kb
Host smart-4ca2083d-5574-44b6-b27b-39a18518c13e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250223672 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.250223672
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1479378934
Short name T33
Test name
Test status
Simulation time 83059977 ps
CPU time 0.81 seconds
Started Jul 01 04:28:38 PM PDT 24
Finished Jul 01 04:28:45 PM PDT 24
Peak memory 204428 kb
Host smart-9d68d293-721a-4177-9ce4-ce10259acc93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479378934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1479378934
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.1320056748
Short name T70
Test name
Test status
Simulation time 31630997 ps
CPU time 0.68 seconds
Started Jul 01 04:28:25 PM PDT 24
Finished Jul 01 04:28:30 PM PDT 24
Peak memory 204200 kb
Host smart-bad565de-a4b1-44f8-8461-baa50687e025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320056748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1320056748
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.542370540
Short name T27
Test name
Test status
Simulation time 58321723 ps
CPU time 0.89 seconds
Started Jul 01 04:28:41 PM PDT 24
Finished Jul 01 04:28:50 PM PDT 24
Peak memory 204284 kb
Host smart-f8ae9901-446c-440c-b2ad-e3118a24c2f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542370540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou
tstanding.542370540
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1793444047
Short name T24
Test name
Test status
Simulation time 86866379 ps
CPU time 1.71 seconds
Started Jul 01 04:28:29 PM PDT 24
Finished Jul 01 04:28:35 PM PDT 24
Peak memory 204420 kb
Host smart-523c2763-2ba1-42b7-ad99-cbb037633c03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793444047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1793444047
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2701963487
Short name T100
Test name
Test status
Simulation time 51972994 ps
CPU time 0.86 seconds
Started Jul 01 04:28:20 PM PDT 24
Finished Jul 01 04:28:26 PM PDT 24
Peak memory 204356 kb
Host smart-206347b4-9a9c-416e-9512-e3092159894c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701963487 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.2701963487
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3195459740
Short name T78
Test name
Test status
Simulation time 166454835 ps
CPU time 0.71 seconds
Started Jul 01 04:28:34 PM PDT 24
Finished Jul 01 04:28:41 PM PDT 24
Peak memory 204328 kb
Host smart-654d819c-4104-4791-ae6f-5eda181ca1c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195459740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3195459740
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.4088718642
Short name T72
Test name
Test status
Simulation time 20937496 ps
CPU time 0.67 seconds
Started Jul 01 04:28:43 PM PDT 24
Finished Jul 01 04:28:53 PM PDT 24
Peak memory 204192 kb
Host smart-a21a4e77-43d5-41e6-acec-8fe45911f8c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088718642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.4088718642
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.4152068344
Short name T49
Test name
Test status
Simulation time 247089007 ps
CPU time 0.81 seconds
Started Jul 01 04:28:43 PM PDT 24
Finished Jul 01 04:28:55 PM PDT 24
Peak memory 204300 kb
Host smart-31217bb6-b175-4668-8ed0-c411f56204a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152068344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.4152068344
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1883946139
Short name T136
Test name
Test status
Simulation time 572701055 ps
CPU time 2.86 seconds
Started Jul 01 04:28:28 PM PDT 24
Finished Jul 01 04:28:35 PM PDT 24
Peak memory 204484 kb
Host smart-bff9d2f8-cbea-4df3-b891-309c4b1ce4b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883946139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1883946139
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1909028271
Short name T17
Test name
Test status
Simulation time 166372514 ps
CPU time 2.53 seconds
Started Jul 01 04:28:23 PM PDT 24
Finished Jul 01 04:28:31 PM PDT 24
Peak memory 204372 kb
Host smart-8f1bad42-7eef-4b9f-97af-70cf902ecdd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909028271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1909028271
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.949933781
Short name T86
Test name
Test status
Simulation time 120118631 ps
CPU time 1.24 seconds
Started Jul 01 04:28:31 PM PDT 24
Finished Jul 01 04:28:38 PM PDT 24
Peak memory 204504 kb
Host smart-d18ad226-5542-43df-b58f-611e3d0370df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949933781 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.949933781
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1128179302
Short name T35
Test name
Test status
Simulation time 20277774 ps
CPU time 0.77 seconds
Started Jul 01 04:28:17 PM PDT 24
Finished Jul 01 04:28:24 PM PDT 24
Peak memory 204300 kb
Host smart-9b23744a-9f73-4802-83ab-fd06822f1a20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128179302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1128179302
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3039711404
Short name T147
Test name
Test status
Simulation time 76709898 ps
CPU time 0.69 seconds
Started Jul 01 04:28:35 PM PDT 24
Finished Jul 01 04:28:42 PM PDT 24
Peak memory 204304 kb
Host smart-f876881d-61cc-40e9-8cac-2d5859b73365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039711404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3039711404
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.852446635
Short name T29
Test name
Test status
Simulation time 33168986 ps
CPU time 0.9 seconds
Started Jul 01 04:28:38 PM PDT 24
Finished Jul 01 04:28:45 PM PDT 24
Peak memory 204268 kb
Host smart-18510676-ce05-4fdf-8d36-4143271ac2aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852446635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_ou
tstanding.852446635
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1307372159
Short name T126
Test name
Test status
Simulation time 111134502 ps
CPU time 2.75 seconds
Started Jul 01 04:28:33 PM PDT 24
Finished Jul 01 04:28:42 PM PDT 24
Peak memory 219944 kb
Host smart-c187ff8a-8f84-4b83-a474-a0a7f83947e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307372159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1307372159
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3038435657
Short name T3
Test name
Test status
Simulation time 446576096 ps
CPU time 1.51 seconds
Started Jul 01 04:28:17 PM PDT 24
Finished Jul 01 04:28:24 PM PDT 24
Peak memory 204376 kb
Host smart-cb888be4-90cb-481d-9694-56b512869099
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038435657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3038435657
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2974467673
Short name T15
Test name
Test status
Simulation time 148841815 ps
CPU time 0.99 seconds
Started Jul 01 04:28:33 PM PDT 24
Finished Jul 01 04:28:39 PM PDT 24
Peak memory 204332 kb
Host smart-4e7a05ec-a969-4584-a035-73060f5b82a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974467673 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2974467673
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.294753250
Short name T101
Test name
Test status
Simulation time 51974603 ps
CPU time 0.69 seconds
Started Jul 01 04:28:32 PM PDT 24
Finished Jul 01 04:28:39 PM PDT 24
Peak memory 204256 kb
Host smart-aa1fadf1-afd1-412f-955c-df5d11c6127e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294753250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.294753250
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1184003185
Short name T51
Test name
Test status
Simulation time 52384577 ps
CPU time 1.22 seconds
Started Jul 01 04:28:34 PM PDT 24
Finished Jul 01 04:28:41 PM PDT 24
Peak memory 204408 kb
Host smart-3fd3d334-24ab-423a-b354-8d6264f69ad0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184003185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1184003185
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2403922430
Short name T163
Test name
Test status
Simulation time 45062667 ps
CPU time 2.21 seconds
Started Jul 01 04:28:43 PM PDT 24
Finished Jul 01 04:28:54 PM PDT 24
Peak memory 212868 kb
Host smart-f74d29c8-bc83-41bc-8933-ca9eb7812a71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403922430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2403922430
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.4069134626
Short name T63
Test name
Test status
Simulation time 78135634 ps
CPU time 1.51 seconds
Started Jul 01 04:28:32 PM PDT 24
Finished Jul 01 04:28:39 PM PDT 24
Peak memory 204368 kb
Host smart-dd1092e3-113d-4a26-83a0-118f66604ede
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069134626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.4069134626
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3579906678
Short name T111
Test name
Test status
Simulation time 53155786 ps
CPU time 0.72 seconds
Started Jul 01 04:28:29 PM PDT 24
Finished Jul 01 04:28:34 PM PDT 24
Peak memory 204304 kb
Host smart-6e938d48-f959-4166-9e4f-87c020d647d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579906678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3579906678
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.4268334387
Short name T74
Test name
Test status
Simulation time 17336610 ps
CPU time 0.67 seconds
Started Jul 01 04:28:23 PM PDT 24
Finished Jul 01 04:28:29 PM PDT 24
Peak memory 204192 kb
Host smart-4daa5bf9-4d1b-4fb7-b5c8-f88efb3d9b92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268334387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.4268334387
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.495011532
Short name T66
Test name
Test status
Simulation time 34724635 ps
CPU time 0.84 seconds
Started Jul 01 04:28:46 PM PDT 24
Finished Jul 01 04:28:58 PM PDT 24
Peak memory 204296 kb
Host smart-0e58f6ad-884f-4558-a185-7fe59695fe2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495011532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou
tstanding.495011532
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3637272433
Short name T95
Test name
Test status
Simulation time 186352831 ps
CPU time 1.31 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:01 PM PDT 24
Peak memory 204456 kb
Host smart-7c0d03c5-b0ae-41cd-aa53-1ac07505e156
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637272433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3637272433
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2147497845
Short name T22
Test name
Test status
Simulation time 56577453 ps
CPU time 0.91 seconds
Started Jul 01 04:28:39 PM PDT 24
Finished Jul 01 04:28:47 PM PDT 24
Peak memory 204540 kb
Host smart-d670f361-7c86-4335-a9fa-caac97e0b16e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147497845 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2147497845
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.325730288
Short name T151
Test name
Test status
Simulation time 20593125 ps
CPU time 0.68 seconds
Started Jul 01 04:28:40 PM PDT 24
Finished Jul 01 04:28:48 PM PDT 24
Peak memory 204236 kb
Host smart-965d0e7f-3f0f-4c57-b751-30a7c9d3a965
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325730288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.325730288
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.733042553
Short name T156
Test name
Test status
Simulation time 15372095 ps
CPU time 0.64 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:01 PM PDT 24
Peak memory 204204 kb
Host smart-c65ff608-2a0e-40ac-a463-4241e8851554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733042553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.733042553
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.310606949
Short name T53
Test name
Test status
Simulation time 131575967 ps
CPU time 1.16 seconds
Started Jul 01 04:28:39 PM PDT 24
Finished Jul 01 04:28:46 PM PDT 24
Peak memory 204408 kb
Host smart-8111beea-5d3e-4d78-90fa-b5baccade1de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310606949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_ou
tstanding.310606949
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1950932019
Short name T14
Test name
Test status
Simulation time 153188976 ps
CPU time 2.71 seconds
Started Jul 01 04:28:33 PM PDT 24
Finished Jul 01 04:28:41 PM PDT 24
Peak memory 204420 kb
Host smart-93a56f26-9171-4587-8307-60f310c060ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950932019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1950932019
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.293638300
Short name T134
Test name
Test status
Simulation time 600210626 ps
CPU time 1.61 seconds
Started Jul 01 04:28:22 PM PDT 24
Finished Jul 01 04:28:28 PM PDT 24
Peak memory 204380 kb
Host smart-82078503-2e7c-492a-b7b6-2d46557e3860
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293638300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.293638300
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2130567169
Short name T76
Test name
Test status
Simulation time 29237955 ps
CPU time 1.14 seconds
Started Jul 01 04:28:30 PM PDT 24
Finished Jul 01 04:28:35 PM PDT 24
Peak memory 204460 kb
Host smart-a69ab4a6-2a5b-4583-a88a-26a917036583
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130567169 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2130567169
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.196022058
Short name T37
Test name
Test status
Simulation time 26819183 ps
CPU time 0.8 seconds
Started Jul 01 04:28:41 PM PDT 24
Finished Jul 01 04:28:50 PM PDT 24
Peak memory 204628 kb
Host smart-ba7f74d4-4ab4-451a-bcb9-d2133d3c613e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196022058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.196022058
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1727345561
Short name T162
Test name
Test status
Simulation time 32524466 ps
CPU time 0.7 seconds
Started Jul 01 04:28:32 PM PDT 24
Finished Jul 01 04:28:38 PM PDT 24
Peak memory 204440 kb
Host smart-7d58c5bf-7e7b-42b4-bea7-46a856b53f86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727345561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1727345561
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.891172909
Short name T84
Test name
Test status
Simulation time 84472515 ps
CPU time 1.18 seconds
Started Jul 01 04:28:37 PM PDT 24
Finished Jul 01 04:28:44 PM PDT 24
Peak memory 204488 kb
Host smart-a1d05c5b-4269-40dd-a67b-f6c5d15dbd75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891172909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_ou
tstanding.891172909
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2605068916
Short name T124
Test name
Test status
Simulation time 552153280 ps
CPU time 2.77 seconds
Started Jul 01 04:28:34 PM PDT 24
Finished Jul 01 04:28:43 PM PDT 24
Peak memory 204496 kb
Host smart-859bf275-6d70-4326-baa9-835798289433
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605068916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2605068916
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2450780056
Short name T36
Test name
Test status
Simulation time 1128697747 ps
CPU time 2.29 seconds
Started Jul 01 04:28:30 PM PDT 24
Finished Jul 01 04:28:37 PM PDT 24
Peak memory 204368 kb
Host smart-0204650d-b226-4317-9e37-4545b56c816b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450780056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2450780056
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1812370146
Short name T47
Test name
Test status
Simulation time 24201063 ps
CPU time 0.77 seconds
Started Jul 01 04:28:51 PM PDT 24
Finished Jul 01 04:29:06 PM PDT 24
Peak memory 204312 kb
Host smart-117c71fe-f108-47c2-85cb-2f21e6cf04fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812370146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1812370146
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.103493273
Short name T152
Test name
Test status
Simulation time 43669590 ps
CPU time 1 seconds
Started Jul 01 04:28:21 PM PDT 24
Finished Jul 01 04:28:32 PM PDT 24
Peak memory 204348 kb
Host smart-4352d679-2321-4605-938f-54bde295c543
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103493273 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.103493273
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2517487979
Short name T34
Test name
Test status
Simulation time 37581583 ps
CPU time 0.67 seconds
Started Jul 01 04:28:05 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 204300 kb
Host smart-b63e3606-7e68-472e-8b97-6454a77f6879
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517487979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2517487979
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3061031520
Short name T94
Test name
Test status
Simulation time 44742500 ps
CPU time 0.85 seconds
Started Jul 01 04:28:21 PM PDT 24
Finished Jul 01 04:28:27 PM PDT 24
Peak memory 204292 kb
Host smart-554b6939-062e-4d2a-8fc1-585ec5f619d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061031520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.3061031520
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1504824159
Short name T96
Test name
Test status
Simulation time 799686890 ps
CPU time 1.89 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 204604 kb
Host smart-94b6c57f-73a8-4444-a3ed-1c1dbb4267b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504824159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1504824159
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2508513596
Short name T54
Test name
Test status
Simulation time 336846598 ps
CPU time 1.66 seconds
Started Jul 01 04:28:27 PM PDT 24
Finished Jul 01 04:28:33 PM PDT 24
Peak memory 204592 kb
Host smart-843e0e45-709f-4174-8074-4c55f193e13c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508513596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2508513596
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.18215884
Short name T140
Test name
Test status
Simulation time 68361632 ps
CPU time 0.71 seconds
Started Jul 01 04:28:37 PM PDT 24
Finished Jul 01 04:28:43 PM PDT 24
Peak memory 204212 kb
Host smart-6d7436a3-0f2b-44b5-80c7-037641bc4b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18215884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.18215884
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1685434713
Short name T120
Test name
Test status
Simulation time 31406348 ps
CPU time 0.72 seconds
Started Jul 01 04:28:40 PM PDT 24
Finished Jul 01 04:28:48 PM PDT 24
Peak memory 204452 kb
Host smart-a1797031-210b-4abf-b82e-e07bbe714cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685434713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1685434713
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.4145764092
Short name T133
Test name
Test status
Simulation time 49206526 ps
CPU time 0.68 seconds
Started Jul 01 04:28:42 PM PDT 24
Finished Jul 01 04:28:51 PM PDT 24
Peak memory 204188 kb
Host smart-5eeb8429-3515-49aa-a93e-cdcf05c3f151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145764092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.4145764092
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.1716456134
Short name T121
Test name
Test status
Simulation time 39923377 ps
CPU time 0.74 seconds
Started Jul 01 04:28:33 PM PDT 24
Finished Jul 01 04:28:39 PM PDT 24
Peak memory 204392 kb
Host smart-50feae6d-7bd1-4daf-baab-90843491c2a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716456134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1716456134
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.357352384
Short name T122
Test name
Test status
Simulation time 78280120 ps
CPU time 0.7 seconds
Started Jul 01 04:28:33 PM PDT 24
Finished Jul 01 04:28:40 PM PDT 24
Peak memory 204212 kb
Host smart-b7972ec2-1804-444b-95c3-a45b8cf1acc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357352384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.357352384
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.1377460171
Short name T158
Test name
Test status
Simulation time 18468481 ps
CPU time 0.71 seconds
Started Jul 01 04:28:32 PM PDT 24
Finished Jul 01 04:28:38 PM PDT 24
Peak memory 204200 kb
Host smart-07102002-2aa0-4035-a6f3-9595ff82088b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377460171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1377460171
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.1821781238
Short name T9
Test name
Test status
Simulation time 18220651 ps
CPU time 0.67 seconds
Started Jul 01 04:28:43 PM PDT 24
Finished Jul 01 04:28:54 PM PDT 24
Peak memory 204196 kb
Host smart-a4e835ee-cd77-4ef9-b43c-2ad6e88f425f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821781238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.1821781238
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3560892688
Short name T108
Test name
Test status
Simulation time 73451168 ps
CPU time 0.68 seconds
Started Jul 01 04:28:31 PM PDT 24
Finished Jul 01 04:28:37 PM PDT 24
Peak memory 204212 kb
Host smart-3d52f42e-d739-47d1-8e02-7039cdfb9ccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560892688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3560892688
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1140779681
Short name T127
Test name
Test status
Simulation time 106269322 ps
CPU time 1.48 seconds
Started Jul 01 04:28:26 PM PDT 24
Finished Jul 01 04:28:32 PM PDT 24
Peak memory 204344 kb
Host smart-24a75e62-c9c5-4218-b3fa-5627368882c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140779681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1140779681
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1201752248
Short name T21
Test name
Test status
Simulation time 671002734 ps
CPU time 5.21 seconds
Started Jul 01 04:28:06 PM PDT 24
Finished Jul 01 04:28:21 PM PDT 24
Peak memory 204432 kb
Host smart-1d14e0a0-70d2-432d-bde0-587c5727d832
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201752248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1201752248
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1003129794
Short name T44
Test name
Test status
Simulation time 26961708 ps
CPU time 0.8 seconds
Started Jul 01 04:28:28 PM PDT 24
Finished Jul 01 04:28:34 PM PDT 24
Peak memory 204360 kb
Host smart-444e0192-a0d0-4c26-b90f-c353d53b74aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003129794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1003129794
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.512688607
Short name T102
Test name
Test status
Simulation time 179790545 ps
CPU time 1.07 seconds
Started Jul 01 04:28:31 PM PDT 24
Finished Jul 01 04:28:37 PM PDT 24
Peak memory 204356 kb
Host smart-15d4bf89-683a-4ea1-b77a-75e9fcc1ce93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512688607 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.512688607
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.703260273
Short name T93
Test name
Test status
Simulation time 20137559 ps
CPU time 0.68 seconds
Started Jul 01 04:28:11 PM PDT 24
Finished Jul 01 04:28:21 PM PDT 24
Peak memory 204260 kb
Host smart-a85eb73d-f35d-4f8c-9595-198e26782f62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703260273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.703260273
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.3411522189
Short name T83
Test name
Test status
Simulation time 44723995 ps
CPU time 0.69 seconds
Started Jul 01 04:28:20 PM PDT 24
Finished Jul 01 04:28:26 PM PDT 24
Peak memory 204144 kb
Host smart-9eb957dd-ca29-4809-9042-07d71c6ad543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411522189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3411522189
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1716875001
Short name T25
Test name
Test status
Simulation time 36258999 ps
CPU time 0.85 seconds
Started Jul 01 04:28:07 PM PDT 24
Finished Jul 01 04:28:18 PM PDT 24
Peak memory 204252 kb
Host smart-40f8d83c-bc27-4a4a-bfdd-578b43d4f64a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716875001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1716875001
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.640752291
Short name T6
Test name
Test status
Simulation time 99476718 ps
CPU time 2.33 seconds
Started Jul 01 04:28:48 PM PDT 24
Finished Jul 01 04:29:04 PM PDT 24
Peak memory 204480 kb
Host smart-2e21f52b-f8cd-4805-a948-a5c268e42a4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640752291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.640752291
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3683752753
Short name T57
Test name
Test status
Simulation time 854939401 ps
CPU time 2.51 seconds
Started Jul 01 04:28:27 PM PDT 24
Finished Jul 01 04:28:34 PM PDT 24
Peak memory 204372 kb
Host smart-bb99b22d-92eb-4819-bd7f-e7196ba09779
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683752753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3683752753
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.3548520572
Short name T1
Test name
Test status
Simulation time 18619394 ps
CPU time 0.73 seconds
Started Jul 01 04:28:32 PM PDT 24
Finished Jul 01 04:28:38 PM PDT 24
Peak memory 204204 kb
Host smart-4e388e23-0f70-4d6c-8f57-7633c3ee5a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548520572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3548520572
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.1160555149
Short name T157
Test name
Test status
Simulation time 80079255 ps
CPU time 0.65 seconds
Started Jul 01 04:28:26 PM PDT 24
Finished Jul 01 04:28:31 PM PDT 24
Peak memory 204184 kb
Host smart-ceba20fe-3dd8-4519-af7a-b3cdd6d0f07f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160555149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.1160555149
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.3843975792
Short name T138
Test name
Test status
Simulation time 87590314 ps
CPU time 0.67 seconds
Started Jul 01 04:28:45 PM PDT 24
Finished Jul 01 04:28:59 PM PDT 24
Peak memory 204192 kb
Host smart-506b97be-7ba4-41ad-aaf8-0a6cf4cbf386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843975792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3843975792
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.16192979
Short name T75
Test name
Test status
Simulation time 19473553 ps
CPU time 0.62 seconds
Started Jul 01 04:28:33 PM PDT 24
Finished Jul 01 04:28:40 PM PDT 24
Peak memory 204208 kb
Host smart-f4e0a3ff-ad27-40a1-a7e7-8dfbd7d65051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16192979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.16192979
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.96983631
Short name T105
Test name
Test status
Simulation time 43264413 ps
CPU time 0.69 seconds
Started Jul 01 04:28:45 PM PDT 24
Finished Jul 01 04:28:57 PM PDT 24
Peak memory 204208 kb
Host smart-ba96b886-2589-46f0-b9e6-d77eafa4a03f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96983631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.96983631
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.4173637648
Short name T161
Test name
Test status
Simulation time 17657809 ps
CPU time 0.68 seconds
Started Jul 01 04:28:26 PM PDT 24
Finished Jul 01 04:28:31 PM PDT 24
Peak memory 204208 kb
Host smart-bc7e50bc-c4cd-45ea-8acb-a1d52b20fdc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173637648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.4173637648
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1130167814
Short name T103
Test name
Test status
Simulation time 18327042 ps
CPU time 0.69 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:00 PM PDT 24
Peak memory 204308 kb
Host smart-05875849-9fda-43a8-8458-955ae73629a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130167814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1130167814
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1506875111
Short name T71
Test name
Test status
Simulation time 113937893 ps
CPU time 0.65 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 204316 kb
Host smart-77039356-c875-43e8-8897-7bd79334e668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506875111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1506875111
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.351949445
Short name T43
Test name
Test status
Simulation time 27557605 ps
CPU time 0.67 seconds
Started Jul 01 04:28:39 PM PDT 24
Finished Jul 01 04:28:47 PM PDT 24
Peak memory 204164 kb
Host smart-8bf326ac-9fcc-442f-82a3-f8b314b93498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351949445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.351949445
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1122018669
Short name T110
Test name
Test status
Simulation time 30228792 ps
CPU time 0.68 seconds
Started Jul 01 04:28:30 PM PDT 24
Finished Jul 01 04:28:36 PM PDT 24
Peak memory 204160 kb
Host smart-d776048e-ed0a-40f2-9cc1-01e20079b118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122018669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1122018669
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.85144824
Short name T31
Test name
Test status
Simulation time 86604899 ps
CPU time 1.43 seconds
Started Jul 01 04:28:16 PM PDT 24
Finished Jul 01 04:28:24 PM PDT 24
Peak memory 204348 kb
Host smart-3c0bdd5a-3178-449e-b5c2-3ea370c92f41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85144824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.85144824
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3100100857
Short name T41
Test name
Test status
Simulation time 1176024166 ps
CPU time 3.8 seconds
Started Jul 01 04:28:27 PM PDT 24
Finished Jul 01 04:28:36 PM PDT 24
Peak memory 204584 kb
Host smart-917b38a3-f535-438b-8a63-fd307013336a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100100857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.3100100857
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.4246742567
Short name T30
Test name
Test status
Simulation time 24702404 ps
CPU time 0.78 seconds
Started Jul 01 04:28:27 PM PDT 24
Finished Jul 01 04:28:33 PM PDT 24
Peak memory 204220 kb
Host smart-867ad1cb-d9d6-4486-a07a-6bf9bda2bbc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246742567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.4246742567
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.370560958
Short name T141
Test name
Test status
Simulation time 28196733 ps
CPU time 0.82 seconds
Started Jul 01 04:28:48 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 204404 kb
Host smart-bc09244c-9b36-4b09-9cf2-06b87b2d30bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370560958 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.370560958
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2903776178
Short name T26
Test name
Test status
Simulation time 105556223 ps
CPU time 0.73 seconds
Started Jul 01 04:28:09 PM PDT 24
Finished Jul 01 04:28:20 PM PDT 24
Peak memory 204288 kb
Host smart-26bf1e22-a9bb-4df5-9617-476fd413b35e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903776178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2903776178
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.2248117886
Short name T160
Test name
Test status
Simulation time 19028810 ps
CPU time 0.71 seconds
Started Jul 01 04:28:15 PM PDT 24
Finished Jul 01 04:28:23 PM PDT 24
Peak memory 204244 kb
Host smart-01d5b7ed-b499-4630-97a1-90af1a5d8416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248117886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.2248117886
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2151125180
Short name T79
Test name
Test status
Simulation time 172508419 ps
CPU time 0.88 seconds
Started Jul 01 04:28:32 PM PDT 24
Finished Jul 01 04:28:38 PM PDT 24
Peak memory 204264 kb
Host smart-2c9bdee1-573e-4b36-9f66-79dcb80baa00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151125180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2151125180
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2112185209
Short name T148
Test name
Test status
Simulation time 32362543 ps
CPU time 1.02 seconds
Started Jul 01 04:28:32 PM PDT 24
Finished Jul 01 04:28:38 PM PDT 24
Peak memory 204520 kb
Host smart-c4b058be-71f3-4926-9532-2800aa002022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112185209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2112185209
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3983389650
Short name T62
Test name
Test status
Simulation time 83001580 ps
CPU time 2.24 seconds
Started Jul 01 04:28:14 PM PDT 24
Finished Jul 01 04:28:24 PM PDT 24
Peak memory 204540 kb
Host smart-1d9f6f3b-f1f0-4027-bdef-4b838f8c9290
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983389650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3983389650
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.92501835
Short name T132
Test name
Test status
Simulation time 43162738 ps
CPU time 0.7 seconds
Started Jul 01 04:28:34 PM PDT 24
Finished Jul 01 04:28:41 PM PDT 24
Peak memory 204556 kb
Host smart-5a252197-59f1-4f0a-a23a-fd12dc460cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92501835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.92501835
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.4103508340
Short name T99
Test name
Test status
Simulation time 18241577 ps
CPU time 0.69 seconds
Started Jul 01 04:28:39 PM PDT 24
Finished Jul 01 04:28:47 PM PDT 24
Peak memory 204544 kb
Host smart-1ac4f2b3-28c6-4c16-b3bc-5dc1ce58801a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103508340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.4103508340
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.319435850
Short name T107
Test name
Test status
Simulation time 30570305 ps
CPU time 0.72 seconds
Started Jul 01 04:28:40 PM PDT 24
Finished Jul 01 04:28:48 PM PDT 24
Peak memory 204240 kb
Host smart-bbd59146-7d3f-4af0-8b14-666e529bff76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319435850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.319435850
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.3035925500
Short name T117
Test name
Test status
Simulation time 17136246 ps
CPU time 0.66 seconds
Started Jul 01 04:28:46 PM PDT 24
Finished Jul 01 04:28:59 PM PDT 24
Peak memory 204336 kb
Host smart-65036563-1c44-4246-b865-53358d29eae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035925500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3035925500
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1570240433
Short name T52
Test name
Test status
Simulation time 49978641 ps
CPU time 0.66 seconds
Started Jul 01 04:28:29 PM PDT 24
Finished Jul 01 04:28:34 PM PDT 24
Peak memory 204212 kb
Host smart-3603386d-26b0-435b-993a-d2f4e29994b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570240433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1570240433
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.143996630
Short name T125
Test name
Test status
Simulation time 34511198 ps
CPU time 0.67 seconds
Started Jul 01 04:28:22 PM PDT 24
Finished Jul 01 04:28:27 PM PDT 24
Peak memory 204188 kb
Host smart-7e855b10-8eb1-48bd-8390-e6170dccd770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143996630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.143996630
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.3404202086
Short name T159
Test name
Test status
Simulation time 28377596 ps
CPU time 0.66 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 204212 kb
Host smart-eab16015-1d36-4634-940f-876925c04d75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404202086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3404202086
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.4174475062
Short name T67
Test name
Test status
Simulation time 16299753 ps
CPU time 0.67 seconds
Started Jul 01 04:28:50 PM PDT 24
Finished Jul 01 04:29:05 PM PDT 24
Peak memory 204196 kb
Host smart-e090cd83-6905-4a51-9439-801bf5e3b610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174475062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.4174475062
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.1425623994
Short name T11
Test name
Test status
Simulation time 65025086 ps
CPU time 0.68 seconds
Started Jul 01 04:29:04 PM PDT 24
Finished Jul 01 04:29:16 PM PDT 24
Peak memory 204196 kb
Host smart-2c0a1094-1d91-4340-8f76-f5a8d6ce09ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425623994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.1425623994
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2989238922
Short name T112
Test name
Test status
Simulation time 33566840 ps
CPU time 0.69 seconds
Started Jul 01 04:28:32 PM PDT 24
Finished Jul 01 04:28:38 PM PDT 24
Peak memory 204168 kb
Host smart-039c5d6e-279f-4258-9288-5ab236366cac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989238922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2989238922
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3413146850
Short name T85
Test name
Test status
Simulation time 128034061 ps
CPU time 1.04 seconds
Started Jul 01 04:28:22 PM PDT 24
Finished Jul 01 04:28:28 PM PDT 24
Peak memory 204440 kb
Host smart-fef2b786-d275-4653-9a63-45e67beafd67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413146850 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3413146850
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1309959840
Short name T32
Test name
Test status
Simulation time 28975848 ps
CPU time 0.84 seconds
Started Jul 01 04:28:19 PM PDT 24
Finished Jul 01 04:28:26 PM PDT 24
Peak memory 204576 kb
Host smart-335f0152-ab6e-4459-80d8-9e64915c977e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309959840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1309959840
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2300507599
Short name T40
Test name
Test status
Simulation time 32939931 ps
CPU time 0.66 seconds
Started Jul 01 04:28:22 PM PDT 24
Finished Jul 01 04:28:27 PM PDT 24
Peak memory 204200 kb
Host smart-a0d1efd8-d473-4552-9fb5-dff726b41b82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300507599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2300507599
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1635073265
Short name T13
Test name
Test status
Simulation time 20856560 ps
CPU time 0.98 seconds
Started Jul 01 04:28:24 PM PDT 24
Finished Jul 01 04:28:30 PM PDT 24
Peak memory 204284 kb
Host smart-580646fa-eeb1-4546-959c-680e60838cb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635073265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.1635073265
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.928941463
Short name T77
Test name
Test status
Simulation time 73270948 ps
CPU time 1.8 seconds
Started Jul 01 04:28:32 PM PDT 24
Finished Jul 01 04:28:39 PM PDT 24
Peak memory 204420 kb
Host smart-c73ab546-1471-4348-8f8e-41586688d787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928941463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.928941463
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2131277343
Short name T60
Test name
Test status
Simulation time 248291411 ps
CPU time 2.14 seconds
Started Jul 01 04:28:17 PM PDT 24
Finished Jul 01 04:28:26 PM PDT 24
Peak memory 204372 kb
Host smart-50440d5e-f891-4112-a5e6-96e089616563
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131277343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2131277343
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3717842884
Short name T87
Test name
Test status
Simulation time 36224551 ps
CPU time 1.2 seconds
Started Jul 01 04:28:05 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 204452 kb
Host smart-241c9369-a9d4-43dd-924a-67612fe52026
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717842884 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3717842884
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3717289293
Short name T28
Test name
Test status
Simulation time 19996932 ps
CPU time 0.78 seconds
Started Jul 01 04:28:40 PM PDT 24
Finished Jul 01 04:28:47 PM PDT 24
Peak memory 204260 kb
Host smart-c403b751-8d11-4b23-8f3e-8ca17706e9d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717289293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3717289293
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1457263319
Short name T82
Test name
Test status
Simulation time 34106456 ps
CPU time 0.65 seconds
Started Jul 01 04:28:42 PM PDT 24
Finished Jul 01 04:28:52 PM PDT 24
Peak memory 204232 kb
Host smart-34100dde-ea31-4d02-aae0-24eb52160cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457263319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1457263319
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2943822168
Short name T115
Test name
Test status
Simulation time 98420762 ps
CPU time 1.31 seconds
Started Jul 01 04:28:19 PM PDT 24
Finished Jul 01 04:28:26 PM PDT 24
Peak memory 204320 kb
Host smart-de2ca2b4-f529-42f5-af89-72c04386dd5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943822168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.2943822168
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2569614866
Short name T128
Test name
Test status
Simulation time 49898036 ps
CPU time 1.19 seconds
Started Jul 01 04:28:26 PM PDT 24
Finished Jul 01 04:28:31 PM PDT 24
Peak memory 204444 kb
Host smart-196cc2a7-1dc6-4dd9-b42b-1442451ab8c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569614866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2569614866
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2009759632
Short name T38
Test name
Test status
Simulation time 1401863891 ps
CPU time 1.59 seconds
Started Jul 01 04:28:33 PM PDT 24
Finished Jul 01 04:28:40 PM PDT 24
Peak memory 204548 kb
Host smart-da26085b-b8c7-437e-89bc-a6c4c146396d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009759632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2009759632
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.730200960
Short name T42
Test name
Test status
Simulation time 160152480 ps
CPU time 1.07 seconds
Started Jul 01 04:28:37 PM PDT 24
Finished Jul 01 04:28:44 PM PDT 24
Peak memory 204336 kb
Host smart-aeb3d37f-e291-4c0a-afae-576831535a01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730200960 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.730200960
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3189496083
Short name T88
Test name
Test status
Simulation time 23950529 ps
CPU time 0.78 seconds
Started Jul 01 04:28:21 PM PDT 24
Finished Jul 01 04:28:27 PM PDT 24
Peak memory 204288 kb
Host smart-12adf6ba-2b71-4e73-ae5b-32ebbcc2dac2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189496083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3189496083
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.121606756
Short name T12
Test name
Test status
Simulation time 60568442 ps
CPU time 0.75 seconds
Started Jul 01 04:28:34 PM PDT 24
Finished Jul 01 04:28:41 PM PDT 24
Peak memory 204304 kb
Host smart-842712de-2306-4341-932c-d48860c46a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121606756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.121606756
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2578480937
Short name T90
Test name
Test status
Simulation time 83004658 ps
CPU time 1.6 seconds
Started Jul 01 04:28:25 PM PDT 24
Finished Jul 01 04:28:31 PM PDT 24
Peak memory 204408 kb
Host smart-479f89b3-d644-485a-8e98-fa9878c0bd21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578480937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.2578480937
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3244256120
Short name T135
Test name
Test status
Simulation time 261023153 ps
CPU time 0.79 seconds
Started Jul 01 04:28:37 PM PDT 24
Finished Jul 01 04:28:44 PM PDT 24
Peak memory 204340 kb
Host smart-6f1ea835-1b1f-4ba2-a633-91a8e1c9e294
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244256120 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.3244256120
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.26932632
Short name T143
Test name
Test status
Simulation time 51745934 ps
CPU time 0.79 seconds
Started Jul 01 04:28:24 PM PDT 24
Finished Jul 01 04:28:30 PM PDT 24
Peak memory 204484 kb
Host smart-8202f2bd-74dd-44db-ae9f-aae96b902d16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26932632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.26932632
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.2669662327
Short name T97
Test name
Test status
Simulation time 25795421 ps
CPU time 0.67 seconds
Started Jul 01 04:28:37 PM PDT 24
Finished Jul 01 04:28:43 PM PDT 24
Peak memory 204204 kb
Host smart-24e8543e-92dc-4d5a-8c0e-2f63a6c1ca93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669662327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.2669662327
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3600963637
Short name T104
Test name
Test status
Simulation time 94367792 ps
CPU time 1.19 seconds
Started Jul 01 04:28:35 PM PDT 24
Finished Jul 01 04:28:42 PM PDT 24
Peak memory 204384 kb
Host smart-114b2638-9982-4862-8d1c-635c9d3586c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600963637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.3600963637
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2453125838
Short name T153
Test name
Test status
Simulation time 504235843 ps
CPU time 2.08 seconds
Started Jul 01 04:28:46 PM PDT 24
Finished Jul 01 04:28:59 PM PDT 24
Peak memory 204508 kb
Host smart-4d502322-26ac-4682-acfd-619197f6b5d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453125838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2453125838
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.424184545
Short name T58
Test name
Test status
Simulation time 78370504 ps
CPU time 1.38 seconds
Started Jul 01 04:28:33 PM PDT 24
Finished Jul 01 04:28:40 PM PDT 24
Peak memory 204360 kb
Host smart-fa466c3b-b87f-431d-9128-282da340dfcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424184545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.424184545
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1689125326
Short name T23
Test name
Test status
Simulation time 33421595 ps
CPU time 0.93 seconds
Started Jul 01 04:28:40 PM PDT 24
Finished Jul 01 04:28:48 PM PDT 24
Peak memory 204432 kb
Host smart-94ef5a00-bedb-4da6-b63a-29eb0a33368d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689125326 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1689125326
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3433751404
Short name T91
Test name
Test status
Simulation time 801439669 ps
CPU time 2.14 seconds
Started Jul 01 04:28:34 PM PDT 24
Finished Jul 01 04:28:42 PM PDT 24
Peak memory 204232 kb
Host smart-620db3ba-0158-4e3a-9574-e0e0becc50c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433751404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3433751404
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.4002065978
Short name T129
Test name
Test status
Simulation time 18347600 ps
CPU time 0.69 seconds
Started Jul 01 04:28:36 PM PDT 24
Finished Jul 01 04:28:43 PM PDT 24
Peak memory 204184 kb
Host smart-decc62e0-022c-4545-afdf-077a84dcc9a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002065978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.4002065978
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2779899824
Short name T7
Test name
Test status
Simulation time 70520015 ps
CPU time 1.28 seconds
Started Jul 01 04:28:14 PM PDT 24
Finished Jul 01 04:28:23 PM PDT 24
Peak memory 204424 kb
Host smart-2484fff7-1928-4c30-86c8-af494069af32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779899824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.2779899824
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.936461679
Short name T92
Test name
Test status
Simulation time 103992429 ps
CPU time 2.52 seconds
Started Jul 01 04:28:29 PM PDT 24
Finished Jul 01 04:28:36 PM PDT 24
Peak memory 204696 kb
Host smart-a7b623c2-75f6-45e4-81fb-767672707b9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936461679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.936461679
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1780382951
Short name T39
Test name
Test status
Simulation time 80714286 ps
CPU time 2.21 seconds
Started Jul 01 04:28:23 PM PDT 24
Finished Jul 01 04:28:30 PM PDT 24
Peak memory 204432 kb
Host smart-b9bd942a-fe7a-4ac6-83b9-1f0e0556a86e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780382951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1780382951
Directory /workspace/9.i2c_tl_intg_err/latest
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