Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	357	1			T1	8		T6	1		T11	5
all_pins[1]	357	1			T1	8		T6	1		T11	5
all_pins[2]	357	1			T1	8		T6	1		T11	5
all_pins[3]	357	1			T1	8		T6	1		T11	5
all_pins[4]	357	1			T1	8		T6	1		T11	5
all_pins[5]	357	1			T1	8		T6	1		T11	5
all_pins[6]	357	1			T1	8		T6	1		T11	5
all_pins[7]	357	1			T1	8		T6	1		T11	5
all_pins[8]	357	1			T1	8		T6	1		T11	5
all_pins[9]	357	1			T1	8		T6	1		T11	5
all_pins[10]	357	1			T1	8		T6	1		T11	5
all_pins[11]	357	1			T1	8		T6	1		T11	5
all_pins[12]	357	1			T1	8		T6	1		T11	5
all_pins[13]	357	1			T1	8		T6	1		T11	5
all_pins[14]	357	1			T1	8		T6	1		T11	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4385	1			T1	89		T6	15		T11	62
values[0x1]	970	1			T1	31		T11	13		T8	28
transitions[0x0=>0x1]	725	1			T1	19		T11	12		T8	18
transitions[0x1=>0x0]	734	1			T1	20		T11	12		T8	18

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	288	1			T1	7		T6	1		T11	5
all_pins[0]	values[0x1]	69	1			T1	1		T8	3		T10	2
all_pins[0]	transitions[0x0=>0x1]	50	1			T1	1		T8	2		T10	2
all_pins[0]	transitions[0x1=>0x0]	46	1			T1	1		T9	3		T67	2
all_pins[1]	values[0x0]	292	1			T1	7		T6	1		T11	5
all_pins[1]	values[0x1]	65	1			T1	1		T8	1		T9	3
all_pins[1]	transitions[0x0=>0x1]	47	1			T1	1		T8	1		T9	2
all_pins[1]	transitions[0x1=>0x0]	31	1			T1	1		T8	1		T9	1
all_pins[2]	values[0x0]	308	1			T1	7		T6	1		T11	5
all_pins[2]	values[0x1]	49	1			T1	1		T8	1		T9	2
all_pins[2]	transitions[0x0=>0x1]	40	1			T1	1		T9	2		T67	1
all_pins[2]	transitions[0x1=>0x0]	58	1			T11	3		T8	2		T9	3
all_pins[3]	values[0x0]	290	1			T1	8		T6	1		T11	2
all_pins[3]	values[0x1]	67	1			T11	3		T8	3		T9	3
all_pins[3]	transitions[0x0=>0x1]	52	1			T11	3		T8	2		T9	2
all_pins[3]	transitions[0x1=>0x0]	59	1			T1	1		T10	3		T12	1
all_pins[4]	values[0x0]	283	1			T1	7		T6	1		T11	5
all_pins[4]	values[0x1]	74	1			T1	1		T8	1		T10	3
all_pins[4]	transitions[0x0=>0x1]	59	1			T10	3		T9	2		T68	1
all_pins[4]	transitions[0x1=>0x0]	61	1			T1	3		T8	3		T12	4
all_pins[5]	values[0x0]	281	1			T1	4		T6	1		T11	5
all_pins[5]	values[0x1]	76	1			T1	4		T8	4		T12	5
all_pins[5]	transitions[0x0=>0x1]	57	1			T1	3		T8	3		T12	4
all_pins[5]	transitions[0x1=>0x0]	29	1			T8	1		T67	2		T68	1
all_pins[6]	values[0x0]	309	1			T1	7		T6	1		T11	5
all_pins[6]	values[0x1]	48	1			T1	1		T8	2		T12	1
all_pins[6]	transitions[0x0=>0x1]	32	1			T8	2		T12	1		T67	1
all_pins[6]	transitions[0x1=>0x0]	64	1			T1	3		T11	4		T8	2
all_pins[7]	values[0x0]	277	1			T1	4		T6	1		T11	1
all_pins[7]	values[0x1]	80	1			T1	4		T11	4		T8	2
all_pins[7]	transitions[0x0=>0x1]	53	1			T1	1		T11	3		T8	2
all_pins[7]	transitions[0x1=>0x0]	47	1			T1	2		T10	1		T9	2
all_pins[8]	values[0x0]	283	1			T1	3		T6	1		T11	4
all_pins[8]	values[0x1]	74	1			T1	5		T11	1		T10	1
all_pins[8]	transitions[0x0=>0x1]	60	1			T1	4		T11	1		T10	1
all_pins[8]	transitions[0x1=>0x0]	41	1			T8	3		T10	1		T9	1
all_pins[9]	values[0x0]	302	1			T1	7		T6	1		T11	5
all_pins[9]	values[0x1]	55	1			T1	1		T8	3		T10	1
all_pins[9]	transitions[0x0=>0x1]	46	1			T1	1		T8	3		T10	1
all_pins[9]	transitions[0x1=>0x0]	43	1			T1	1		T10	1		T12	2
all_pins[10]	values[0x0]	305	1			T1	7		T6	1		T11	5
all_pins[10]	values[0x1]	52	1			T1	1		T10	1		T12	2
all_pins[10]	transitions[0x0=>0x1]	38	1			T1	1		T12	1		T68	1
all_pins[10]	transitions[0x1=>0x0]	52	1			T1	2		T11	1		T8	1
all_pins[11]	values[0x0]	291	1			T1	6		T6	1		T11	4
all_pins[11]	values[0x1]	66	1			T1	2		T11	1		T8	1
all_pins[11]	transitions[0x0=>0x1]	53	1			T1	1		T11	1		T10	2
all_pins[11]	transitions[0x1=>0x0]	36	1			T1	1		T11	2		T8	1
all_pins[12]	values[0x0]	308	1			T1	6		T6	1		T11	3
all_pins[12]	values[0x1]	49	1			T1	2		T11	2		T8	2
all_pins[12]	transitions[0x0=>0x1]	38	1			T1	1		T11	2		T10	1
all_pins[12]	transitions[0x1=>0x0]	52	1			T1	4		T8	2		T10	1
all_pins[13]	values[0x0]	294	1			T1	3		T6	1		T11	5
all_pins[13]	values[0x1]	63	1			T1	5		T8	4		T10	1
all_pins[13]	transitions[0x0=>0x1]	44	1			T1	3		T8	3		T12	2
all_pins[13]	transitions[0x1=>0x0]	64	1			T11	2		T10	5		T9	1
all_pins[14]	values[0x0]	274	1			T1	6		T6	1		T11	3
all_pins[14]	values[0x1]	83	1			T1	2		T11	2		T8	1
all_pins[14]	transitions[0x0=>0x1]	56	1			T1	1		T11	2		T10	4
all_pins[14]	transitions[0x1=>0x0]	51	1			T1	1		T8	2		T10	1