Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

170371

1

T1

1094

T8

29

T9

522

ack

15379

1

T1

29

T5

13

T8

3

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	664	1			T1	3		T9	4		T10	4
high	38103	1			T1	235		T5	1		T8	5
med	69013	1			T1	459		T5	3		T8	16
sml	77258	1			T1	415		T5	9		T8	11
all_zero	712	1			T1	11		T9	1		T10	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93030

1

T1

546

T5

6

T8

15

auto[1]

92720

1

T1

577

T5

7

T8

17

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127390

1

T1

733

T5

13

T8

18

auto[1]

58360

1

T1

390

T8

14

T9

195

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177640

1

T1

1116

T5

7

T8

30

auto[1]

8110

1

T1

7

T5

6

T8

2

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175264

1

T1

1096

T5

6

T8

30

auto[1]

10486

1

T1

27

T5

7

T8

2

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176284

1

T1

1111

T5

7

T8

31

auto[1]

9466

1

T1

12

T5

6

T8

1

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93030

1

T1

546

T5

6

T8

15

auto[1]

92720

1

T1

577

T5

7

T8

17

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127390

1

T1

733

T5

13

T8

18

auto[1]

58360

1

T1

390

T8

14

T9

195

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177640

1

T1

1116

T5

7

T8

30

auto[1]

8110

1

T1

7

T5

6

T8

2

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175264

1

T1

1096

T5

6

T8

30

auto[1]

10486

1

T1

27

T5

7

T8

2

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176284

1

T1

1111

T5

7

T8

31

auto[1]

9466

1

T1

12

T5

6

T8

1

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

2

1

T271

1

T120

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T272

1

T273

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T35

1

T274

1

T117

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

285

1

T1

1

T46

1

T142

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

166

1

T9

2

T142

3

T71

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

131

1

T46

1

T142

2

T140

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

559

1

T9

3

T46

7

T142

5

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

274

1

T1

1

T9

1

T46

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

276

1

T46

1

T142

1

T140

4

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

564

1

T9

2

T46

4

T142

5

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

301

1

T1

1

T46

3

T142

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

266

1

T1

1

T9

1

T46

4

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T275

1

T276

1

T101

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T50

1

T277

1

T278

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T49

1

T279

1

T272

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	54426	1			T1	337		T8	8		T9	173
write_address_byte	10486	1			T1	27		T5	7		T8	2
read_with_ack	2402	1			T1	2		T8	2		T9	25
read_with_nack	5708	1			T1	5		T5	6		T9	41
stop_byte	9466	1			T1	12		T5	6		T8	1
write_address_byte_nak	5192	1			T1	8		T9	18		T46	41
data_byte_nack	170371	1			T1	1094		T8	29		T9	522
stop_byte_nack	5686	1			T1	8		T8	1		T9	15
nakok_byte_nack	85131	1			T1	561		T8	14		T9	249
nakok_addr_byte_nack	2622	1			T1	2		T9	9		T46	15