Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 44481561 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 10525045 1 T1 50716 T2 412 T3 16



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 54260426 1 T1 417693 T2 1653 T3 21
values[0x0] 373314 1 T1 4749 T2 9 T3 10
values[0x1] 372866 1 T1 4736 T2 10 T3 10



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 31710270 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 23296336 1 T1 168712 T2 694 T3 17



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 223323 1 T1 2717 T3 1 T4 341
valid_sources[0x01] 210626 1 T1 1730 T4 399 T5 321
valid_sources[0x02] 192238 1 T1 58 T4 322 T5 304
valid_sources[0x03] 225832 1 T1 4025 T4 295 T5 308
valid_sources[0x04] 211140 1 T1 91 T4 309 T5 302
valid_sources[0x05] 198280 1 T1 481 T4 337 T5 305
valid_sources[0x06] 206709 1 T1 663 T4 319 T5 318
valid_sources[0x07] 190160 1 T1 21 T4 354 T5 307
valid_sources[0x08] 245111 1 T1 2833 T4 299 T5 311
valid_sources[0x09] 1005344 1 T1 4181 T4 346 T5 335
valid_sources[0x0a] 220839 1 T1 84 T4 309 T5 345
valid_sources[0x0b] 194465 1 T1 2286 T4 314 T5 310
valid_sources[0x0c] 217694 1 T1 1672 T4 303 T5 287
valid_sources[0x0d] 214025 1 T1 1710 T4 368 T5 330
valid_sources[0x0e] 215747 1 T1 631 T4 336 T5 319
valid_sources[0x0f] 204677 1 T1 505 T4 327 T5 315
valid_sources[0x10] 198105 1 T1 4082 T4 304 T5 323
valid_sources[0x11] 223829 1 T1 79 T4 313 T5 267
valid_sources[0x12] 328644 1 T1 1818 T3 2 T4 319
valid_sources[0x13] 215767 1 T1 1848 T4 318 T5 311
valid_sources[0x14] 204760 1 T1 4447 T4 338 T5 322
valid_sources[0x15] 197894 1 T1 30 T4 323 T5 348
valid_sources[0x16] 197054 1 T1 2869 T3 2 T4 336
valid_sources[0x17] 214292 1 T1 214 T4 395 T5 355
valid_sources[0x18] 198148 1 T1 944 T4 325 T5 354
valid_sources[0x19] 197645 1 T1 623 T3 3 T4 350
valid_sources[0x1a] 208166 1 T1 53 T4 294 T5 324
valid_sources[0x1b] 211412 1 T1 1597 T3 1 T4 292
valid_sources[0x1c] 200754 1 T1 1987 T4 313 T5 279
valid_sources[0x1d] 201916 1 T1 1425 T4 311 T5 337
valid_sources[0x1e] 219036 1 T1 53 T4 312 T5 343
valid_sources[0x1f] 197895 1 T1 39 T4 313 T5 305
valid_sources[0x20] 225642 1 T1 2031 T4 351 T5 333
valid_sources[0x21] 214485 1 T1 827 T4 344 T5 323
valid_sources[0x22] 210351 1 T1 2307 T3 1 T4 359
valid_sources[0x23] 207414 1 T1 1094 T4 315 T5 298
valid_sources[0x24] 222155 1 T1 1123 T4 316 T5 329
valid_sources[0x25] 203447 1 T1 250 T4 291 T5 312
valid_sources[0x26] 188796 1 T1 27 T4 350 T5 347
valid_sources[0x27] 208260 1 T1 650 T4 351 T5 301
valid_sources[0x28] 203879 1 T1 81 T4 349 T5 326
valid_sources[0x29] 198951 1 T1 178 T4 337 T5 312
valid_sources[0x2a] 200835 1 T1 1863 T4 273 T5 336
valid_sources[0x2b] 211750 1 T1 2715 T4 333 T5 313
valid_sources[0x2c] 208410 1 T1 4069 T4 379 T5 320
valid_sources[0x2d] 196317 1 T1 3450 T4 271 T5 292
valid_sources[0x2e] 216180 1 T1 6615 T4 348 T5 323
valid_sources[0x2f] 191637 1 T1 464 T4 374 T5 308
valid_sources[0x30] 198866 1 T1 50 T4 363 T5 311
valid_sources[0x31] 208855 1 T1 1836 T4 339 T5 312
valid_sources[0x32] 185392 1 T1 658 T4 313 T5 319
valid_sources[0x33] 213592 1 T1 40 T3 1 T4 337
valid_sources[0x34] 197985 1 T1 214 T4 336 T5 315
valid_sources[0x35] 196478 1 T1 781 T3 1 T4 333
valid_sources[0x36] 202272 1 T1 3628 T4 328 T5 304
valid_sources[0x37] 203897 1 T1 3737 T4 324 T5 313
valid_sources[0x38] 194886 1 T1 205 T4 353 T5 289
valid_sources[0x39] 202410 1 T1 674 T4 336 T5 328
valid_sources[0x3a] 195974 1 T1 1530 T4 323 T5 337
valid_sources[0x3b] 198381 1 T1 34 T3 1 T4 313
valid_sources[0x3c] 218668 1 T1 141 T4 323 T5 336
valid_sources[0x3d] 258382 1 T1 1777 T4 324 T5 346
valid_sources[0x3e] 219060 1 T1 484 T4 365 T5 285
valid_sources[0x3f] 206897 1 T1 906 T4 294 T5 314
valid_sources[0x40] 189554 1 T1 2154 T4 329 T5 359
valid_sources[0x41] 234676 1 T1 4616 T4 268 T5 326
valid_sources[0x42] 205071 1 T1 58 T4 371 T5 326
valid_sources[0x43] 204210 1 T1 97 T4 348 T5 322
valid_sources[0x44] 201711 1 T1 1662 T3 1 T4 370
valid_sources[0x45] 212002 1 T1 958 T4 291 T5 310
valid_sources[0x46] 191424 1 T1 1952 T4 318 T5 301
valid_sources[0x47] 200376 1 T1 36 T4 334 T5 307
valid_sources[0x48] 232504 1 T1 2112 T4 312 T5 299
valid_sources[0x49] 198497 1 T1 3099 T3 2 T4 339
valid_sources[0x4a] 218544 1 T1 354 T4 340 T5 319
valid_sources[0x4b] 202765 1 T1 167 T4 364 T5 316
valid_sources[0x4c] 204774 1 T1 943 T4 275 T5 326
valid_sources[0x4d] 208939 1 T1 3229 T4 324 T5 301
valid_sources[0x4e] 202084 1 T1 49 T4 336 T5 361
valid_sources[0x4f] 208977 1 T1 787 T4 358 T5 322
valid_sources[0x50] 213169 1 T1 1400 T4 303 T5 287
valid_sources[0x51] 208568 1 T1 1100 T4 329 T5 352
valid_sources[0x52] 197778 1 T1 4045 T4 349 T5 314
valid_sources[0x53] 209771 1 T1 14 T3 1 T4 342
valid_sources[0x54] 198979 1 T1 1072 T4 309 T5 303
valid_sources[0x55] 193518 1 T1 2848 T4 364 T5 347
valid_sources[0x56] 216841 1 T1 921 T4 349 T5 304
valid_sources[0x57] 198933 1 T1 480 T4 350 T5 330
valid_sources[0x58] 192230 1 T1 3433 T4 287 T5 306
valid_sources[0x59] 243977 1 T1 3866 T4 347 T5 327
valid_sources[0x5a] 198152 1 T1 5810 T4 388 T5 302
valid_sources[0x5b] 196511 1 T1 1400 T4 291 T5 324
valid_sources[0x5c] 198262 1 T1 3452 T4 294 T5 356
valid_sources[0x5d] 208670 1 T1 2570 T4 378 T5 305
valid_sources[0x5e] 210587 1 T1 2609 T4 340 T5 290
valid_sources[0x5f] 199244 1 T1 47 T4 342 T5 301
valid_sources[0x60] 213473 1 T1 43 T4 370 T5 299
valid_sources[0x61] 227803 1 T1 327 T4 317 T5 338
valid_sources[0x62] 215068 1 T1 2232 T3 1 T4 336
valid_sources[0x63] 226634 1 T1 76 T4 336 T5 331
valid_sources[0x64] 195509 1 T1 48 T4 323 T5 300
valid_sources[0x65] 187687 1 T1 2082 T4 336 T5 307
valid_sources[0x66] 192997 1 T1 1677 T4 323 T5 364
valid_sources[0x67] 198507 1 T1 2126 T4 335 T5 324
valid_sources[0x68] 203668 1 T1 1489 T4 329 T5 305
valid_sources[0x69] 193262 1 T1 812 T3 1 T4 323
valid_sources[0x6a] 205307 1 T1 570 T4 292 T5 313
valid_sources[0x6b] 184643 1 T1 79 T4 257 T5 309
valid_sources[0x6c] 230279 1 T1 3019 T3 1 T4 350
valid_sources[0x6d] 193357 1 T1 1548 T4 348 T5 318
valid_sources[0x6e] 194298 1 T1 2864 T4 298 T5 306
valid_sources[0x6f] 390135 1 T1 68 T4 334 T5 324
valid_sources[0x70] 203644 1 T1 79 T4 360 T5 289
valid_sources[0x71] 203208 1 T1 4518 T4 375 T5 273
valid_sources[0x72] 190000 1 T1 201 T4 302 T5 318
valid_sources[0x73] 227955 1 T1 48 T4 329 T5 355
valid_sources[0x74] 207690 1 T1 1249 T4 345 T5 300
valid_sources[0x75] 195567 1 T1 1259 T4 298 T5 300
valid_sources[0x76] 192233 1 T1 3617 T4 328 T5 338
valid_sources[0x77] 212304 1 T1 1237 T3 1 T4 311
valid_sources[0x78] 196258 1 T1 38 T4 358 T5 296
valid_sources[0x79] 195025 1 T1 1983 T4 346 T5 310
valid_sources[0x7a] 205688 1 T1 3472 T3 1 T4 340
valid_sources[0x7b] 197984 1 T1 461 T4 316 T5 296
valid_sources[0x7c] 184890 1 T1 86 T4 285 T5 332
valid_sources[0x7d] 199266 1 T1 6705 T4 338 T5 326
valid_sources[0x7e] 190377 1 T1 1951 T4 343 T5 311
valid_sources[0x7f] 214966 1 T1 58 T4 355 T5 321
valid_sources[0x80] 209086 1 T1 3584 T4 328 T5 320



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 10157426 1 T1 47334 T2 398 T3 11
values[0x0] all_enables biggest_size 211452 1 T1 2190 T2 8 T3 4
values[0x1] all_enables biggest_size 156167 1 T1 1192 T2 6 T3 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%