Unified Coverage Report :: Module :: i2c_fifos

Module : i2c_fifos

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	100.00				100.00	40.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos	80.00	100.00				100.00	40.00

---

Module Instance : tb.dut.i2c_core.u_fifos

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	100.00				100.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.43	99.86	85.73			98.65	93.48

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.38	97.74	78.46			93.33	100.00	i2c_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_acq_fifo_sram_adapter	96.17	100.00	86.16			98.51	100.00
u_fmt_fifo_sram_adapter	96.32	100.00	86.79			98.51	100.00
u_ram_1p	99.02	97.06				100.00	100.00
u_ram_arbiter	91.58	100.00	85.09			100.00	81.25
u_rx_fifo_sram_adapter	96.32	100.00	86.79			98.51	100.00
u_tx_fifo_sram_adapter	95.54	100.00	83.65			98.51	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : i2c_fifos

	Line No.	Total	Covered	Percent
TOTAL		31	31	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
ALWAYS	270	3	3	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	304	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
114	1	1
115	1	1
147	1	1
148	1	1
150	1	1
182	1	1
183	1	1
185	1	1
217	1	1
218	1	1
220	1	1
254	1	1
255	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
262	1	1
263	1	1
264	1	1
265	1	1
270	1	1
271	1	1
273	1	1
276	1	1
277	1	1
278	1	1
279	1	1
304	1	1

---

Branch Coverage for Module : i2c_fifos

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	270	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	270	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fifos

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	2	40.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	2	40.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AcqWriteStableBeforeHandshake_A	348816115	0	0	0
FmtWriteStableBeforeHandshake_A	348816115	0	0	0
RamDepthSuffices_A	1481	1481	0	0
RamWidthSuffices_A	1481	1481	0	0
TxWriteStableBeforeHandshake_A	348816115	0	0	0

AcqWriteStableBeforeHandshake_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348816115	0	0	0

FmtWriteStableBeforeHandshake_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348816115	0	0	0

RamDepthSuffices_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

RamWidthSuffices_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TxWriteStableBeforeHandshake_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348816115	0	0	0