Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	349543852	0	0	0
ctrl_rd_A	349543852	2830	0	0
host_fifo_config_rd_A	349543852	6474	0	0
host_nack_handler_timeout_rd_A	349543852	1596	0	0
host_timeout_ctrl_rd_A	349543852	1589	0	0
intr_enable_rd_A	349543852	4359	0	0
ovrd_rd_A	349543852	2355	0	0
target_fifo_config_rd_A	349543852	1606	0	0
target_id_rd_A	349543852	2018	0	0
target_timeout_ctrl_rd_A	349543852	1731	0	0
timeout_ctrl_rd_A	349543852	1887	0	0
timing0_rd_A	349543852	1690	0	0
timing1_rd_A	349543852	1728	0	0
timing2_rd_A	349543852	1753	0	0
timing3_rd_A	349543852	1693	0	0
timing4_rd_A	349543852	1798	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	2830	0	0
T88	2133	26	0	0
T89	6320	84	0	0
T90	14129	172	0	0
T91	2734	20	0	0
T92	2870	6	0	0
T93	2012	33	0	0
T94	7274	195	0	0
T95	12737	287	0	0
T96	5342	40	0	0
T97	5580	92	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	6474	0	0
T35	107458	0	0	0
T49	0	123	0	0
T65	1433	0	0	0
T98	332929	107	0	0
T99	0	373	0	0
T100	0	139	0	0
T101	0	168	0	0
T102	0	302	0	0
T103	0	164	0	0
T104	0	228	0	0
T105	0	66	0	0
T106	0	227	0	0
T107	249968	0	0	0
T108	25568	0	0	0
T109	20281	0	0	0
T110	45059	0	0	0
T111	13784	0	0	0
T112	410567	0	0	0
T113	284993	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	1596	0	0
T89	6320	15	0	0
T90	14129	62	0	0
T91	2734	2	0	0
T92	2870	5	0	0
T93	2012	9	0	0
T94	7274	59	0	0
T95	12737	101	0	0
T96	5342	21	0	0
T97	5580	8	0	0
T114	4094	16	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	1589	0	0
T88	2133	3	0	0
T89	6320	62	0	0
T90	14129	40	0	0
T91	2734	13	0	0
T92	2870	14	0	0
T93	2012	10	0	0
T94	7274	34	0	0
T95	12737	69	0	0
T96	5342	65	0	0
T97	5580	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	4359	0	0
T49	910756	44	0	0
T67	0	36	0	0
T73	12272	0	0	0
T101	0	9	0	0
T102	0	9	0	0
T115	0	11	0	0
T116	0	22	0	0
T117	0	25	0	0
T118	0	17	0	0
T119	0	47	0	0
T120	0	39	0	0
T121	1158	0	0	0
T122	85371	0	0	0
T123	12914	0	0	0
T124	159379	0	0	0
T125	119517	0	0	0
T126	234760	0	0	0
T127	11104	0	0	0
T128	46238	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	2355	0	0
T11	96748	0	0	0
T18	761862	0	0	0
T24	115543	0	0	0
T33	166105	0	0	0
T82	2141	9	0	0
T83	27672	0	0	0
T84	5723	0	0	0
T129	0	17	0	0
T130	0	38	0	0
T131	0	59	0	0
T132	0	35	0	0
T133	0	55	0	0
T134	0	68	0	0
T135	0	49	0	0
T136	0	67	0	0
T137	0	52	0	0
T138	59471	0	0	0
T139	44095	0	0	0
T140	68900	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	1606	0	0
T88	2133	4	0	0
T89	6320	50	0	0
T90	14129	67	0	0
T91	2734	6	0	0
T92	2870	14	0	0
T93	2012	12	0	0
T94	7274	67	0	0
T95	12737	105	0	0
T96	5342	35	0	0
T97	5580	40	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	2018	0	0
T88	2133	16	0	0
T89	6320	18	0	0
T90	14129	90	0	0
T91	2734	8	0	0
T92	2870	3	0	0
T93	2012	12	0	0
T94	7274	75	0	0
T95	12737	160	0	0
T96	5342	35	0	0
T97	5580	27	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	1731	0	0
T88	2133	3	0	0
T89	6320	56	0	0
T90	14129	53	0	0
T92	2870	5	0	0
T93	2012	6	0	0
T94	7274	41	0	0
T95	12737	122	0	0
T96	5342	56	0	0
T97	5580	62	0	0
T114	4094	29	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	1887	0	0
T88	2133	8	0	0
T89	6320	11	0	0
T90	14129	138	0	0
T91	2734	1	0	0
T92	2870	17	0	0
T93	2012	10	0	0
T94	7274	74	0	0
T95	12737	100	0	0
T96	5342	32	0	0
T97	5580	44	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	1690	0	0
T88	2133	8	0	0
T89	6320	41	0	0
T90	14129	49	0	0
T91	2734	1	0	0
T92	2870	3	0	0
T93	2012	19	0	0
T94	7274	40	0	0
T95	12737	101	0	0
T96	5342	44	0	0
T97	5580	38	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	1728	0	0
T88	2133	1	0	0
T89	6320	49	0	0
T90	14129	73	0	0
T91	2734	1	0	0
T92	2870	12	0	0
T93	2012	6	0	0
T94	7274	47	0	0
T95	12737	117	0	0
T96	5342	51	0	0
T97	5580	44	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	1753	0	0
T88	2133	13	0	0
T89	6320	56	0	0
T90	14129	45	0	0
T91	2734	17	0	0
T92	2870	30	0	0
T93	2012	6	0	0
T94	7274	42	0	0
T95	12737	97	0	0
T96	5342	22	0	0
T97	5580	60	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	1693	0	0
T88	2133	7	0	0
T89	6320	36	0	0
T90	14129	64	0	0
T91	2734	2	0	0
T92	2870	5	0	0
T93	2012	4	0	0
T94	7274	15	0	0
T95	12737	91	0	0
T96	5342	67	0	0
T97	5580	37	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349543852	1798	0	0
T88	2133	7	0	0
T89	6320	55	0	0
T90	14129	68	0	0
T91	2734	10	0	0
T92	2870	11	0	0
T93	2012	11	0	0
T94	7274	63	0	0
T95	12737	110	0	0
T96	5342	45	0	0
T97	5580	41	0	0