Module Definition
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Module : i2c_target_fsm
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.11 86.76 74.17 68.87 75.76 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i2c_core.u_i2c_target_fsm 81.11 86.76 74.17 68.87 75.76 100.00



Module Instance : tb.dut.i2c_core.u_i2c_target_fsm

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.11 86.76 74.17 68.87 75.76 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.11 86.76 74.17 68.87 75.76 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c_target_fsm
Line No.TotalCoveredPercent
TOTAL35530886.76
ALWAYS1308787.50
ALWAYS14433100.00
ALWAYS15466100.00
ALWAYS16555100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17811100.00
ALWAYS18233100.00
ALWAYS19133100.00
ALWAYS20077100.00
CONT_ASSIGN21211100.00
ALWAYS21699100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23311100.00
CONT_ASSIGN23511100.00
ALWAYS23977100.00
ALWAYS25055100.00
CONT_ASSIGN26711100.00
CONT_ASSIGN27011100.00
CONT_ASSIGN27111100.00
ALWAYS30244100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32711100.00
ALWAYS33114812483.78
CONT_ASSIGN64611100.00
CONT_ASSIGN64711100.00
CONT_ASSIGN65111100.00
CONT_ASSIGN66511100.00
CONT_ASSIGN67011100.00
ALWAYS6741199781.51
ALWAYS100733100.00
ALWAYS101633100.00
CONT_ASSIGN102311100.00
CONT_ASSIGN102411100.00
CONT_ASSIGN102711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
130 1 1
131 1 1
132 1 1
133 1 1
134 1 1
135 0 1
138 1 1
139 1 1
MISSING_ELSE
144 1 1
145 1 1
147 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
MISSING_ELSE
165 1 1
166 1 1
167 1 1
169 1 1
171 1 1
175 1 1
176 1 1
177 1 1
178 1 1
182 1 1
183 1 1
185 1 1
191 1 1
192 1 1
194 1 1
200 1 1
201 1 1
202 1 1
203 1 1
205 1 1
206 1 1
207 1 1
212 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 1 1
223 2 2
224 1 1
226 1 1
231 1 1
233 1 1
235 1 1
239 1 1
240 1 1
241 1 1
242 1 1
243 1 1
244 2 2
MISSING_ELSE
MISSING_ELSE
250 1 1
251 1 1
252 1 1
253 2 2
MISSING_ELSE
MISSING_ELSE
267 1 1
270 1 1
271 1 1
302 1 1
303 1 1
304 1 1
305 1 1
MISSING_ELSE
319 1 1
323 1 1
327 1 1
331 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
342 1 1
343 1 1
344 1 1
345 1 1
346 1 1
347 1 1
348 1 1
349 1 1
350 1 1
352 1 1
357 1 1
358 1 1
359 1 1
360 1 1
361 1 1
362 1 1
371 1 1
372 1 1
373 1 1
377 1 1
378 1 1
380 1 1
381 1 1
382 1 1
383 1 1
MISSING_ELSE
MISSING_ELSE
389 1 1
391 1 1
394 0 1
MISSING_ELSE
399 1 1
400 1 1
401 1 1
405 1 1
406 1 1
407 1 1
411 1 1
412 1 1
413 1 1
416 1 1
417 1 1
421 1 1
423 1 1
424 1 1
MISSING_ELSE
427 1 1
428 1 1
430 1 1
==> MISSING_ELSE
436 1 1
440 1 1
441 1 1
442 1 1
446 1 1
449 1 1
450 1 1
454 1 1
457 1 1
458 1 1
462 1 1
465 1 1
466 1 1
468 1 1
MISSING_ELSE
473 1 1
474 1 1
475 1 1
479 1 1
483 1 1
484 1 1
487 0 1
MISSING_ELSE
492 1 1
493 1 1
494 1 1
498 1 1
499 1 1
500 1 1
504 1 1
505 1 1
506 1 1
508 1 1
509 1 1
510 1 1
511 1 1
==> MISSING_ELSE
517 0 1
518 0 1
519 0 1
521 0 1
522 0 1
526 0 1
527 0 1
==> MISSING_ELSE
533 0 1
534 0 1
535 0 1
536 0 1
541 1 1
542 1 1
543 1 1
545 1 1
546 0 1
550 0 1
551 0 1
552 1 1
553 1 1
554 1 1
555 1 1
557 1 1
MISSING_ELSE
563 1 1
564 1 1
565 1 1
567 1 1
571 0 1
MISSING_ELSE
576 1 1
577 1 1
578 1 1
579 1 1
583 1 1
584 1 1
585 1 1
586 1 1
589 1 1
590 0 1
591 0 1
592 0 1
MISSING_ELSE
598 1 1
599 1 1
600 1 1
601 1 1
623 1 1
624 1 1
625 1 1
630 1 1
631 1 1
632 0 1
634 1 1
636 1 1
637 1 1
638 1 1
639 1 1
640 0 1
641 0 1
642 0 1
MISSING_ELSE
646 1 1
647 1 1
651 1 1
665 1 1
670 1 1
674 1 1
675 1 1
676 1 1
677 1 1
678 1 1
680 1 1
692 1 1
693 1 1
694 1 1
MISSING_ELSE
701 1 1
702 1 1
703 1 1
705 1 1
706 1 1
709 1 1
MISSING_ELSE
715 1 1
717 0 1
718 1 1
719 1 1
721 1 1
723 0 1
730 0 1
731 0 1
734 0 1
738 0 1
==> MISSING_ELSE
745 2 2
MISSING_ELSE
749 1 1
750 1 1
751 1 1
752 1 1
MISSING_ELSE
757 1 1
763 1 1
769 0 1
770 1 1
776 1 1
777 1 1
779 1 1
782 1 1
==> MISSING_ELSE
788 1 1
789 1 1
791 1 1
796 2 2
MISSING_ELSE
800 1 1
801 1 1
802 1 1
803 1 1
MISSING_ELSE
808 1 1
809 1 1
810 1 1
812 1 1
813 1 1
814 1 1
==> MISSING_ELSE
820 1 1
821 1 1
MISSING_ELSE
827 1 1
829 1 1
830 1 1
833 1 1
MISSING_ELSE
841 1 1
845 1 1
846 1 1
847 1 1
848 1 1
MISSING_ELSE
853 1 1
855 0 1
856 1 1
857 1 1
858 0 1
859 1 1
863 1 1
865 1 1
==> MISSING_ELSE
871 2 2
MISSING_ELSE
875 1 1
876 1 1
877 1 1
878 1 1
MISSING_ELSE
883 1 1
884 1 1
==> MISSING_ELSE
892 0 1
893 0 1
894 0 1
895 0 1
896 0 1
897 0 1
==> MISSING_ELSE
903 0 1
904 0 1
==> MISSING_ELSE
912 1 1
913 0 1
914 1 1
920 1 1
MISSING_ELSE
926 1 1
927 1 1
928 0 1
929 1 1
936 1 1
937 1 1
938 1 1
941 1 1
MISSING_ELSE
946 1 1
947 1 1
MISSING_ELSE
958 1 1
959 0 1
960 1 1
961 1 1
962 1 1
963 1 1
MISSING_ELSE
969 1 1
970 1 1
MISSING_ELSE
986 1 1
995 0 1
996 1 1
997 1 1
998 1 1
999 1 1
1000 1 1
1001 0 1
MISSING_ELSE
1007 1 1
1008 1 1
1010 1 1
1016 1 1
1017 1 1
1019 1 1
1023 1 1
1024 1 1
1027 1 1


Cond Coverage for Module : i2c_target_fsm
TotalCoveredPercent
Conditions1208974.17
Logical1208974.17
Non-Logical00
Event00

 LINE       158
 EXPRESSION (start_detect_i && target_idle_o)
             -------1------    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T6
11CoveredT1,T2,T4

 LINE       167
 EXPRESSION (auto_ack_load_i && ack_ctrl_stretching)
             -------1-------    ---------2---------
-1--2-StatusTests
01CoveredT11,T12,T13
10Not Covered
11CoveredT11,T12,T13

 LINE       175
 EXPRESSION (((!ack_ctrl_mode_i)) || (auto_ack_cnt_q > '0))
             ----------1---------    ----------2----------
-1--2-StatusTests
00CoveredT11,T12,T13
01CoveredT11,T12,T13
10CoveredT1,T2,T3

 LINE       212
 EXPRESSION (bit_idx == 4'd8)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       220
 EXPRESSION (scl_i_q && ((!scl_i)))
             ---1---    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       223
 EXPRESSION (input_byte_clr || bit_ack)
             -------1------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT2,T4,T6

 LINE       231
 EXPRESSION (((input_byte[7:1] & target_mask0_i) == target_address0_i) && (target_mask0_i != '0))
             ----------------------------1----------------------------    -----------2----------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT1,T2,T3
11CoveredT2,T4,T6

 LINE       231
 SUB-EXPRESSION ((input_byte[7:1] & target_mask0_i) == target_address0_i)
                ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (target_mask0_i != '0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

 LINE       233
 EXPRESSION (((input_byte[7:1] & target_mask1_i) == target_address1_i) && (target_mask1_i != '0))
             ----------------------------1----------------------------    -----------2----------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT1,T2,T3
11CoveredT2,T4,T6

 LINE       233
 SUB-EXPRESSION ((input_byte[7:1] & target_mask1_i) == target_address1_i)
                ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       233
 SUB-EXPRESSION (target_mask1_i != '0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

 LINE       235
 EXPRESSION (address0_match || address1_match)
             -------1------    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T6
10CoveredT2,T4,T6

 LINE       243
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       252
 EXPRESSION (((!scl_i_q)) && scl_i)
             ------1-----    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       304
 EXPRESSION (bit_ack && address_match)
             ---1---    ------2------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT1,T2,T4
11CoveredT2,T4,T6

 LINE       323
 EXPRESSION (target_enable_i & xfer_for_us_q & rw_bit_q & stop_detect_i & ((!expect_stop)))
             -------1-------   ------2------   ----3---   ------4------   --------5-------
-1--2--3--4--5-StatusTests
01111Not Covered
10111CoveredT14,T15
11011CoveredT2,T4,T6
11101CoveredT4,T6,T16
11110CoveredT4,T6,T16
11111CoveredT14,T15

 LINE       327
 EXPRESSION (((!nack_transaction_q)) && nack_transaction_d)
             -----------1-----------    ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       416
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT2,T4,T6

 LINE       508
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT2,T4,T6

 LINE       589
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------
-1--2-StatusTests
00CoveredT2,T17,T18
01Not Covered
10Not Covered

 LINE       589
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------
-1--2-StatusTests
01CoveredT11,T12,T13
10Not Covered
11Not Covered

 LINE       623
 EXPRESSION (target_enable_i && (stop_detect_i || bus_timeout_i))
             -------1-------    ----------------2---------------
-1--2-StatusTests
01CoveredT1,T5,T8
10CoveredT2,T4,T6
11CoveredT2,T4,T6

 LINE       623
 SUB-EXPRESSION (stop_detect_i || bus_timeout_i)
                 ------1------    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T4

 LINE       625
 EXPRESSION (bus_timeout_i && rw_bit_q)
             ------1------    ----2---
-1--2-StatusTests
01CoveredT4,T6,T16
10Not Covered
11Not Covered

 LINE       631
 EXPRESSION (nack_transaction_q || bus_timeout_i)
             ---------1--------    ------2------
-1--2-StatusTests
00CoveredT2,T4,T6
01Not Covered
10Not Covered

 LINE       636
 EXPRESSION (target_enable_i && start_detect_i)
             -------1-------    -------2------
-1--2-StatusTests
01CoveredT1,T5,T8
10CoveredT2,T4,T6
11CoveredT2,T4,T6

 LINE       646
 EXPRESSION (((!acq_fifo_plenty_space)) || ((!can_auto_ack)))
             -------------1------------    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT2,T17,T18

 LINE       651
 EXPRESSION (nack_timeout_en_i && (stretch_active_cnt >= nack_timeout_i))
             --------1--------    -------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       665
 EXPRESSION (((!tx_fifo_rvalid_i)) || unhandled_tx_stretch_event_i || (acq_fifo_depth_i > 9'(1'b1)))
             ----------1----------    --------------2-------------    --------------3--------------
-1--2--3-StatusTests
000CoveredT4,T6,T16
001CoveredT4,T6,T16
010CoveredT19,T20,T21
100CoveredT1,T2,T3

 LINE       718
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT2,T4,T6

 LINE       757
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT2,T4,T6

 LINE       808
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT4,T6,T16

 LINE       856
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT2,T4,T6

 LINE       883
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT2,T4,T6

 LINE       903
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       920
 EXPRESSION (rw_bit_q ? StretchTx : AcquireByte)
             ----1---
-1-StatusTests
0CoveredT2,T17,T18
1Not Covered

 LINE       946
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT4,T6,T16
1CoveredT4,T6,T16

 LINE       958
 EXPRESSION (nack_timeout || (sw_nack_i && ((!can_auto_ack))))
             ------1-----    ----------------2---------------
-1--2-StatusTests
00CoveredT2,T17,T18
01Not Covered
10Not Covered

 LINE       958
 SUB-EXPRESSION (sw_nack_i && ((!can_auto_ack)))
                 ----1----    --------2--------
-1--2-StatusTests
01CoveredT11,T12,T13
10Not Covered
11Not Covered

 LINE       969
 EXPRESSION (tcount_q == 16'b1)
            ---------1---------
-1-StatusTests
0CoveredT2,T17,T18
1CoveredT2,T17,T18

 LINE       986
 EXPRESSION (((!target_idle)) && ((!target_enable_i)))
             --------1-------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T6
11Not Covered

 LINE       996
 EXPRESSION (target_enable_i && start_detect_i)
             -------1-------    -------2------
-1--2-StatusTests
01CoveredT1,T5,T8
10CoveredT2,T4,T6
11CoveredT2,T4,T6

 LINE       998
 EXPRESSION (stop_detect_i || bus_timeout_i)
             ------1------    ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T4

FSM Coverage for Module : i2c_target_fsm
Summary for FSM :: state_q
TotalCoveredPercent
States 26 24 92.31 (Not included in score)
Transitions 106 73 68.87
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AcquireAckHold 876 Covered T2,T4,T6
AcquireAckPulse 871 Covered T2,T4,T6
AcquireAckSetup 865 Covered T2,T4,T6
AcquireAckWait 846 Covered T2,T4,T6
AcquireByte 782 Covered T2,T4,T6
AcquireStart 997 Covered T2,T4,T6
AddrAckHold 750 Covered T2,T4,T6
AddrAckPulse 745 Covered T2,T4,T6
AddrAckSetup 721 Covered T2,T4,T6
AddrAckWait 703 Covered T2,T4,T6
AddrRead 693 Covered T2,T4,T6
Idle 995 Covered T1,T2,T3
StretchAcqFull 863 Covered T2,T17,T18
StretchAcqSetup 961 Covered T2,T17,T18
StretchAddr 776 Covered T2,T17,T18
StretchAddrAck 734 Not Covered
StretchAddrAckSetup 895 Not Covered
StretchTx 789 Covered T4,T6,T16
StretchTxSetup 936 Covered T4,T6,T16
TransmitAck 810 Covered T4,T6,T16
TransmitAckPulse 821 Covered T4,T6,T16
TransmitHold 801 Covered T4,T6,T16
TransmitPulse 796 Covered T4,T6,T16
TransmitSetup 791 Covered T4,T6,T16
TransmitWait 779 Covered T4,T6,T16
WaitForStop 709 Covered T4,T6,T16


transitionsLine No.CoveredTests
AcquireAckHold->AcquireByte 884 Covered T2,T4,T6
AcquireAckHold->AcquireStart 997 Covered T14,T15
AcquireAckHold->Idle 995 Covered T14,T15
AcquireAckHold->WaitForStop 1001 Not Covered
AcquireAckPulse->AcquireAckHold 876 Covered T2,T4,T6
AcquireAckPulse->AcquireStart 997 Covered T14,T15
AcquireAckPulse->Idle 995 Covered T14,T15
AcquireAckPulse->WaitForStop 1001 Not Covered
AcquireAckSetup->AcquireAckPulse 871 Covered T2,T4,T6
AcquireAckSetup->AcquireStart 997 Covered T14,T15
AcquireAckSetup->Idle 995 Covered T14,T15
AcquireAckSetup->WaitForStop 1001 Not Covered
AcquireAckWait->AcquireAckSetup 865 Covered T2,T4,T6
AcquireAckWait->AcquireStart 997 Covered T14,T15
AcquireAckWait->Idle 995 Covered T14,T15
AcquireAckWait->StretchAcqFull 863 Covered T2,T17,T18
AcquireAckWait->WaitForStop 855 Not Covered
AcquireByte->AcquireAckWait 846 Covered T2,T4,T6
AcquireByte->AcquireStart 997 Covered T2,T4,T6
AcquireByte->Idle 995 Covered T2,T4,T6
AcquireByte->WaitForStop 1001 Not Covered
AcquireStart->AddrRead 693 Covered T2,T4,T6
AcquireStart->Idle 995 Covered T14,T15
AcquireStart->WaitForStop 1001 Not Covered
AddrAckHold->AcquireByte 782 Covered T2,T4,T6
AddrAckHold->AcquireStart 997 Covered T14,T15
AddrAckHold->Idle 995 Covered T14,T15
AddrAckHold->StretchAddr 776 Covered T2,T17,T18
AddrAckHold->TransmitWait 779 Covered T4,T6,T16
AddrAckHold->WaitForStop 769 Not Covered
AddrAckPulse->AcquireStart 997 Covered T14,T15
AddrAckPulse->AddrAckHold 750 Covered T2,T4,T6
AddrAckPulse->Idle 995 Covered T14,T15
AddrAckPulse->WaitForStop 1001 Not Covered
AddrAckSetup->AcquireStart 997 Covered T14,T15
AddrAckSetup->AddrAckPulse 745 Covered T2,T4,T6
AddrAckSetup->Idle 995 Covered T14,T15
AddrAckSetup->WaitForStop 1001 Not Covered
AddrAckWait->AcquireStart 997 Covered T14,T15
AddrAckWait->AddrAckSetup 721 Covered T2,T4,T6
AddrAckWait->Idle 995 Covered T14,T15
AddrAckWait->StretchAddrAck 734 Not Covered
AddrAckWait->WaitForStop 717 Not Covered
AddrRead->AcquireStart 997 Covered T14,T15
AddrRead->AddrAckWait 703 Covered T2,T4,T6
AddrRead->Idle 995 Covered T14,T15
AddrRead->WaitForStop 709 Covered T22,T11,T23
Idle->AcquireStart 997 Covered T2,T4,T6
Idle->WaitForStop 1001 Not Covered
StretchAcqFull->AcquireStart 997 Covered T14,T15
StretchAcqFull->Idle 995 Covered T14,T15
StretchAcqFull->StretchAcqSetup 961 Covered T2,T17,T18
StretchAcqFull->WaitForStop 959 Not Covered
StretchAcqSetup->AcquireAckSetup 970 Covered T2,T17,T18
StretchAcqSetup->AcquireStart 997 Not Covered
StretchAcqSetup->Idle 995 Not Covered
StretchAcqSetup->WaitForStop 1001 Not Covered
StretchAddr->AcquireByte 920 Covered T2,T17,T18
StretchAddr->AcquireStart 997 Covered T14,T15
StretchAddr->Idle 995 Covered T14,T15
StretchAddr->StretchTx 920 Not Covered
StretchAddr->WaitForStop 913 Not Covered
StretchAddrAck->AcquireStart 997 Not Covered
StretchAddrAck->Idle 995 Not Covered
StretchAddrAck->StretchAddrAckSetup 895 Not Covered
StretchAddrAck->WaitForStop 893 Not Covered
StretchAddrAckSetup->AcquireStart 997 Not Covered
StretchAddrAckSetup->AddrAckSetup 904 Not Covered
StretchAddrAckSetup->Idle 995 Not Covered
StretchAddrAckSetup->WaitForStop 1001 Not Covered
StretchTx->AcquireStart 997 Covered T14,T15
StretchTx->Idle 995 Covered T14,T15
StretchTx->StretchTxSetup 936 Covered T4,T6,T16
StretchTx->WaitForStop 928 Not Covered
StretchTxSetup->AcquireStart 997 Covered T14,T15
StretchTxSetup->Idle 995 Covered T14,T15
StretchTxSetup->TransmitSetup 947 Covered T4,T6,T16
StretchTxSetup->WaitForStop 1001 Not Covered
TransmitAck->AcquireStart 997 Covered T14,T15
TransmitAck->Idle 995 Covered T14,T15
TransmitAck->TransmitAckPulse 821 Covered T4,T6,T16
TransmitAck->WaitForStop 1001 Not Covered
TransmitAckPulse->AcquireStart 997 Covered T14,T15
TransmitAckPulse->Idle 995 Covered T14,T15
TransmitAckPulse->TransmitWait 830 Covered T4,T6,T16
TransmitAckPulse->WaitForStop 833 Covered T4,T6,T16
TransmitHold->AcquireStart 997 Covered T14,T15
TransmitHold->Idle 995 Covered T14,T15
TransmitHold->TransmitAck 810 Covered T4,T6,T16
TransmitHold->TransmitSetup 814 Covered T4,T6,T16
TransmitHold->WaitForStop 1001 Not Covered
TransmitPulse->AcquireStart 997 Covered T14,T15
TransmitPulse->Idle 995 Covered T14,T15
TransmitPulse->TransmitHold 801 Covered T4,T6,T16
TransmitPulse->WaitForStop 1001 Not Covered
TransmitSetup->AcquireStart 997 Covered T14,T15
TransmitSetup->Idle 995 Covered T14,T15
TransmitSetup->TransmitPulse 796 Covered T4,T6,T16
TransmitSetup->WaitForStop 1001 Not Covered
TransmitWait->AcquireStart 997 Covered T14,T15
TransmitWait->Idle 995 Covered T14,T15
TransmitWait->StretchTx 789 Covered T4,T6,T16
TransmitWait->TransmitSetup 791 Covered T4,T6,T16
TransmitWait->WaitForStop 1001 Not Covered
WaitForStop->AcquireStart 997 Covered T4,T6,T16
WaitForStop->Idle 995 Covered T4,T6,T16



Branch Coverage for Module : i2c_target_fsm
Line No.TotalCoveredPercent
Branches 165 125 75.76
IF 131 6 4 66.67
IF 144 2 2 100.00
IF 154 4 4 100.00
IF 165 3 3 100.00
IF 182 2 2 100.00
IF 191 2 2 100.00
IF 200 2 2 100.00
IF 216 5 5 100.00
IF 239 5 5 100.00
IF 250 4 4 100.00
IF 302 3 3 100.00
CASE 352 44 32 72.73
IF 623 5 3 60.00
CASE 680 69 47 68.12
IF 986 5 3 60.00
IF 1007 2 2 100.00
IF 1016 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 131 if (load_tcount) -2-: 132 case (tcount_sel) -3-: 138 if (target_enable_i)

Branches:
-1--2--3-StatusTests
1 tSetupData - Covered T2,T4,T6
1 tHoldData - Covered T2,T4,T6
1 tNoDelay - Not Covered
1 default - Not Covered
0 - 1 Covered T2,T4,T6
0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 144 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 154 if ((!rst_ni)) -2-: 156 if (actively_stretching) -3-: 158 if ((start_detect_i && target_idle_o))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T4,T6
0 0 1 Covered T1,T2,T4
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if ((!rst_ni)) -2-: 167 if ((auto_ack_load_i && ack_ctrl_stretching))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T11,T12,T13
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 182 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 200 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 216 if ((!rst_ni)) -2-: 218 if (start_detect_i) -3-: 220 if ((scl_i_q && (!scl_i))) -4-: 223 if ((input_byte_clr || bit_ack))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T4
0 0 1 1 Covered T1,T2,T4
0 0 1 0 Covered T1,T2,T3
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 239 if ((!rst_ni)) -2-: 241 if (input_byte_clr) -3-: 243 if (((!scl_i_q) && scl_i)) -4-: 244 if ((!bit_ack))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T2,T4,T6
0 0 1 1 Covered T1,T2,T3
0 0 1 0 Covered T1,T2,T4
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 250 if ((!rst_ni)) -2-: 252 if (((!scl_i_q) && scl_i)) -3-: 253 if (bit_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T1,T2,T4
0 1 0 Covered T1,T2,T3
0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 302 if ((!rst_ni)) -2-: 304 if ((bit_ack && address_match))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T4,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 352 case (state_q) -2-: 380 if (bit_ack) -3-: 381 if (address_match) -4-: 391 if (scl_i) -5-: 416 if ((tcount_q == 16'b1)) -6-: 417 if (nack_transaction_q) -7-: 421 if ((!stretch_addr)) -8-: 427 if (restart_det_q) -9-: 466 if ((!scl_i)) -10-: 484 if (scl_i) -11-: 508 if ((tcount_q == 16'b1)) -12-: 521 if (nack_timeout) -13-: 545 if (nack_timeout) -14-: 552 if ((!stretch_addr)) -15-: 554 if (restart_det_q) -16-: 567 if (nack_timeout) -17-: 589 if ((nack_timeout || (sw_nack_i && (!can_auto_ack))))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17-StatusTests
Idle - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireStart - - - - - - - - - - - - - - - - Covered T2,T4,T6
AddrRead 1 1 - - - - - - - - - - - - - - Covered T2,T4,T6
AddrRead 1 0 - - - - - - - - - - - - - - Covered T22,T11,T23
AddrRead 0 - - - - - - - - - - - - - - - Covered T2,T4,T6
AddrAckWait - - 1 - - - - - - - - - - - - - Not Covered
AddrAckWait - - 0 - - - - - - - - - - - - - Covered T2,T4,T6
AddrAckSetup - - - - - - - - - - - - - - - - Covered T2,T4,T6
AddrAckPulse - - - - - - - - - - - - - - - - Covered T2,T4,T6
AddrAckHold - - - 1 1 - - - - - - - - - - - Not Covered
AddrAckHold - - - 1 0 1 - - - - - - - - - - Covered T2,T4,T6
AddrAckHold - - - 1 0 0 - - - - - - - - - - Covered T2,T17,T18
AddrAckHold - - - 1 - - 1 - - - - - - - - - Covered T2,T4,T6
AddrAckHold - - - 1 - - 0 - - - - - - - - - Covered T2,T4,T6
AddrAckHold - - - 0 - - - - - - - - - - - - Not Covered
TransmitWait - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitSetup - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitPulse - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitHold - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitAck - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitAckPulse - - - - - - - 1 - - - - - - - - Covered T4,T6,T16
TransmitAckPulse - - - - - - - 0 - - - - - - - - Covered T4,T6,T16
WaitForStop - - - - - - - - - - - - - - - - Covered T4,T6,T16
AcquireByte - - - - - - - - - - - - - - - - Covered T2,T4,T6
AcquireAckWait - - - - - - - - 1 - - - - - - - Not Covered
AcquireAckWait - - - - - - - - 0 - - - - - - - Covered T2,T4,T6
AcquireAckSetup - - - - - - - - - - - - - - - - Covered T2,T4,T6
AcquireAckPulse - - - - - - - - - - - - - - - - Covered T2,T4,T6
AcquireAckHold - - - - - - - - - 1 - - - - - - Covered T2,T4,T6
AcquireAckHold - - - - - - - - - 0 - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - 1 - - - - - Not Covered
StretchAddrAck - - - - - - - - - - 0 - - - - - Not Covered
StretchAddrAckSetup - - - - - - - - - - - - - - - - Not Covered
StretchAddr - - - - - - - - - - - 1 - - - - Not Covered
StretchAddr - - - - - - - - - - - 0 1 1 - - Covered T2,T17,T18
StretchAddr - - - - - - - - - - - 0 1 0 - - Covered T2,T17,T24
StretchAddr - - - - - - - - - - - 0 0 - - - Covered T2,T17,T18
StretchTx - - - - - - - - - - - - - - 1 - Not Covered
StretchTx - - - - - - - - - - - - - - 0 - Covered T4,T6,T16
StretchTxSetup - - - - - - - - - - - - - - - - Covered T4,T6,T16
StretchAcqFull - - - - - - - - - - - - - - - 1 Not Covered
StretchAcqFull - - - - - - - - - - - - - - - 0 Covered T2,T17,T18
StretchAcqSetup - - - - - - - - - - - - - - - - Covered T2,T17,T18
default - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 623 if ((target_enable_i && (stop_detect_i || bus_timeout_i))) -2-: 631 if ((nack_transaction_q || bus_timeout_i)) -3-: 636 if ((target_enable_i && start_detect_i)) -4-: 639 if (arbitration_lost_i)

Branches:
-1--2--3--4-StatusTests
1 1 - - Not Covered
1 0 - - Covered T2,T4,T6
0 - 1 - Covered T2,T4,T6
0 - 0 1 Not Covered
0 - 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 680 case (state_q) -2-: 692 if ((!scl_i)) -3-: 701 if (bit_ack) -4-: 702 if (address_match) -5-: 715 if (scl_i) -6-: 718 if ((tcount_q == 16'b1)) -7-: 719 if ((!nack_addr_after_timeout_i)) -8-: 723 if (nack_transaction_q) -9-: 731 if (stretch_addr) -10-: 745 if (scl_i) -11-: 749 if ((!scl_i)) -12-: 757 if ((tcount_q == 16'b1)) -13-: 763 if (nack_transaction_q) -14-: 770 if (stretch_addr) -15-: 777 if (rw_bit_q) -16-: 788 if (stretch_tx) -17-: 796 if (scl_i) -18-: 800 if ((!scl_i)) -19-: 808 if ((tcount_q == 16'b1)) -20-: 809 if (bit_ack) -21-: 820 if (scl_i) -22-: 827 if ((!scl_i)) -23-: 829 if (host_ack) -24-: 845 if (bit_ack) -25-: 853 if (scl_i) -26-: 856 if ((tcount_q == 16'b1)) -27-: 857 if (nack_transaction_q) -28-: 859 if (stretch_rx) -29-: 871 if (scl_i) -30-: 875 if ((!scl_i)) -31-: 883 if ((tcount_q == 16'b1)) -32-: 892 if (nack_timeout) -33-: 894 if ((!stretch_addr)) -34-: 903 if ((tcount_q == 16'b1)) -35-: 912 if (nack_timeout) -36-: 914 if ((!stretch_addr)) -37-: 920 (rw_bit_q) ? -38-: 927 if (nack_timeout) -39-: 929 if ((!stretch_tx)) -40-: 946 if ((tcount_q == 16'b1)) -41-: 958 if ((nack_timeout || (sw_nack_i && (!can_auto_ack)))) -42-: 960 if ((~stretch_rx)) -43-: 969 if ((tcount_q == 16'b1))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26--27--28--29--30--31--32--33--34--35--36--37--38--39--40--41--42--43-StatusTests
Idle - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
AcquireStart 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T4,T6
AcquireStart 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T4,T6
AddrRead - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T4,T6
AddrRead - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T22,T11,T23
AddrRead - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T4,T6
AddrAckWait - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T4,T6
AddrAckWait - - - 0 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 1 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 1 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckWait - - - 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckSetup - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T4,T6
AddrAckSetup - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T4,T6
AddrAckPulse - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T4,T6
AddrAckPulse - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T4,T6
AddrAckHold - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
AddrAckHold - - - - - - - - - - 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T17,T18
AddrAckHold - - - - - - - - - - 1 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
AddrAckHold - - - - - - - - - - 1 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T2,T4,T6
AddrAckHold - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitWait - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitWait - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitSetup - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitSetup - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitPulse - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitPulse - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitHold - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitHold - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitHold - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - Not Covered
TransmitAck - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitAck - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitAckPulse - - - - - - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitAckPulse - - - - - - - - - - - - - - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
TransmitAckPulse - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
WaitForStop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T4,T6,T16
AcquireByte - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - - Covered T2,T4,T6
AcquireByte - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - - - - - - Covered T2,T4,T6
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - - Not Covered
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 1 1 - - - - - - - - - - - - - - - - Not Covered
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 1 0 1 - - - - - - - - - - - - - - - Covered T2,T17,T18
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 1 0 0 - - - - - - - - - - - - - - - Covered T2,T4,T6
AcquireAckWait - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - - - - - - - - - - - Not Covered
AcquireAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - Covered T2,T4,T6
AcquireAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - - Covered T2,T4,T6
AcquireAckPulse - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - Covered T2,T4,T6
AcquireAckPulse - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - - Covered T2,T4,T6
AcquireAckHold - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - Covered T2,T4,T6
AcquireAckHold - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - - - - - - - - - - Not Covered
StretchAddrAck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - - - - Not Covered
StretchAddrAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - Not Covered
StretchAddrAckSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - - - - - - Not Covered
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - Not Covered
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 1 - - - - - - Not Covered
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 0 - - - - - - Covered T2,T17,T18
StretchAddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - - Covered T2,T17,T18
StretchTx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - - Not Covered
StretchTx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - - - - Covered T4,T6,T16
StretchTx - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - - - - Covered T4,T6,T16
StretchTxSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - Covered T4,T6,T16
StretchTxSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - Covered T4,T6,T16
StretchAcqFull - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - Not Covered
StretchAcqFull - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 1 - Covered T2,T17,T18
StretchAcqFull - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 - Covered T2,T17,T18
StretchAcqSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 Covered T2,T17,T18
StretchAcqSetup - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 Covered T2,T17,T18
default - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 986 if (((!target_idle) && (!target_enable_i))) -2-: 996 if ((target_enable_i && start_detect_i)) -3-: 998 if ((stop_detect_i || bus_timeout_i)) -4-: 1000 if (arbitration_lost_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Covered T2,T4,T6
0 0 1 - Covered T1,T2,T4
0 0 0 1 Not Covered
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1007 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 1016 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : i2c_target_fsm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AcqDepthRdCheck_A 348816115 1050871 0 0
AcqFifoDeepEnough_A 348816115 348629247 0 0
SclOutputGlitch_A 348816115 40623 0 0


AcqDepthRdCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348816115 1050871 0 0
T4 774955 20192 0 0
T5 163451 0 0 0
T6 348171 9452 0 0
T7 1984 0 0 0
T8 87321 0 0 0
T9 738178 0 0 0
T10 140748 0 0 0
T16 91526 543 0 0
T22 0 293 0 0
T25 129933 498 0 0
T26 0 4391 0 0
T27 0 366 0 0
T28 0 305 0 0
T29 0 4847 0 0
T30 0 1136 0 0
T31 561811 0 0 0

AcqFifoDeepEnough_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348816115 348629247 0 0
T1 298634 298424 0 0
T2 215277 215270 0 0
T3 2335 2241 0 0
T4 774955 774859 0 0
T5 163451 163354 0 0
T6 348171 348121 0 0
T7 1984 1893 0 0
T8 87321 87258 0 0
T9 738178 737374 0 0
T10 140748 140667 0 0

SclOutputGlitch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348816115 40623 0 0
T2 215277 528 0 0
T3 2335 0 0 0
T4 774955 226 0 0
T5 163451 0 0 0
T6 348171 174 0 0
T7 1984 0 0 0
T8 87321 0 0 0
T9 738178 0 0 0
T10 140748 0 0 0
T16 91526 28 0 0
T17 0 305 0 0
T22 0 15 0 0
T25 0 344 0 0
T26 0 39 0 0
T27 0 53 0 0
T28 0 46 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%