Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
94.44	94.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	94.44	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	3	24	88.89

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	3	24	88.89	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

177042

1

T1

960

T3

40

T5

3

ack

15161

1

T1

30

T2

33

T3

4

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	778	1			T1	7		T3	1		T32	1
high	39320	1			T1	189		T2	4		T3	10
med	71450	1			T1	387		T2	6		T3	16
sml	79946	1			T1	403		T2	23		T3	17
all_zero	709	1			T1	4		T32	1		T142	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95696

1

T1

494

T2

21

T3

25

auto[1]

96507

1

T1

496

T2

12

T3

19

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

131816

1

T1

692

T2

25

T3

33

auto[1]

60387

1

T1

298

T2

8

T3

11

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

184222

1

T1

976

T2

13

T3

44

auto[1]

7981

1

T1

14

T2

20

T32

1

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181659

1

T1

961

T2

20

T3

40

auto[1]

10544

1

T1

29

T2

13

T3

4

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

182701

1

T1

962

T2

21

T3

43

auto[1]

9502

1

T1

28

T2

12

T3

1

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95696

1

T1

494

T2

21

T3

25

auto[1]

96507

1

T1

496

T2

12

T3

19

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

131816

1

T1

692

T2

25

T3

33

auto[1]

60387

1

T1

298

T2

8

T3

11

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

184222

1

T1

976

T2

13

T3

44

auto[1]

7981

1

T1

14

T2

20

T32

1

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181659

1

T1

961

T2

20

T3

40

auto[1]

10544

1

T1

29

T2

13

T3

4

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

182701

1

T1

962

T2

21

T3

43

auto[1]

9502

1

T1

28

T2

12

T3

1

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	3	24	88.89	1
Automatically Generated Cross Bins	15	1	14	93.33	1
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[ack]	0	1	1

Covered bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T259

1

T260

1

T76

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T108

2

T155

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

323

1

T1

3

T142

1

T48

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

141

1

T54

1

T142

1

T73

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

157

1

T48

1

T73

2

T41

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

579

1

T1

3

T54

2

T142

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

275

1

T48

4

T73

3

T118

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

272

1

T1

1

T73

5

T41

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

545

1

T1

2

T54

1

T142

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

299

1

T1

4

T32

1

T142

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

299

1

T1

3

T48

1

T73

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T95

1

T261

1

T262

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T263

1

T264

1

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T48

1

T265

1

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	56389	1			T1	309		T3	15		T31	2
write_address_byte	10544	1			T1	29		T2	13		T3	4
read_with_ack	2320	1			T2	8		T47	12		T33	15
read_with_nack	5661	1			T1	14		T2	12		T32	1
stop_byte	9502	1			T1	28		T2	12		T3	1
write_address_byte_nak	5316	1			T1	26		T32	2		T54	13
data_byte_nack	177042	1			T1	960		T3	40		T5	3
stop_byte_nack	5815	1			T1	25		T3	1		T31	2
nakok_byte_nack	88839	1			T1	480		T3	18		T5	2
nakok_addr_byte_nack	2677	1			T1	10		T32	1		T54	6