Unified Coverage Report :: Group :: i2c_env_pkg::i2c_b2b_txn_cg

Group : i2c_env_pkg::i2c_b2b_txn_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	93.75	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.b2b_txn_target_cg	87.50	1	100	1	64	64
i2c_env_pkg.b2b_txn_host_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.b2b_txn_target_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_target_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group Instance i2c_env_pkg.b2b_txn_target_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	1	7	87.50	100	1	1	0

---

Group Instance : i2c_env_pkg.b2b_txn_host_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.b2b_txn_host_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group Instance i2c_env_pkg.b2b_txn_host_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
B2B_txn_cp	8	0	8	100.00	100	1	1	0

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	1	7	87.50

User Defined Bins for B2B_txn_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
write_after_read_same_addr	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	45	1			T274	1		T275	1		T276	1
b2b_read_same_addr	280	1			T7	1		T8	1		T26	3
write_after_read_different_addr	39	1			T4	1		T277	2		T278	1
read_after_write_different_addr	49	1			T4	1		T26	1		T119	1
read_after_write_same_addr	1	1			T279	1		-	-		-	-
b2b_write_different_addr	37	1			T231	2		T88	1		T280	1
b2b_write_same_addr	233	1			T6	1		T9	1		T29	2

Summary for Variable B2B_txn_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for B2B_txn_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
b2b_read_different_addr	3480	1			T1	13		T2	9		T3	1
b2b_read_same_addr	316	1			T3	2		T5	1		T48	1
write_after_read_different_addr	3518	1			T1	8		T2	9		T32	1
write_after_read_same_addr	52	1			T37	1		T281	1		T282	1
read_after_write_different_addr	3515	1			T1	6		T2	8		T31	1
read_after_write_same_addr	41	1			T1	1		T142	1		T55	1
b2b_write_different_addr	3591	1			T1	1		T2	6		T32	1
b2b_write_same_addr	306	1			T32	1		T41	3		T38	2