Line Coverage for Module :
i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=64,SramAw=9,SramBaseAddr,DepthW=7,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=6,SramDepthW=6,SramAddrLeadingZeros=3 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Line Coverage for Module :
i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=268,SramAw=9,SramBaseAddr=192,DepthW=9,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=9,SramDepthW=9,SramAddrLeadingZeros=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Module :
i2c_fifo_sync_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 43 | 84.31 |
Logical | 51 | 43 | 84.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T41,T37,T95 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T74,T77,T75 |
1 | 1 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T152,T77 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T74,T152,T77 |
1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T74,T152,T77 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T6,T32 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T6,T32 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T6,T32 |
Branch Coverage for Module :
i2c_fifo_sync_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T1,T2,T3 |
1 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
i2c_fifo_sync_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5920 |
5920 |
0 |
0 |
T1 |
4 |
4 |
0 |
0 |
T2 |
4 |
4 |
0 |
0 |
T3 |
4 |
4 |
0 |
0 |
T4 |
4 |
4 |
0 |
0 |
T5 |
4 |
4 |
0 |
0 |
T6 |
4 |
4 |
0 |
0 |
T7 |
4 |
4 |
0 |
0 |
T8 |
4 |
4 |
0 |
0 |
T9 |
4 |
4 |
0 |
0 |
T10 |
4 |
4 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5920 |
5920 |
0 |
0 |
T1 |
4 |
4 |
0 |
0 |
T2 |
4 |
4 |
0 |
0 |
T3 |
4 |
4 |
0 |
0 |
T4 |
4 |
4 |
0 |
0 |
T5 |
4 |
4 |
0 |
0 |
T6 |
4 |
4 |
0 |
0 |
T7 |
4 |
4 |
0 |
0 |
T8 |
4 |
4 |
0 |
0 |
T9 |
4 |
4 |
0 |
0 |
T10 |
4 |
4 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1584100864 |
1583338204 |
0 |
0 |
T1 |
1480180 |
1479972 |
0 |
0 |
T2 |
382960 |
382656 |
0 |
0 |
T3 |
72460 |
70236 |
0 |
0 |
T4 |
150832 |
150628 |
0 |
0 |
T5 |
35900 |
33668 |
0 |
0 |
T6 |
473092 |
472708 |
0 |
0 |
T7 |
42540 |
42192 |
0 |
0 |
T8 |
438752 |
438384 |
0 |
0 |
T9 |
45528 |
45284 |
0 |
0 |
T10 |
164356 |
164076 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1584100864 |
1268507579 |
0 |
0 |
T1 |
1480180 |
1130230 |
0 |
0 |
T2 |
382960 |
372755 |
0 |
0 |
T3 |
72460 |
61038 |
0 |
0 |
T4 |
150832 |
130368 |
0 |
0 |
T5 |
35900 |
30779 |
0 |
0 |
T6 |
473092 |
366082 |
0 |
0 |
T7 |
42540 |
33746 |
0 |
0 |
T8 |
438752 |
360299 |
0 |
0 |
T9 |
45528 |
35239 |
0 |
0 |
T10 |
164356 |
124250 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1584100864 |
22950791 |
0 |
0 |
T1 |
370045 |
164 |
0 |
0 |
T6 |
0 |
88799 |
0 |
0 |
T14 |
219605 |
25 |
0 |
0 |
T15 |
0 |
12 |
0 |
0 |
T16 |
761860 |
0 |
0 |
0 |
T26 |
11855 |
0 |
0 |
0 |
T27 |
26000 |
0 |
0 |
0 |
T28 |
30843 |
0 |
0 |
0 |
T29 |
14086 |
0 |
0 |
0 |
T32 |
684475 |
175010 |
0 |
0 |
T36 |
236592 |
0 |
0 |
0 |
T37 |
0 |
7264 |
0 |
0 |
T41 |
0 |
69933 |
0 |
0 |
T45 |
0 |
69979 |
0 |
0 |
T47 |
155520 |
0 |
0 |
0 |
T48 |
0 |
709 |
0 |
0 |
T54 |
42247 |
0 |
0 |
0 |
T66 |
16538 |
2947 |
0 |
0 |
T73 |
0 |
901 |
0 |
0 |
T80 |
0 |
9068 |
0 |
0 |
T95 |
0 |
153435 |
0 |
0 |
T96 |
0 |
29858 |
0 |
0 |
T108 |
0 |
602 |
0 |
0 |
T128 |
0 |
384232 |
0 |
0 |
T153 |
0 |
56092 |
0 |
0 |
T154 |
0 |
7 |
0 |
0 |
T155 |
0 |
158 |
0 |
0 |
T156 |
0 |
2406 |
0 |
0 |
T157 |
0 |
1618 |
0 |
0 |
T158 |
70156 |
0 |
0 |
0 |
T159 |
13075 |
0 |
0 |
0 |
T160 |
185179 |
0 |
0 |
0 |
T161 |
17583 |
0 |
0 |
0 |
T162 |
19614 |
0 |
0 |
0 |
T163 |
40573 |
0 |
0 |
0 |
T164 |
125136 |
0 |
0 |
0 |
T165 |
811 |
0 |
0 |
0 |
T166 |
932847 |
0 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1584100864 |
528290 |
0 |
0 |
T1 |
740090 |
1875 |
0 |
0 |
T2 |
191480 |
25 |
0 |
0 |
T3 |
36230 |
42 |
0 |
0 |
T4 |
150832 |
68 |
0 |
0 |
T5 |
35900 |
6 |
0 |
0 |
T6 |
473092 |
0 |
0 |
0 |
T7 |
42540 |
0 |
0 |
0 |
T8 |
438752 |
353 |
0 |
0 |
T9 |
45528 |
0 |
0 |
0 |
T10 |
164356 |
289 |
0 |
0 |
T11 |
0 |
161 |
0 |
0 |
T16 |
0 |
397 |
0 |
0 |
T26 |
23710 |
16 |
0 |
0 |
T27 |
0 |
41 |
0 |
0 |
T29 |
0 |
14 |
0 |
0 |
T30 |
0 |
235 |
0 |
0 |
T31 |
474318 |
12 |
0 |
0 |
T32 |
1368950 |
258 |
0 |
0 |
T47 |
0 |
49 |
0 |
0 |
T48 |
0 |
1178 |
0 |
0 |
T54 |
0 |
88 |
0 |
0 |
T66 |
0 |
89 |
0 |
0 |
T142 |
0 |
82 |
0 |
0 |
T167 |
0 |
137 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1584100864 |
528290 |
0 |
0 |
T1 |
740090 |
1875 |
0 |
0 |
T2 |
191480 |
25 |
0 |
0 |
T3 |
36230 |
42 |
0 |
0 |
T4 |
150832 |
68 |
0 |
0 |
T5 |
35900 |
6 |
0 |
0 |
T6 |
473092 |
0 |
0 |
0 |
T7 |
42540 |
0 |
0 |
0 |
T8 |
438752 |
353 |
0 |
0 |
T9 |
45528 |
0 |
0 |
0 |
T10 |
164356 |
289 |
0 |
0 |
T11 |
0 |
161 |
0 |
0 |
T16 |
0 |
397 |
0 |
0 |
T26 |
23710 |
16 |
0 |
0 |
T27 |
0 |
41 |
0 |
0 |
T29 |
0 |
14 |
0 |
0 |
T30 |
0 |
235 |
0 |
0 |
T31 |
474318 |
12 |
0 |
0 |
T32 |
1368950 |
258 |
0 |
0 |
T47 |
0 |
49 |
0 |
0 |
T48 |
0 |
1178 |
0 |
0 |
T54 |
0 |
88 |
0 |
0 |
T66 |
0 |
89 |
0 |
0 |
T142 |
0 |
82 |
0 |
0 |
T167 |
0 |
137 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 38 | 74.51 |
Logical | 51 | 38 | 74.51 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T6,T7 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T6,T7 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T4,T6,T7 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T4,T6,T7 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T6,T7 |
0 | 1 | Covered | T4,T6,T7 |
1 | 0 | Not Covered | |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T4,T6,T7 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T4,T6,T7 |
1 | 0 | Covered | T4,T6,T7 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T4,T6,T7 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T4,T6,T7 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T4,T6,T7 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T4,T6,T7 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T6,T7 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T6,T7 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T96,T97 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T96,T97 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T6,T96,T97 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T6,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T4,T6,T7 |
1 |
0 |
- |
Covered |
T4,T6,T7 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1480 |
1480 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1480 |
1480 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
395834551 |
0 |
0 |
T1 |
370045 |
369993 |
0 |
0 |
T2 |
95740 |
95664 |
0 |
0 |
T3 |
18115 |
17559 |
0 |
0 |
T4 |
37708 |
37657 |
0 |
0 |
T5 |
8975 |
8417 |
0 |
0 |
T6 |
118273 |
118177 |
0 |
0 |
T7 |
10635 |
10548 |
0 |
0 |
T8 |
109688 |
109596 |
0 |
0 |
T9 |
11382 |
11321 |
0 |
0 |
T10 |
41089 |
41019 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
371274478 |
0 |
0 |
T1 |
370045 |
369993 |
0 |
0 |
T2 |
95740 |
95664 |
0 |
0 |
T3 |
18115 |
17559 |
0 |
0 |
T4 |
37708 |
29550 |
0 |
0 |
T5 |
8975 |
8417 |
0 |
0 |
T6 |
118273 |
11551 |
0 |
0 |
T7 |
10635 |
2102 |
0 |
0 |
T8 |
109688 |
78136 |
0 |
0 |
T9 |
11382 |
1276 |
0 |
0 |
T10 |
41089 |
41019 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
2942570 |
0 |
0 |
T6 |
118273 |
88799 |
0 |
0 |
T7 |
10635 |
0 |
0 |
0 |
T8 |
109688 |
0 |
0 |
0 |
T9 |
11382 |
0 |
0 |
0 |
T10 |
41089 |
0 |
0 |
0 |
T26 |
11855 |
0 |
0 |
0 |
T27 |
26000 |
0 |
0 |
0 |
T31 |
237159 |
0 |
0 |
0 |
T32 |
684475 |
0 |
0 |
0 |
T54 |
42247 |
0 |
0 |
0 |
T82 |
0 |
2 |
0 |
0 |
T96 |
0 |
29858 |
0 |
0 |
T97 |
0 |
50572 |
0 |
0 |
T125 |
0 |
108831 |
0 |
0 |
T146 |
0 |
80086 |
0 |
0 |
T168 |
0 |
95883 |
0 |
0 |
T169 |
0 |
32239 |
0 |
0 |
T170 |
0 |
58660 |
0 |
0 |
T171 |
0 |
120 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
50538 |
0 |
0 |
T4 |
37708 |
43 |
0 |
0 |
T5 |
8975 |
0 |
0 |
0 |
T6 |
118273 |
202 |
0 |
0 |
T7 |
10635 |
59 |
0 |
0 |
T8 |
109688 |
211 |
0 |
0 |
T9 |
11382 |
50 |
0 |
0 |
T10 |
41089 |
0 |
0 |
0 |
T26 |
11855 |
15 |
0 |
0 |
T27 |
0 |
41 |
0 |
0 |
T28 |
0 |
32 |
0 |
0 |
T29 |
0 |
3 |
0 |
0 |
T30 |
0 |
227 |
0 |
0 |
T31 |
237159 |
0 |
0 |
0 |
T32 |
684475 |
0 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
50538 |
0 |
0 |
T4 |
37708 |
43 |
0 |
0 |
T5 |
8975 |
0 |
0 |
0 |
T6 |
118273 |
202 |
0 |
0 |
T7 |
10635 |
59 |
0 |
0 |
T8 |
109688 |
211 |
0 |
0 |
T9 |
11382 |
50 |
0 |
0 |
T10 |
41089 |
0 |
0 |
0 |
T26 |
11855 |
15 |
0 |
0 |
T27 |
0 |
41 |
0 |
0 |
T28 |
0 |
32 |
0 |
0 |
T29 |
0 |
3 |
0 |
0 |
T30 |
0 |
227 |
0 |
0 |
T31 |
237159 |
0 |
0 |
0 |
T32 |
684475 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 42 | 82.35 |
Logical | 51 | 42 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T74,T75,T76 |
1 | 1 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T172,T75 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T74,T172,T75 |
1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T74,T172,T75 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T32,T66,T41 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T32,T66,T41 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T32,T66,T41 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T1,T2,T3 |
1 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1480 |
1480 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1480 |
1480 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
395834551 |
0 |
0 |
T1 |
370045 |
369993 |
0 |
0 |
T2 |
95740 |
95664 |
0 |
0 |
T3 |
18115 |
17559 |
0 |
0 |
T4 |
37708 |
37657 |
0 |
0 |
T5 |
8975 |
8417 |
0 |
0 |
T6 |
118273 |
118177 |
0 |
0 |
T7 |
10635 |
10548 |
0 |
0 |
T8 |
109688 |
109596 |
0 |
0 |
T9 |
11382 |
11321 |
0 |
0 |
T10 |
41089 |
41019 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
328296282 |
0 |
0 |
T1 |
370045 |
186477 |
0 |
0 |
T2 |
95740 |
85763 |
0 |
0 |
T3 |
18115 |
8361 |
0 |
0 |
T4 |
37708 |
37657 |
0 |
0 |
T5 |
8975 |
5528 |
0 |
0 |
T6 |
118273 |
118177 |
0 |
0 |
T7 |
10635 |
10548 |
0 |
0 |
T8 |
109688 |
109596 |
0 |
0 |
T9 |
11382 |
11321 |
0 |
0 |
T10 |
41089 |
41019 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
19333977 |
0 |
0 |
T16 |
761860 |
0 |
0 |
0 |
T26 |
11855 |
0 |
0 |
0 |
T27 |
26000 |
0 |
0 |
0 |
T28 |
30843 |
0 |
0 |
0 |
T29 |
14086 |
0 |
0 |
0 |
T32 |
684475 |
175010 |
0 |
0 |
T36 |
236592 |
0 |
0 |
0 |
T41 |
0 |
58589 |
0 |
0 |
T45 |
0 |
69979 |
0 |
0 |
T47 |
155520 |
0 |
0 |
0 |
T54 |
42247 |
0 |
0 |
0 |
T66 |
16538 |
2947 |
0 |
0 |
T80 |
0 |
9068 |
0 |
0 |
T95 |
0 |
143107 |
0 |
0 |
T128 |
0 |
384232 |
0 |
0 |
T153 |
0 |
56083 |
0 |
0 |
T156 |
0 |
2406 |
0 |
0 |
T157 |
0 |
1618 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
179323 |
0 |
0 |
T1 |
370045 |
945 |
0 |
0 |
T2 |
95740 |
25 |
0 |
0 |
T3 |
18115 |
42 |
0 |
0 |
T4 |
37708 |
0 |
0 |
0 |
T5 |
8975 |
6 |
0 |
0 |
T6 |
118273 |
0 |
0 |
0 |
T7 |
10635 |
0 |
0 |
0 |
T8 |
109688 |
0 |
0 |
0 |
T9 |
11382 |
0 |
0 |
0 |
T10 |
41089 |
0 |
0 |
0 |
T31 |
0 |
12 |
0 |
0 |
T32 |
0 |
258 |
0 |
0 |
T47 |
0 |
49 |
0 |
0 |
T54 |
0 |
88 |
0 |
0 |
T66 |
0 |
89 |
0 |
0 |
T142 |
0 |
82 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
179323 |
0 |
0 |
T1 |
370045 |
945 |
0 |
0 |
T2 |
95740 |
25 |
0 |
0 |
T3 |
18115 |
42 |
0 |
0 |
T4 |
37708 |
0 |
0 |
0 |
T5 |
8975 |
6 |
0 |
0 |
T6 |
118273 |
0 |
0 |
0 |
T7 |
10635 |
0 |
0 |
0 |
T8 |
109688 |
0 |
0 |
0 |
T9 |
11382 |
0 |
0 |
0 |
T10 |
41089 |
0 |
0 |
0 |
T31 |
0 |
12 |
0 |
0 |
T32 |
0 |
258 |
0 |
0 |
T47 |
0 |
49 |
0 |
0 |
T54 |
0 |
88 |
0 |
0 |
T66 |
0 |
89 |
0 |
0 |
T142 |
0 |
82 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 42 | 82.35 |
Logical | 51 | 42 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T14,T15 |
1 | 1 | Covered | T4,T6,T7 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T8,T10 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T8,T10 |
1 | 1 | Covered | T4,T8,T10 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T8,T10 |
1 | 1 | Covered | T4,T8,T10 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T8,T10 |
0 | 1 | Covered | T4,T8,T10 |
1 | 0 | Covered | T152,T173,T174 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T152,T173,T174 |
1 | Covered | T4,T8,T10 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T152,T173,T174 |
0 | 1 | Covered | T4,T8,T10 |
1 | 0 | Covered | T4,T8,T10 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T8,T10 |
1 | 1 | Covered | T4,T8,T10 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T8,T10 |
1 | 1 | Covered | T4,T8,T10 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T8,T10 |
1 | 1 | Covered | T4,T8,T10 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T8,T10 |
1 | 1 | Covered | T4,T8,T10 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T8,T10 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T8,T10 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T8,T10 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T14,T15 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T14,T15 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T7,T8 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T14,T15 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T8,T10 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T4,T8,T10 |
1 |
0 |
- |
Covered |
T4,T8,T10 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1480 |
1480 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1480 |
1480 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
395834551 |
0 |
0 |
T1 |
370045 |
369993 |
0 |
0 |
T2 |
95740 |
95664 |
0 |
0 |
T3 |
18115 |
17559 |
0 |
0 |
T4 |
37708 |
37657 |
0 |
0 |
T5 |
8975 |
8417 |
0 |
0 |
T6 |
118273 |
118177 |
0 |
0 |
T7 |
10635 |
10548 |
0 |
0 |
T8 |
109688 |
109596 |
0 |
0 |
T9 |
11382 |
11321 |
0 |
0 |
T10 |
41089 |
41019 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
211569964 |
0 |
0 |
T1 |
370045 |
369993 |
0 |
0 |
T2 |
95740 |
95664 |
0 |
0 |
T3 |
18115 |
17559 |
0 |
0 |
T4 |
37708 |
25504 |
0 |
0 |
T5 |
8975 |
8417 |
0 |
0 |
T6 |
118273 |
118177 |
0 |
0 |
T7 |
10635 |
10548 |
0 |
0 |
T8 |
109688 |
62971 |
0 |
0 |
T9 |
11382 |
11321 |
0 |
0 |
T10 |
41089 |
1193 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
37 |
0 |
0 |
T14 |
219605 |
25 |
0 |
0 |
T15 |
0 |
12 |
0 |
0 |
T158 |
70156 |
0 |
0 |
0 |
T159 |
13075 |
0 |
0 |
0 |
T160 |
185179 |
0 |
0 |
0 |
T161 |
17583 |
0 |
0 |
0 |
T162 |
19614 |
0 |
0 |
0 |
T163 |
40573 |
0 |
0 |
0 |
T164 |
125136 |
0 |
0 |
0 |
T165 |
811 |
0 |
0 |
0 |
T166 |
932847 |
0 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
108992 |
0 |
0 |
T4 |
37708 |
68 |
0 |
0 |
T5 |
8975 |
0 |
0 |
0 |
T6 |
118273 |
0 |
0 |
0 |
T7 |
10635 |
0 |
0 |
0 |
T8 |
109688 |
353 |
0 |
0 |
T9 |
11382 |
0 |
0 |
0 |
T10 |
41089 |
289 |
0 |
0 |
T11 |
0 |
161 |
0 |
0 |
T16 |
0 |
397 |
0 |
0 |
T26 |
11855 |
16 |
0 |
0 |
T27 |
0 |
41 |
0 |
0 |
T29 |
0 |
14 |
0 |
0 |
T30 |
0 |
235 |
0 |
0 |
T31 |
237159 |
0 |
0 |
0 |
T32 |
684475 |
0 |
0 |
0 |
T167 |
0 |
137 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
108992 |
0 |
0 |
T4 |
37708 |
68 |
0 |
0 |
T5 |
8975 |
0 |
0 |
0 |
T6 |
118273 |
0 |
0 |
0 |
T7 |
10635 |
0 |
0 |
0 |
T8 |
109688 |
353 |
0 |
0 |
T9 |
11382 |
0 |
0 |
0 |
T10 |
41089 |
289 |
0 |
0 |
T11 |
0 |
161 |
0 |
0 |
T16 |
0 |
397 |
0 |
0 |
T26 |
11855 |
16 |
0 |
0 |
T27 |
0 |
41 |
0 |
0 |
T29 |
0 |
14 |
0 |
0 |
T30 |
0 |
235 |
0 |
0 |
T31 |
237159 |
0 |
0 |
0 |
T32 |
684475 |
0 |
0 |
0 |
T167 |
0 |
137 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 43 | 84.31 |
Logical | 51 | 43 | 84.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T41,T37,T95 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T77,T78,T79 |
1 | 1 | Covered | T1,T48,T73 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T48,T73 |
1 | 1 | Covered | T1,T48,T73 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T48,T73 |
1 | 1 | Covered | T1,T48,T73 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T48,T73 |
0 | 1 | Covered | T1,T48,T73 |
1 | 0 | Covered | T77,T78,T175 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T77,T78,T175 |
1 | Covered | T1,T48,T73 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T77,T78,T175 |
0 | 1 | Covered | T1,T48,T73 |
1 | 0 | Covered | T1,T48,T73 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T48,T73 |
1 | 1 | Covered | T1,T48,T73 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T48,T73 |
1 | 1 | Covered | T1,T48,T73 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T48,T73 |
1 | 1 | Covered | T1,T48,T73 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T48,T73 |
1 | 1 | Covered | T1,T48,T73 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T48,T73 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T48,T73 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T48,T73 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T48,T73 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T48,T73 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T48,T73 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T48,T73 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T48,T73 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T1,T48,T73 |
1 |
0 |
- |
Covered |
T1,T48,T73 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1480 |
1480 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1480 |
1480 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
395834551 |
0 |
0 |
T1 |
370045 |
369993 |
0 |
0 |
T2 |
95740 |
95664 |
0 |
0 |
T3 |
18115 |
17559 |
0 |
0 |
T4 |
37708 |
37657 |
0 |
0 |
T5 |
8975 |
8417 |
0 |
0 |
T6 |
118273 |
118177 |
0 |
0 |
T7 |
10635 |
10548 |
0 |
0 |
T8 |
109688 |
109596 |
0 |
0 |
T9 |
11382 |
11321 |
0 |
0 |
T10 |
41089 |
41019 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
357366855 |
0 |
0 |
T1 |
370045 |
203767 |
0 |
0 |
T2 |
95740 |
95664 |
0 |
0 |
T3 |
18115 |
17559 |
0 |
0 |
T4 |
37708 |
37657 |
0 |
0 |
T5 |
8975 |
8417 |
0 |
0 |
T6 |
118273 |
118177 |
0 |
0 |
T7 |
10635 |
10548 |
0 |
0 |
T8 |
109688 |
109596 |
0 |
0 |
T9 |
11382 |
11321 |
0 |
0 |
T10 |
41089 |
41019 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
674207 |
0 |
0 |
T1 |
370045 |
164 |
0 |
0 |
T2 |
95740 |
0 |
0 |
0 |
T3 |
18115 |
0 |
0 |
0 |
T4 |
37708 |
0 |
0 |
0 |
T5 |
8975 |
0 |
0 |
0 |
T6 |
118273 |
0 |
0 |
0 |
T7 |
10635 |
0 |
0 |
0 |
T8 |
109688 |
0 |
0 |
0 |
T9 |
11382 |
0 |
0 |
0 |
T10 |
41089 |
0 |
0 |
0 |
T37 |
0 |
7264 |
0 |
0 |
T41 |
0 |
11344 |
0 |
0 |
T48 |
0 |
709 |
0 |
0 |
T73 |
0 |
901 |
0 |
0 |
T95 |
0 |
10328 |
0 |
0 |
T108 |
0 |
602 |
0 |
0 |
T153 |
0 |
9 |
0 |
0 |
T154 |
0 |
7 |
0 |
0 |
T155 |
0 |
158 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
189437 |
0 |
0 |
T1 |
370045 |
930 |
0 |
0 |
T2 |
95740 |
0 |
0 |
0 |
T3 |
18115 |
0 |
0 |
0 |
T4 |
37708 |
0 |
0 |
0 |
T5 |
8975 |
0 |
0 |
0 |
T6 |
118273 |
0 |
0 |
0 |
T7 |
10635 |
0 |
0 |
0 |
T8 |
109688 |
0 |
0 |
0 |
T9 |
11382 |
0 |
0 |
0 |
T10 |
41089 |
0 |
0 |
0 |
T37 |
0 |
2976 |
0 |
0 |
T41 |
0 |
3790 |
0 |
0 |
T48 |
0 |
1178 |
0 |
0 |
T73 |
0 |
1054 |
0 |
0 |
T95 |
0 |
5642 |
0 |
0 |
T108 |
0 |
806 |
0 |
0 |
T153 |
0 |
64 |
0 |
0 |
T155 |
0 |
930 |
0 |
0 |
T176 |
0 |
992 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
396025216 |
189437 |
0 |
0 |
T1 |
370045 |
930 |
0 |
0 |
T2 |
95740 |
0 |
0 |
0 |
T3 |
18115 |
0 |
0 |
0 |
T4 |
37708 |
0 |
0 |
0 |
T5 |
8975 |
0 |
0 |
0 |
T6 |
118273 |
0 |
0 |
0 |
T7 |
10635 |
0 |
0 |
0 |
T8 |
109688 |
0 |
0 |
0 |
T9 |
11382 |
0 |
0 |
0 |
T10 |
41089 |
0 |
0 |
0 |
T37 |
0 |
2976 |
0 |
0 |
T41 |
0 |
3790 |
0 |
0 |
T48 |
0 |
1178 |
0 |
0 |
T73 |
0 |
1054 |
0 |
0 |
T95 |
0 |
5642 |
0 |
0 |
T108 |
0 |
806 |
0 |
0 |
T153 |
0 |
64 |
0 |
0 |
T155 |
0 |
930 |
0 |
0 |
T176 |
0 |
992 |
0 |
0 |