Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	396685548	0	0	0
ctrl_rd_A	396685548	2354	0	0
host_fifo_config_rd_A	396685548	5735	0	0
host_nack_handler_timeout_rd_A	396685548	1928	0	0
host_timeout_ctrl_rd_A	396685548	1685	0	0
intr_enable_rd_A	396685548	4086	0	0
ovrd_rd_A	396685548	2705	0	0
target_fifo_config_rd_A	396685548	1902	0	0
target_id_rd_A	396685548	2149	0	0
target_timeout_ctrl_rd_A	396685548	1888	0	0
timeout_ctrl_rd_A	396685548	1911	0	0
timing0_rd_A	396685548	1901	0	0
timing1_rd_A	396685548	1888	0	0
timing2_rd_A	396685548	1961	0	0
timing3_rd_A	396685548	1826	0	0
timing4_rd_A	396685548	1838	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	2354	0	0
T98	3436	5	0	0
T99	23452	149	0	0
T100	3041	23	0	0
T101	12120	92	0	0
T102	45566	214	0	0
T103	6651	126	0	0
T104	2220	17	0	0
T105	5279	33	0	0
T106	13502	364	0	0
T107	10910	25	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	5735	0	0
T23	94663	0	0	0
T37	0	195	0	0
T41	221547	125	0	0
T73	471616	184	0	0
T97	85180	0	0	0
T108	0	162	0	0
T109	0	109	0	0
T110	0	117	0	0
T111	0	114	0	0
T112	0	325	0	0
T113	0	239	0	0
T114	0	77	0	0
T115	1555	0	0	0
T116	93687	0	0	0
T117	149521	0	0	0
T118	57277	0	0	0
T119	98209	0	0	0
T120	272036	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	1928	0	0
T98	3436	28	0	0
T99	23452	150	0	0
T100	3041	6	0	0
T101	12120	84	0	0
T102	45566	279	0	0
T103	6651	132	0	0
T104	2220	21	0	0
T105	5279	22	0	0
T106	13502	133	0	0
T121	3788	1	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	1685	0	0
T98	3436	9	0	0
T99	23452	97	0	0
T100	3041	4	0	0
T101	12120	31	0	0
T102	45566	286	0	0
T103	6651	147	0	0
T104	2220	6	0	0
T105	5279	31	0	0
T106	13502	76	0	0
T121	3788	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	4086	0	0
T19	5820	0	0	0
T20	15785	0	0	0
T37	0	5	0	0
T41	221547	11	0	0
T43	0	14	0	0
T46	0	56	0	0
T76	0	7	0	0
T112	0	36	0	0
T113	0	18	0	0
T119	98209	0	0	0
T120	272036	0	0	0
T122	0	28	0	0
T123	0	19	0	0
T124	0	2	0	0
T125	136645	0	0	0
T126	1257	0	0	0
T127	68069	0	0	0
T128	520783	0	0	0
T129	20562	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	2705	0	0
T23	94663	0	0	0
T55	167387	0	0	0
T69	134610	0	0	0
T71	2796	37	0	0
T73	471616	0	0	0
T94	0	40	0	0
T97	85180	0	0	0
T115	1555	0	0	0
T116	93687	0	0	0
T117	149521	0	0	0
T130	0	60	0	0
T131	0	52	0	0
T132	0	20	0	0
T133	0	42	0	0
T134	0	43	0	0
T135	0	37	0	0
T136	0	80	0	0
T137	0	23	0	0
T138	1140	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	1902	0	0
T98	3436	33	0	0
T99	23452	165	0	0
T100	3041	5	0	0
T101	12120	52	0	0
T102	45566	298	0	0
T103	6651	114	0	0
T104	2220	21	0	0
T105	5279	26	0	0
T106	13502	105	0	0
T121	3788	8	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	2149	0	0
T98	3436	14	0	0
T99	23452	152	0	0
T100	3041	1	0	0
T101	12120	122	0	0
T102	45566	246	0	0
T103	6651	122	0	0
T104	2220	11	0	0
T105	5279	31	0	0
T106	13502	230	0	0
T107	10910	16	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	1888	0	0
T98	3436	16	0	0
T99	23452	126	0	0
T100	3041	17	0	0
T101	12120	64	0	0
T102	45566	317	0	0
T103	6651	122	0	0
T104	2220	6	0	0
T105	5279	23	0	0
T106	13502	114	0	0
T107	10910	6	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	1911	0	0
T98	3436	22	0	0
T99	23452	123	0	0
T100	3041	23	0	0
T101	12120	114	0	0
T102	45566	259	0	0
T103	6651	98	0	0
T104	2220	17	0	0
T105	5279	26	0	0
T106	13502	171	0	0
T107	10910	18	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	1901	0	0
T98	3436	19	0	0
T99	23452	152	0	0
T100	3041	9	0	0
T101	12120	66	0	0
T102	45566	277	0	0
T103	6651	108	0	0
T104	2220	8	0	0
T105	5279	46	0	0
T106	13502	104	0	0
T121	3788	9	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	1888	0	0
T98	3436	17	0	0
T99	23452	144	0	0
T100	3041	4	0	0
T101	12120	59	0	0
T102	45566	296	0	0
T103	6651	109	0	0
T104	2220	2	0	0
T105	5279	39	0	0
T106	13502	149	0	0
T121	3788	9	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	1961	0	0
T98	3436	10	0	0
T99	23452	171	0	0
T100	3041	16	0	0
T101	12120	30	0	0
T102	45566	302	0	0
T103	6651	125	0	0
T104	2220	11	0	0
T105	5279	36	0	0
T106	13502	121	0	0
T121	3788	8	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	1826	0	0
T98	3436	22	0	0
T99	23452	127	0	0
T100	3041	10	0	0
T101	12120	47	0	0
T102	45566	246	0	0
T103	6651	128	0	0
T104	2220	13	0	0
T105	5279	9	0	0
T106	13502	124	0	0
T107	10910	13	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396685548	1838	0	0
T98	3436	16	0	0
T99	23452	126	0	0
T100	3041	6	0	0
T101	12120	42	0	0
T102	45566	258	0	0
T103	6651	92	0	0
T104	2220	24	0	0
T105	5279	29	0	0
T106	13502	106	0	0
T121	3788	5	0	0