Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	948784	1			T1	2		T2	3		T3	2
all_values[1]	948784	1			T1	2		T2	3		T3	2
all_values[2]	948784	1			T1	2		T2	3		T3	2
all_values[3]	948784	1			T1	2		T2	3		T3	2
all_values[4]	948784	1			T1	2		T2	3		T3	2
all_values[5]	948784	1			T1	2		T2	3		T3	2
all_values[6]	948784	1			T1	2		T2	3		T3	2
all_values[7]	948784	1			T1	2		T2	3		T3	2
all_values[8]	948784	1			T1	2		T2	3		T3	2
all_values[9]	948784	1			T1	2		T2	3		T3	2
all_values[10]	948784	1			T1	2		T2	3		T3	2
all_values[11]	948784	1			T1	2		T2	3		T3	2
all_values[12]	948784	1			T1	2		T2	3		T3	2
all_values[13]	948784	1			T1	2		T2	3		T3	2
all_values[14]	948784	1			T1	2		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11638583

1

T1

26

T2

39

T3

26

auto[1]

2593177

1

T1

4

T2

6

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12540375

1

T1

30

T2

45

T3

30

auto[1]

1691385

1

T155

4996

T126

119

T66

3042

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	92816	1			T2	1		T5	1		T6	1
all_values[0]	auto[0]	auto[1]	9729	1			T155	12		T126	6		T66	15
all_values[0]	auto[1]	auto[0]	741346	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	104893	1			T155	345		T126	2		T66	202
all_values[1]	auto[0]	auto[0]	839065	1			T1	2		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	109045	1			T155	354		T126	4		T66	215
all_values[1]	auto[1]	auto[0]	454	1			T155	53		T55	2		T251	1
all_values[1]	auto[1]	auto[1]	220	1			T155	3		T126	1		T66	1
all_values[2]	auto[0]	auto[0]	834758	1			T1	2		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	113776	1			T155	352		T126	4		T66	216
all_values[2]	auto[1]	auto[0]	50	1			T32	1		T164	1		T181	1
all_values[2]	auto[1]	auto[1]	200	1			T155	4		T126	5		T66	2
all_values[3]	auto[0]	auto[0]	834185	1			T1	2		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	114375	1			T155	354		T126	5		T66	216
all_values[3]	auto[1]	auto[1]	224	1			T155	2		T126	4		T66	2
all_values[4]	auto[0]	auto[0]	834157	1			T1	2		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	114419	1			T155	355		T126	4		T66	216
all_values[4]	auto[1]	auto[0]	19	1			T252	2		T253	1		T254	1
all_values[4]	auto[1]	auto[1]	189	1			T155	2		T126	4		T66	2
all_values[5]	auto[0]	auto[0]	834175	1			T1	2		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	114381	1			T155	350		T126	2		T66	214
all_values[5]	auto[1]	auto[1]	228	1			T155	7		T126	2		T66	3
all_values[6]	auto[0]	auto[0]	841652	1			T1	2		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	106891	1			T155	352		T126	4		T66	216
all_values[6]	auto[1]	auto[1]	241	1			T155	4		T126	5		T55	3
all_values[7]	auto[0]	auto[0]	815141	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	103622	1			T155	308		T126	6		T55	22218
all_values[7]	auto[1]	auto[0]	26741	1			T2	1		T6	1		T30	113
all_values[7]	auto[1]	auto[1]	3280	1			T155	49		T126	2		T55	254
all_values[8]	auto[0]	auto[0]	834836	1			T1	2		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	113727	1			T155	4		T126	2		T66	214
all_values[8]	auto[1]	auto[1]	221	1			T155	2		T126	5		T66	3
all_values[9]	auto[0]	auto[0]	170036	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	10179	1			T155	330		T126	5		T66	200
all_values[9]	auto[1]	auto[0]	664137	1			T2	1		T6	1		T30	2
all_values[9]	auto[1]	auto[1]	104432	1			T155	25		T126	3		T66	17
all_values[10]	auto[0]	auto[0]	839499	1			T1	2		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	109076	1			T155	352		T126	5		T66	215
all_values[10]	auto[1]	auto[1]	209	1			T155	5		T126	3		T66	3
all_values[11]	auto[0]	auto[0]	2908	1			T2	1		T5	1		T6	1
all_values[11]	auto[0]	auto[1]	470	1			T126	8		T66	5		T55	9
all_values[11]	auto[1]	auto[0]	831260	1			T1	2		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	114146	1			T155	355		T126	1		T66	213
all_values[12]	auto[0]	auto[0]	834479	1			T1	2		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	114092	1			T155	352		T126	6		T66	215
all_values[12]	auto[1]	auto[0]	13	1			T32	1		T255	1		T256	1
all_values[12]	auto[1]	auto[1]	200	1			T155	5		T126	3		T66	1
all_values[13]	auto[0]	auto[0]	834177	1			T1	2		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	114369	1			T155	355		T126	8		T66	214
all_values[13]	auto[1]	auto[1]	238	1			T155	2		T126	1		T66	4
all_values[14]	auto[0]	auto[0]	834471	1			T1	2		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	114077	1			T155	351		T126	5		T66	216
all_values[14]	auto[1]	auto[1]	236	1			T155	5		T126	4		T66	2