Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
15 |
0 |
15 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
| | | | | | | | | | | | |
all_pins[0] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[1] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[2] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[3] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[4] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[5] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[6] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[7] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[8] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[9] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[10] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[11] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[12] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[13] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[14] |
948784 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
| | | | | | | | | | | | |
values[0x0] |
11643788 |
1 |
|
|
T1 |
26 |
|
T2 |
39 |
|
T3 |
26 |
values[0x1] |
2587972 |
1 |
|
|
T1 |
4 |
|
T2 |
6 |
|
T3 |
4 |
transitions[0x0=>0x1] |
2586932 |
1 |
|
|
T1 |
4 |
|
T2 |
6 |
|
T3 |
4 |
transitions[0x1=>0x0] |
2585736 |
1 |
|
|
T1 |
3 |
|
T2 |
5 |
|
T3 |
3 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
60 |
0 |
60 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
| | | | | | | | | | | | | |
all_pins[0] |
values[0x0] |
105945 |
1 |
|
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
1 |
all_pins[0] |
values[0x1] |
842839 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
all_pins[0] |
transitions[0x0=>0x1] |
842232 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
all_pins[0] |
transitions[0x1=>0x0] |
66 |
1 |
|
|
T155 |
2 |
|
T57 |
1 |
|
T277 |
1 |
all_pins[1] |
values[0x0] |
948111 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[1] |
values[0x1] |
673 |
1 |
|
|
T155 |
71 |
|
T126 |
1 |
|
T66 |
1 |
all_pins[1] |
transitions[0x0=>0x1] |
656 |
1 |
|
|
T155 |
71 |
|
T126 |
1 |
|
T66 |
1 |
all_pins[1] |
transitions[0x1=>0x0] |
130 |
1 |
|
|
T32 |
1 |
|
T164 |
1 |
|
T181 |
1 |
all_pins[2] |
values[0x0] |
948637 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[2] |
values[0x1] |
147 |
1 |
|
|
T32 |
1 |
|
T164 |
1 |
|
T181 |
1 |
all_pins[2] |
transitions[0x0=>0x1] |
126 |
1 |
|
|
T32 |
1 |
|
T164 |
1 |
|
T181 |
1 |
all_pins[2] |
transitions[0x1=>0x0] |
86 |
1 |
|
|
T126 |
2 |
|
T66 |
2 |
|
T55 |
1 |
all_pins[3] |
values[0x0] |
948677 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[3] |
values[0x1] |
107 |
1 |
|
|
T155 |
1 |
|
T126 |
2 |
|
T66 |
2 |
all_pins[3] |
transitions[0x0=>0x1] |
79 |
1 |
|
|
T155 |
1 |
|
T126 |
2 |
|
T66 |
2 |
all_pins[3] |
transitions[0x1=>0x0] |
94 |
1 |
|
|
T126 |
1 |
|
T55 |
2 |
|
T47 |
1 |
all_pins[4] |
values[0x0] |
948662 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[4] |
values[0x1] |
122 |
1 |
|
|
T126 |
1 |
|
T55 |
3 |
|
T47 |
1 |
all_pins[4] |
transitions[0x0=>0x1] |
98 |
1 |
|
|
T126 |
1 |
|
T55 |
2 |
|
T47 |
1 |
all_pins[4] |
transitions[0x1=>0x0] |
100 |
1 |
|
|
T155 |
2 |
|
T66 |
3 |
|
T55 |
1 |
all_pins[5] |
values[0x0] |
948660 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[5] |
values[0x1] |
124 |
1 |
|
|
T155 |
2 |
|
T66 |
3 |
|
T55 |
2 |
all_pins[5] |
transitions[0x0=>0x1] |
93 |
1 |
|
|
T155 |
1 |
|
T66 |
3 |
|
T55 |
2 |
all_pins[5] |
transitions[0x1=>0x0] |
86 |
1 |
|
|
T126 |
3 |
|
T55 |
1 |
|
T57 |
4 |
all_pins[6] |
values[0x0] |
948667 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[6] |
values[0x1] |
117 |
1 |
|
|
T155 |
1 |
|
T126 |
3 |
|
T55 |
1 |
all_pins[6] |
transitions[0x0=>0x1] |
83 |
1 |
|
|
T126 |
3 |
|
T55 |
1 |
|
T57 |
4 |
all_pins[6] |
transitions[0x1=>0x0] |
33183 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T30 |
117 |
all_pins[7] |
values[0x0] |
915567 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
all_pins[7] |
values[0x1] |
33217 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T30 |
117 |
all_pins[7] |
transitions[0x0=>0x1] |
33194 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T30 |
117 |
all_pins[7] |
transitions[0x1=>0x0] |
77 |
1 |
|
|
T155 |
2 |
|
T126 |
2 |
|
T66 |
1 |
all_pins[8] |
values[0x0] |
948684 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[8] |
values[0x1] |
100 |
1 |
|
|
T155 |
2 |
|
T126 |
2 |
|
T66 |
1 |
all_pins[8] |
transitions[0x0=>0x1] |
66 |
1 |
|
|
T155 |
2 |
|
T126 |
1 |
|
T55 |
1 |
all_pins[8] |
transitions[0x1=>0x0] |
768444 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T30 |
2 |
all_pins[9] |
values[0x0] |
180306 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
all_pins[9] |
values[0x1] |
768478 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T30 |
2 |
all_pins[9] |
transitions[0x0=>0x1] |
768451 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T30 |
2 |
all_pins[9] |
transitions[0x1=>0x0] |
84 |
1 |
|
|
T155 |
3 |
|
T126 |
2 |
|
T55 |
1 |
all_pins[10] |
values[0x0] |
948673 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[10] |
values[0x1] |
111 |
1 |
|
|
T155 |
3 |
|
T126 |
2 |
|
T55 |
1 |
all_pins[10] |
transitions[0x0=>0x1] |
75 |
1 |
|
|
T155 |
1 |
|
T126 |
2 |
|
T55 |
1 |
all_pins[10] |
transitions[0x1=>0x0] |
941552 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
all_pins[11] |
values[0x0] |
7196 |
1 |
|
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
1 |
all_pins[11] |
values[0x1] |
941588 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
all_pins[11] |
transitions[0x0=>0x1] |
941533 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
all_pins[11] |
transitions[0x1=>0x0] |
61 |
1 |
|
|
T155 |
1 |
|
T116 |
1 |
|
T264 |
3 |
all_pins[12] |
values[0x0] |
948668 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[12] |
values[0x1] |
116 |
1 |
|
|
T32 |
1 |
|
T164 |
1 |
|
T248 |
1 |
all_pins[12] |
transitions[0x0=>0x1] |
98 |
1 |
|
|
T32 |
1 |
|
T164 |
1 |
|
T248 |
1 |
all_pins[12] |
transitions[0x1=>0x0] |
98 |
1 |
|
|
T66 |
1 |
|
T47 |
1 |
|
T57 |
1 |
all_pins[13] |
values[0x0] |
948668 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[13] |
values[0x1] |
116 |
1 |
|
|
T155 |
2 |
|
T66 |
1 |
|
T47 |
1 |
all_pins[13] |
transitions[0x0=>0x1] |
77 |
1 |
|
|
T155 |
2 |
|
T47 |
1 |
|
T57 |
1 |
all_pins[13] |
transitions[0x1=>0x0] |
78 |
1 |
|
|
T155 |
3 |
|
T66 |
1 |
|
T55 |
1 |
all_pins[14] |
values[0x0] |
948667 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
2 |
all_pins[14] |
values[0x1] |
117 |
1 |
|
|
T155 |
3 |
|
T66 |
2 |
|
T55 |
1 |
all_pins[14] |
transitions[0x0=>0x1] |
71 |
1 |
|
|
T155 |
2 |
|
T66 |
1 |
|
T57 |
3 |
all_pins[14] |
transitions[0x1=>0x0] |
841597 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |