Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	476	1			T155	8		T126	7		T66	4
all_values[1]	476	1			T155	8		T126	7		T66	4
all_values[2]	476	1			T155	8		T126	7		T66	4
all_values[3]	476	1			T155	8		T126	7		T66	4
all_values[4]	476	1			T155	8		T126	7		T66	4
all_values[5]	476	1			T155	8		T126	7		T66	4
all_values[6]	476	1			T155	8		T126	7		T66	4
all_values[7]	476	1			T155	8		T126	7		T66	4
all_values[8]	476	1			T155	8		T126	7		T66	4
all_values[9]	476	1			T155	8		T126	7		T66	4
all_values[10]	476	1			T155	8		T126	7		T66	4
all_values[11]	476	1			T155	8		T126	7		T66	4
all_values[12]	476	1			T155	8		T126	7		T66	4
all_values[13]	476	1			T155	8		T126	7		T66	4
all_values[14]	476	1			T155	8		T126	7		T66	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3641

1

T155

53

T126

61

T66

33

auto[1]

3499

1

T155

67

T126

44

T66

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1151

1

T155

12

T126

16

T66

14

auto[1]

5989

1

T155

108

T126

89

T66

46

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4188

1

T155

71

T126

62

T66

37

auto[1]

2952

1

T155

49

T126

43

T66

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	40	1			T126	1		T66	1		T47	1
all_values[0]	auto[0]	auto[0]	auto[1]	105	1			T155	3		T126	1		T47	1
all_values[0]	auto[0]	auto[1]	auto[0]	26	1			T277	2		T278	3		T279	1
all_values[0]	auto[0]	auto[1]	auto[1]	97	1			T155	3		T126	3		T66	2
all_values[0]	auto[1]	auto[0]	auto[1]	113	1			T155	1		T126	1		T66	1
all_values[0]	auto[1]	auto[1]	auto[1]	95	1			T155	1		T126	1		T55	6
all_values[1]	auto[0]	auto[0]	auto[0]	47	1			T66	1		T47	2		T57	2
all_values[1]	auto[0]	auto[0]	auto[1]	111	1			T155	1		T66	1		T55	3
all_values[1]	auto[0]	auto[1]	auto[0]	32	1			T126	4		T66	1		T47	2
all_values[1]	auto[0]	auto[1]	auto[1]	96	1			T155	4		T126	2		T57	1
all_values[1]	auto[1]	auto[0]	auto[1]	104	1			T155	1		T66	1		T55	2
all_values[1]	auto[1]	auto[1]	auto[1]	86	1			T155	2		T126	1		T55	2
all_values[2]	auto[0]	auto[0]	auto[0]	46	1			T47	2		T57	2		T116	2
all_values[2]	auto[0]	auto[0]	auto[1]	90	1			T155	2		T126	2		T66	1
all_values[2]	auto[0]	auto[1]	auto[0]	37	1			T155	1		T47	2		T57	1
all_values[2]	auto[0]	auto[1]	auto[1]	103	1			T155	1		T66	1		T55	1
all_values[2]	auto[1]	auto[0]	auto[1]	107	1			T155	4		T126	2		T66	2
all_values[2]	auto[1]	auto[1]	auto[1]	93	1			T126	3		T55	1		T57	1
all_values[3]	auto[0]	auto[0]	auto[0]	43	1			T57	1		T116	1		T280	1
all_values[3]	auto[0]	auto[0]	auto[1]	95	1			T155	4		T55	3		T47	3
all_values[3]	auto[0]	auto[1]	auto[0]	34	1			T155	1		T55	1		T118	2
all_values[3]	auto[0]	auto[1]	auto[1]	109	1			T126	3		T66	2		T55	1
all_values[3]	auto[1]	auto[0]	auto[1]	104	1			T155	2		T126	3		T47	1
all_values[3]	auto[1]	auto[1]	auto[1]	91	1			T155	1		T126	1		T66	2
all_values[4]	auto[0]	auto[0]	auto[0]	48	1			T126	1		T47	1		T264	1
all_values[4]	auto[0]	auto[0]	auto[1]	96	1			T155	1		T126	1		T66	2
all_values[4]	auto[0]	auto[1]	auto[0]	31	1			T277	3		T118	1		T279	3
all_values[4]	auto[0]	auto[1]	auto[1]	112	1			T155	5		T126	1		T55	1
all_values[4]	auto[1]	auto[0]	auto[1]	90	1			T155	1		T126	4		T66	2
all_values[4]	auto[1]	auto[1]	auto[1]	99	1			T155	1		T55	3		T57	3
all_values[5]	auto[0]	auto[0]	auto[0]	42	1			T126	3		T66	1		T264	1
all_values[5]	auto[0]	auto[0]	auto[1]	87	1			T155	3		T126	1		T55	2
all_values[5]	auto[0]	auto[1]	auto[0]	36	1			T126	2		T55	1		T47	2
all_values[5]	auto[0]	auto[1]	auto[1]	122	1			T155	1		T66	1		T47	1
all_values[5]	auto[1]	auto[0]	auto[1]	101	1			T155	2		T55	3		T57	1
all_values[5]	auto[1]	auto[1]	auto[1]	88	1			T155	2		T126	1		T66	2
all_values[6]	auto[0]	auto[0]	auto[0]	40	1			T66	2		T47	1		T264	3
all_values[6]	auto[0]	auto[0]	auto[1]	95	1			T155	2		T126	3		T55	2
all_values[6]	auto[0]	auto[1]	auto[0]	29	1			T155	1		T55	1		T278	1
all_values[6]	auto[0]	auto[1]	auto[1]	104	1			T155	2		T126	1		T66	1
all_values[6]	auto[1]	auto[0]	auto[1]	112	1			T126	2		T47	2		T57	2
all_values[6]	auto[1]	auto[1]	auto[1]	96	1			T155	3		T126	1		T66	1
all_values[7]	auto[0]	auto[0]	auto[0]	42	1			T126	1		T66	1		T90	2
all_values[7]	auto[0]	auto[0]	auto[1]	91	1			T155	3		T126	1		T55	3
all_values[7]	auto[0]	auto[1]	auto[0]	40	1			T66	3		T280	3		T281	1
all_values[7]	auto[0]	auto[1]	auto[1]	106	1			T155	1		T126	2		T47	1
all_values[7]	auto[1]	auto[0]	auto[1]	99	1			T155	2		T126	1		T55	2
all_values[7]	auto[1]	auto[1]	auto[1]	98	1			T155	2		T126	2		T55	2
all_values[8]	auto[0]	auto[0]	auto[0]	55	1			T155	1		T126	2		T66	1
all_values[8]	auto[0]	auto[0]	auto[1]	105	1			T126	1		T66	1		T57	3
all_values[8]	auto[0]	auto[1]	auto[0]	40	1			T155	3		T47	1		T116	2
all_values[8]	auto[0]	auto[1]	auto[1]	85	1			T155	2		T126	1		T55	4
all_values[8]	auto[1]	auto[0]	auto[1]	104	1			T126	2		T66	1		T57	2
all_values[8]	auto[1]	auto[1]	auto[1]	87	1			T155	2		T126	1		T66	1
all_values[9]	auto[0]	auto[0]	auto[0]	36	1			T155	1		T126	1		T66	1
all_values[9]	auto[0]	auto[0]	auto[1]	89	1			T155	2		T126	1		T55	2
all_values[9]	auto[0]	auto[1]	auto[0]	43	1			T155	1		T55	1		T47	1
all_values[9]	auto[0]	auto[1]	auto[1]	104	1			T126	1		T66	1		T55	1
all_values[9]	auto[1]	auto[0]	auto[1]	101	1			T155	3		T126	2		T55	2
all_values[9]	auto[1]	auto[1]	auto[1]	103	1			T155	1		T126	2		T66	2
all_values[10]	auto[0]	auto[0]	auto[0]	37	1			T126	1		T277	1		T264	1
all_values[10]	auto[0]	auto[0]	auto[1]	94	1			T155	2		T66	1		T55	3
all_values[10]	auto[0]	auto[1]	auto[0]	30	1			T55	1		T47	2		T57	2
all_values[10]	auto[0]	auto[1]	auto[1]	106	1			T155	1		T126	3		T55	1
all_values[10]	auto[1]	auto[0]	auto[1]	105	1			T155	2		T126	2		T66	3
all_values[10]	auto[1]	auto[1]	auto[1]	104	1			T155	3		T126	1		T55	1
all_values[11]	auto[0]	auto[0]	auto[0]	46	1			T155	1		T57	1		T264	1
all_values[11]	auto[0]	auto[0]	auto[1]	98	1			T155	2		T126	5		T66	1
all_values[11]	auto[0]	auto[1]	auto[0]	26	1			T155	1		T55	1		T264	1
all_values[11]	auto[0]	auto[1]	auto[1]	112	1			T155	1		T126	1		T66	1
all_values[11]	auto[1]	auto[0]	auto[1]	84	1			T126	1		T66	1		T55	1
all_values[11]	auto[1]	auto[1]	auto[1]	110	1			T155	3		T66	1		T55	3
all_values[12]	auto[0]	auto[0]	auto[0]	38	1			T277	1		T118	1		T282	1
all_values[12]	auto[0]	auto[0]	auto[1]	104	1			T155	1		T126	3		T66	1
all_values[12]	auto[0]	auto[1]	auto[0]	32	1			T66	2		T55	1		T116	1
all_values[12]	auto[0]	auto[1]	auto[1]	102	1			T155	2		T126	1		T55	3
all_values[12]	auto[1]	auto[0]	auto[1]	103	1			T155	1		T126	3		T66	1
all_values[12]	auto[1]	auto[1]	auto[1]	97	1			T155	4		T116	1		T264	3
all_values[13]	auto[0]	auto[0]	auto[0]	50	1			T116	1		T280	1		T279	2
all_values[13]	auto[0]	auto[0]	auto[1]	108	1			T155	2		T126	2		T66	3
all_values[13]	auto[0]	auto[1]	auto[0]	32	1			T57	2		T278	1		T282	3
all_values[13]	auto[0]	auto[1]	auto[1]	101	1			T155	4		T126	3		T55	1
all_values[13]	auto[1]	auto[0]	auto[1]	90	1			T55	3		T47	1		T57	1
all_values[13]	auto[1]	auto[1]	auto[1]	95	1			T155	2		T126	2		T66	1
all_values[14]	auto[0]	auto[0]	auto[0]	46	1			T57	1		T116	4		T277	2
all_values[14]	auto[0]	auto[0]	auto[1]	99	1			T155	2		T126	3		T66	2
all_values[14]	auto[0]	auto[1]	auto[0]	27	1			T155	1		T55	1		T47	4
all_values[14]	auto[0]	auto[1]	auto[1]	111	1			T155	2		T66	1		T55	1
all_values[14]	auto[1]	auto[0]	auto[1]	101	1			T155	1		T126	4		T55	2
all_values[14]	auto[1]	auto[1]	auto[1]	92	1			T155	2		T66	1		T55	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal