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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.87 96.57 89.80 97.22 69.64 93.55 98.44 90.84


Total test records in report: 1641
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T192 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1863394619 Jul 04 06:38:06 PM PDT 24 Jul 04 06:38:08 PM PDT 24 317430283 ps
T231 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2423651208 Jul 04 06:38:09 PM PDT 24 Jul 04 06:38:10 PM PDT 24 23030531 ps
T111 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3821468792 Jul 04 06:37:22 PM PDT 24 Jul 04 06:37:25 PM PDT 24 352599869 ps
T202 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.4013113300 Jul 04 06:38:11 PM PDT 24 Jul 04 06:38:13 PM PDT 24 1039078574 ps
T1535 /workspace/coverage/cover_reg_top/22.i2c_intr_test.1020026262 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:27 PM PDT 24 45036570 ps
T216 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2989110085 Jul 04 06:37:36 PM PDT 24 Jul 04 06:37:37 PM PDT 24 24959023 ps
T1536 /workspace/coverage/cover_reg_top/13.i2c_intr_test.3257122207 Jul 04 06:38:02 PM PDT 24 Jul 04 06:38:03 PM PDT 24 33460623 ps
T112 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.439384428 Jul 04 06:38:20 PM PDT 24 Jul 04 06:38:21 PM PDT 24 57875909 ps
T193 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2506915635 Jul 04 06:38:17 PM PDT 24 Jul 04 06:38:20 PM PDT 24 565278857 ps
T1537 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1703256162 Jul 04 06:37:55 PM PDT 24 Jul 04 06:37:56 PM PDT 24 22872490 ps
T203 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1555045247 Jul 04 06:37:36 PM PDT 24 Jul 04 06:37:38 PM PDT 24 71665907 ps
T113 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3486780101 Jul 04 06:37:53 PM PDT 24 Jul 04 06:37:54 PM PDT 24 334448579 ps
T1538 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2065411049 Jul 04 06:37:53 PM PDT 24 Jul 04 06:37:54 PM PDT 24 55377227 ps
T153 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2564337235 Jul 04 06:38:04 PM PDT 24 Jul 04 06:38:06 PM PDT 24 130045687 ps
T1539 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.459483650 Jul 04 06:37:47 PM PDT 24 Jul 04 06:37:48 PM PDT 24 39299605 ps
T204 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.10953381 Jul 04 06:37:29 PM PDT 24 Jul 04 06:37:32 PM PDT 24 145754959 ps
T1540 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2454835548 Jul 04 06:38:01 PM PDT 24 Jul 04 06:38:02 PM PDT 24 76286130 ps
T1541 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2219965732 Jul 04 06:37:21 PM PDT 24 Jul 04 06:37:27 PM PDT 24 522212996 ps
T1542 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.38576197 Jul 04 06:38:20 PM PDT 24 Jul 04 06:38:21 PM PDT 24 22677539 ps
T1543 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3348088295 Jul 04 06:38:23 PM PDT 24 Jul 04 06:38:25 PM PDT 24 383721564 ps
T1544 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1470460143 Jul 04 06:38:25 PM PDT 24 Jul 04 06:38:26 PM PDT 24 37543869 ps
T1545 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1906636195 Jul 04 06:38:04 PM PDT 24 Jul 04 06:38:05 PM PDT 24 44806577 ps
T210 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1956517903 Jul 04 06:38:12 PM PDT 24 Jul 04 06:38:14 PM PDT 24 143129529 ps
T1546 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.192701049 Jul 04 06:37:54 PM PDT 24 Jul 04 06:37:56 PM PDT 24 75396332 ps
T1547 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.226076993 Jul 04 06:37:50 PM PDT 24 Jul 04 06:37:52 PM PDT 24 124836756 ps
T1548 /workspace/coverage/cover_reg_top/10.i2c_intr_test.914445399 Jul 04 06:37:55 PM PDT 24 Jul 04 06:37:56 PM PDT 24 19746636 ps
T1549 /workspace/coverage/cover_reg_top/27.i2c_intr_test.963674631 Jul 04 06:38:24 PM PDT 24 Jul 04 06:38:25 PM PDT 24 19668247 ps
T1550 /workspace/coverage/cover_reg_top/4.i2c_intr_test.1870630396 Jul 04 06:37:46 PM PDT 24 Jul 04 06:37:47 PM PDT 24 21791090 ps
T1551 /workspace/coverage/cover_reg_top/28.i2c_intr_test.3356780696 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:27 PM PDT 24 18587898 ps
T1552 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1671488016 Jul 04 06:38:18 PM PDT 24 Jul 04 06:38:19 PM PDT 24 121947736 ps
T1553 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1118318933 Jul 04 06:37:22 PM PDT 24 Jul 04 06:37:23 PM PDT 24 16686443 ps
T1554 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1256459873 Jul 04 06:37:55 PM PDT 24 Jul 04 06:37:57 PM PDT 24 32604556 ps
T206 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2892510729 Jul 04 06:38:04 PM PDT 24 Jul 04 06:38:07 PM PDT 24 148504093 ps
T1555 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2205838450 Jul 04 06:37:48 PM PDT 24 Jul 04 06:37:49 PM PDT 24 17280438 ps
T1556 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.4196439410 Jul 04 06:38:02 PM PDT 24 Jul 04 06:38:03 PM PDT 24 22786029 ps
T1557 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1857110020 Jul 04 06:38:02 PM PDT 24 Jul 04 06:38:03 PM PDT 24 64830166 ps
T1558 /workspace/coverage/cover_reg_top/31.i2c_intr_test.1183499830 Jul 04 06:38:27 PM PDT 24 Jul 04 06:38:28 PM PDT 24 25256884 ps
T1559 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.509159087 Jul 04 06:37:48 PM PDT 24 Jul 04 06:37:53 PM PDT 24 113324442 ps
T1560 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1185092793 Jul 04 06:37:54 PM PDT 24 Jul 04 06:37:55 PM PDT 24 37760720 ps
T217 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.502928031 Jul 04 06:38:01 PM PDT 24 Jul 04 06:38:02 PM PDT 24 18799801 ps
T205 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.275496305 Jul 04 06:37:21 PM PDT 24 Jul 04 06:37:24 PM PDT 24 123892159 ps
T1561 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2315635857 Jul 04 06:37:22 PM PDT 24 Jul 04 06:37:24 PM PDT 24 31563237 ps
T196 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3597591354 Jul 04 06:37:38 PM PDT 24 Jul 04 06:37:40 PM PDT 24 122570851 ps
T1562 /workspace/coverage/cover_reg_top/26.i2c_intr_test.337200965 Jul 04 06:38:27 PM PDT 24 Jul 04 06:38:28 PM PDT 24 38602772 ps
T209 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2322213108 Jul 04 06:37:46 PM PDT 24 Jul 04 06:37:48 PM PDT 24 262790568 ps
T1563 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.656338840 Jul 04 06:37:49 PM PDT 24 Jul 04 06:37:50 PM PDT 24 22161726 ps
T208 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.321011722 Jul 04 06:38:19 PM PDT 24 Jul 04 06:38:21 PM PDT 24 248703536 ps
T1564 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2182048727 Jul 04 06:37:30 PM PDT 24 Jul 04 06:37:31 PM PDT 24 62618170 ps
T197 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.30610961 Jul 04 06:37:47 PM PDT 24 Jul 04 06:37:49 PM PDT 24 95047017 ps
T199 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2876500365 Jul 04 06:38:13 PM PDT 24 Jul 04 06:38:16 PM PDT 24 480967315 ps
T1565 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3566282724 Jul 04 06:38:13 PM PDT 24 Jul 04 06:38:14 PM PDT 24 107793427 ps
T1566 /workspace/coverage/cover_reg_top/48.i2c_intr_test.2153815072 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:27 PM PDT 24 30497753 ps
T198 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2914649246 Jul 04 06:37:22 PM PDT 24 Jul 04 06:37:24 PM PDT 24 83621571 ps
T1567 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4030241189 Jul 04 06:37:58 PM PDT 24 Jul 04 06:37:59 PM PDT 24 82993038 ps
T1568 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3988120326 Jul 04 06:37:56 PM PDT 24 Jul 04 06:37:56 PM PDT 24 59899910 ps
T1569 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1767601210 Jul 04 06:37:53 PM PDT 24 Jul 04 06:37:55 PM PDT 24 36025861 ps
T1570 /workspace/coverage/cover_reg_top/1.i2c_intr_test.2070472190 Jul 04 06:37:21 PM PDT 24 Jul 04 06:37:22 PM PDT 24 24307580 ps
T218 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1936662782 Jul 04 06:37:54 PM PDT 24 Jul 04 06:37:55 PM PDT 24 28844125 ps
T1571 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.296238792 Jul 04 06:37:21 PM PDT 24 Jul 04 06:37:22 PM PDT 24 65011407 ps
T1572 /workspace/coverage/cover_reg_top/8.i2c_intr_test.1823311220 Jul 04 06:37:54 PM PDT 24 Jul 04 06:37:55 PM PDT 24 27459457 ps
T1573 /workspace/coverage/cover_reg_top/23.i2c_intr_test.2779351981 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:27 PM PDT 24 43832927 ps
T219 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1959635348 Jul 04 06:37:47 PM PDT 24 Jul 04 06:37:48 PM PDT 24 46897073 ps
T1574 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3626943666 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:27 PM PDT 24 57012995 ps
T1575 /workspace/coverage/cover_reg_top/49.i2c_intr_test.581796707 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:27 PM PDT 24 32313607 ps
T1576 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3046603515 Jul 04 06:37:29 PM PDT 24 Jul 04 06:37:29 PM PDT 24 32043550 ps
T1577 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1415074568 Jul 04 06:38:03 PM PDT 24 Jul 04 06:38:04 PM PDT 24 40290566 ps
T1578 /workspace/coverage/cover_reg_top/45.i2c_intr_test.656057448 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:27 PM PDT 24 47743110 ps
T1579 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3440029539 Jul 04 06:38:03 PM PDT 24 Jul 04 06:38:04 PM PDT 24 31337865 ps
T1580 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.310732718 Jul 04 06:38:18 PM PDT 24 Jul 04 06:38:19 PM PDT 24 144774692 ps
T1581 /workspace/coverage/cover_reg_top/24.i2c_intr_test.2095906668 Jul 04 06:38:24 PM PDT 24 Jul 04 06:38:25 PM PDT 24 17126925 ps
T1582 /workspace/coverage/cover_reg_top/16.i2c_intr_test.3176761884 Jul 04 06:38:13 PM PDT 24 Jul 04 06:38:14 PM PDT 24 41800417 ps
T1583 /workspace/coverage/cover_reg_top/32.i2c_intr_test.4063937535 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:28 PM PDT 24 24841352 ps
T1584 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.4122259263 Jul 04 06:38:02 PM PDT 24 Jul 04 06:38:03 PM PDT 24 30180877 ps
T1585 /workspace/coverage/cover_reg_top/44.i2c_intr_test.2199336916 Jul 04 06:38:25 PM PDT 24 Jul 04 06:38:25 PM PDT 24 14685880 ps
T1586 /workspace/coverage/cover_reg_top/34.i2c_intr_test.2914479964 Jul 04 06:38:25 PM PDT 24 Jul 04 06:38:26 PM PDT 24 17430217 ps
T220 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1441927558 Jul 04 06:37:25 PM PDT 24 Jul 04 06:37:26 PM PDT 24 41892563 ps
T1587 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3000565314 Jul 04 06:37:54 PM PDT 24 Jul 04 06:37:55 PM PDT 24 99995721 ps
T1588 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3217435948 Jul 04 06:37:36 PM PDT 24 Jul 04 06:37:39 PM PDT 24 381484598 ps
T1589 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2227569827 Jul 04 06:37:53 PM PDT 24 Jul 04 06:37:55 PM PDT 24 139439379 ps
T1590 /workspace/coverage/cover_reg_top/12.i2c_intr_test.2736314890 Jul 04 06:38:01 PM PDT 24 Jul 04 06:38:02 PM PDT 24 23036130 ps
T1591 /workspace/coverage/cover_reg_top/3.i2c_intr_test.502633220 Jul 04 06:37:37 PM PDT 24 Jul 04 06:37:38 PM PDT 24 19058506 ps
T207 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1135796376 Jul 04 06:37:54 PM PDT 24 Jul 04 06:37:57 PM PDT 24 144471043 ps
T222 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1070721609 Jul 04 06:38:11 PM PDT 24 Jul 04 06:38:12 PM PDT 24 18853990 ps
T1592 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1920283931 Jul 04 06:37:37 PM PDT 24 Jul 04 06:37:38 PM PDT 24 19280706 ps
T221 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3330897764 Jul 04 06:37:28 PM PDT 24 Jul 04 06:37:30 PM PDT 24 290573869 ps
T223 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2786639950 Jul 04 06:38:03 PM PDT 24 Jul 04 06:38:04 PM PDT 24 18583993 ps
T1593 /workspace/coverage/cover_reg_top/41.i2c_intr_test.1004891916 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:27 PM PDT 24 51694885 ps
T1594 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1076525221 Jul 04 06:37:47 PM PDT 24 Jul 04 06:37:48 PM PDT 24 140224400 ps
T1595 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2778307448 Jul 04 06:37:38 PM PDT 24 Jul 04 06:37:39 PM PDT 24 72691332 ps
T1596 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3311544258 Jul 04 06:37:47 PM PDT 24 Jul 04 06:37:49 PM PDT 24 34131585 ps
T1597 /workspace/coverage/cover_reg_top/33.i2c_intr_test.1735733054 Jul 04 06:38:25 PM PDT 24 Jul 04 06:38:26 PM PDT 24 24653358 ps
T1598 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3570618752 Jul 04 06:37:50 PM PDT 24 Jul 04 06:37:53 PM PDT 24 287552946 ps
T1599 /workspace/coverage/cover_reg_top/46.i2c_intr_test.2696827109 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:27 PM PDT 24 18072266 ps
T1600 /workspace/coverage/cover_reg_top/43.i2c_intr_test.3728369199 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:28 PM PDT 24 20023330 ps
T1601 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3639975571 Jul 04 06:37:54 PM PDT 24 Jul 04 06:37:55 PM PDT 24 72862799 ps
T1602 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1418522323 Jul 04 06:38:29 PM PDT 24 Jul 04 06:38:30 PM PDT 24 23058519 ps
T1603 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4011926819 Jul 04 06:38:20 PM PDT 24 Jul 04 06:38:21 PM PDT 24 28400359 ps
T1604 /workspace/coverage/cover_reg_top/36.i2c_intr_test.3231764425 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:27 PM PDT 24 118078847 ps
T1605 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.582937484 Jul 04 06:38:24 PM PDT 24 Jul 04 06:38:26 PM PDT 24 92219087 ps
T1606 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1644376456 Jul 04 06:38:18 PM PDT 24 Jul 04 06:38:20 PM PDT 24 136184731 ps
T1607 /workspace/coverage/cover_reg_top/19.i2c_intr_test.1003213682 Jul 04 06:38:18 PM PDT 24 Jul 04 06:38:19 PM PDT 24 26309779 ps
T1608 /workspace/coverage/cover_reg_top/17.i2c_intr_test.3744371003 Jul 04 06:38:18 PM PDT 24 Jul 04 06:38:18 PM PDT 24 21133050 ps
T1609 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1211756667 Jul 04 06:37:46 PM PDT 24 Jul 04 06:37:48 PM PDT 24 25888889 ps
T1610 /workspace/coverage/cover_reg_top/47.i2c_intr_test.3458834759 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:28 PM PDT 24 20745902 ps
T1611 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2310974065 Jul 04 06:38:20 PM PDT 24 Jul 04 06:38:21 PM PDT 24 81137200 ps
T1612 /workspace/coverage/cover_reg_top/18.i2c_intr_test.3333991783 Jul 04 06:38:18 PM PDT 24 Jul 04 06:38:19 PM PDT 24 42466392 ps
T1613 /workspace/coverage/cover_reg_top/9.i2c_intr_test.2753791561 Jul 04 06:37:54 PM PDT 24 Jul 04 06:37:54 PM PDT 24 17137308 ps
T1614 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1553416750 Jul 04 06:37:23 PM PDT 24 Jul 04 06:37:25 PM PDT 24 341193575 ps
T1615 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1917996273 Jul 04 06:37:54 PM PDT 24 Jul 04 06:37:57 PM PDT 24 131324032 ps
T1616 /workspace/coverage/cover_reg_top/11.i2c_intr_test.3379798846 Jul 04 06:38:02 PM PDT 24 Jul 04 06:38:02 PM PDT 24 80088732 ps
T1617 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1709664004 Jul 04 06:37:50 PM PDT 24 Jul 04 06:37:51 PM PDT 24 102952314 ps
T1618 /workspace/coverage/cover_reg_top/6.i2c_intr_test.3001229929 Jul 04 06:37:46 PM PDT 24 Jul 04 06:37:47 PM PDT 24 51065908 ps
T224 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.694978248 Jul 04 06:37:22 PM PDT 24 Jul 04 06:37:23 PM PDT 24 25116761 ps
T1619 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1455122469 Jul 04 06:38:01 PM PDT 24 Jul 04 06:38:03 PM PDT 24 49529840 ps
T1620 /workspace/coverage/cover_reg_top/29.i2c_intr_test.1515978653 Jul 04 06:38:26 PM PDT 24 Jul 04 06:38:26 PM PDT 24 50898406 ps
T225 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1263847354 Jul 04 06:38:02 PM PDT 24 Jul 04 06:38:03 PM PDT 24 24795974 ps
T1621 /workspace/coverage/cover_reg_top/40.i2c_intr_test.256870171 Jul 04 06:38:27 PM PDT 24 Jul 04 06:38:28 PM PDT 24 21279524 ps
T1622 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.228628848 Jul 04 06:37:55 PM PDT 24 Jul 04 06:37:56 PM PDT 24 21235016 ps
T1623 /workspace/coverage/cover_reg_top/21.i2c_intr_test.3968752698 Jul 04 06:38:29 PM PDT 24 Jul 04 06:38:30 PM PDT 24 17514732 ps
T1624 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2611823989 Jul 04 06:38:11 PM PDT 24 Jul 04 06:38:12 PM PDT 24 27808972 ps
T200 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.576562072 Jul 04 06:37:46 PM PDT 24 Jul 04 06:37:48 PM PDT 24 174234073 ps
T1625 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2452359114 Jul 04 06:38:06 PM PDT 24 Jul 04 06:38:08 PM PDT 24 388360842 ps
T1626 /workspace/coverage/cover_reg_top/39.i2c_intr_test.293488326 Jul 04 06:38:29 PM PDT 24 Jul 04 06:38:30 PM PDT 24 51592765 ps
T201 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.506518194 Jul 04 06:37:46 PM PDT 24 Jul 04 06:37:48 PM PDT 24 171353910 ps
T227 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.4261497254 Jul 04 06:37:47 PM PDT 24 Jul 04 06:37:48 PM PDT 24 50782154 ps
T1627 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3836534675 Jul 04 06:38:01 PM PDT 24 Jul 04 06:38:02 PM PDT 24 17145878 ps
T1628 /workspace/coverage/cover_reg_top/25.i2c_intr_test.491787852 Jul 04 06:38:25 PM PDT 24 Jul 04 06:38:26 PM PDT 24 36906492 ps
T1629 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.4242468485 Jul 04 06:37:48 PM PDT 24 Jul 04 06:37:49 PM PDT 24 140797833 ps
T1630 /workspace/coverage/cover_reg_top/7.i2c_intr_test.723124011 Jul 04 06:37:47 PM PDT 24 Jul 04 06:37:48 PM PDT 24 18658198 ps
T1631 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1966113569 Jul 04 06:38:27 PM PDT 24 Jul 04 06:38:28 PM PDT 24 19892590 ps
T1632 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2943982428 Jul 04 06:37:22 PM PDT 24 Jul 04 06:37:24 PM PDT 24 79653847 ps
T1633 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.822561689 Jul 04 06:37:46 PM PDT 24 Jul 04 06:37:47 PM PDT 24 28450469 ps
T226 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3919793030 Jul 04 06:38:18 PM PDT 24 Jul 04 06:38:19 PM PDT 24 29453289 ps
T1634 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1802473946 Jul 04 06:38:18 PM PDT 24 Jul 04 06:38:19 PM PDT 24 66263690 ps
T1635 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3304516673 Jul 04 06:37:47 PM PDT 24 Jul 04 06:37:49 PM PDT 24 274743775 ps
T1636 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1658438699 Jul 04 06:37:54 PM PDT 24 Jul 04 06:37:56 PM PDT 24 87557936 ps
T1637 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3114573298 Jul 04 06:38:18 PM PDT 24 Jul 04 06:38:19 PM PDT 24 157157651 ps
T1638 /workspace/coverage/cover_reg_top/20.i2c_intr_test.533428849 Jul 04 06:38:27 PM PDT 24 Jul 04 06:38:28 PM PDT 24 49811536 ps
T1639 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.751313499 Jul 04 06:38:18 PM PDT 24 Jul 04 06:38:20 PM PDT 24 55499499 ps
T1640 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1515886414 Jul 04 06:38:11 PM PDT 24 Jul 04 06:38:12 PM PDT 24 45119404 ps
T1641 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.930966069 Jul 04 06:37:47 PM PDT 24 Jul 04 06:37:49 PM PDT 24 361762754 ps

Test location /workspace/coverage/default/14.i2c_target_hrst.4104056980
Short name T7
Test name
Test status
Simulation time 1066241613 ps
CPU time 2.56 seconds
Started Jul 04 04:53:47 PM PDT 24
Finished Jul 04 04:53:50 PM PDT 24
Peak memory 204700 kb
Host smart-2f1a4ecb-911e-4381-ba86-ffcdb4387b9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104056980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.4104056980
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.116648678
Short name T41
Test name
Test status
Simulation time 3006239082 ps
CPU time 44.59 seconds
Started Jul 04 04:57:13 PM PDT 24
Finished Jul 04 04:57:58 PM PDT 24
Peak memory 593396 kb
Host smart-da858420-473b-499b-9a60-7a3a14c8d04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116648678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.116648678
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2459494853
Short name T12
Test name
Test status
Simulation time 34715080474 ps
CPU time 9.66 seconds
Started Jul 04 04:52:01 PM PDT 24
Finished Jul 04 04:52:10 PM PDT 24
Peak memory 213508 kb
Host smart-83016317-f215-48f2-989f-4be96ef85793
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459494853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2459494853
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.3120613198
Short name T155
Test name
Test status
Simulation time 39284417459 ps
CPU time 919.81 seconds
Started Jul 04 04:52:44 PM PDT 24
Finished Jul 04 05:08:04 PM PDT 24
Peak memory 1861652 kb
Host smart-57c147cf-f363-4b5f-8ae6-cd045d570cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120613198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.3120613198
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3821468792
Short name T111
Test name
Test status
Simulation time 352599869 ps
CPU time 2.04 seconds
Started Jul 04 06:37:22 PM PDT 24
Finished Jul 04 06:37:25 PM PDT 24
Peak memory 204632 kb
Host smart-706dd7da-7b0e-4909-93f5-d6bcc55dd12a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821468792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3821468792
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.2772903974
Short name T126
Test name
Test status
Simulation time 63784437484 ps
CPU time 337.97 seconds
Started Jul 04 04:59:07 PM PDT 24
Finished Jul 04 05:04:46 PM PDT 24
Peak memory 884732 kb
Host smart-18fe6635-a37b-453a-a165-df5c326ed8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772903974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2772903974
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3974173389
Short name T4
Test name
Test status
Simulation time 38174694 ps
CPU time 0.87 seconds
Started Jul 04 04:52:24 PM PDT 24
Finished Jul 04 04:52:25 PM PDT 24
Peak memory 222024 kb
Host smart-72b15b99-8eae-4410-ab6b-e769c402b238
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974173389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3974173389
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.1480793950
Short name T8
Test name
Test status
Simulation time 19204215189 ps
CPU time 36.44 seconds
Started Jul 04 04:55:03 PM PDT 24
Finished Jul 04 04:55:40 PM PDT 24
Peak memory 705776 kb
Host smart-f214c018-006b-41c5-80af-ab10e37494c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480793950 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.1480793950
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_host_override.2452699087
Short name T145
Test name
Test status
Simulation time 30595750 ps
CPU time 0.65 seconds
Started Jul 04 04:56:26 PM PDT 24
Finished Jul 04 04:56:27 PM PDT 24
Peak memory 204408 kb
Host smart-72680dbf-1496-45c9-8c2d-1480b8742bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452699087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.2452699087
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.643527843
Short name T44
Test name
Test status
Simulation time 696040287 ps
CPU time 28.39 seconds
Started Jul 04 04:57:02 PM PDT 24
Finished Jul 04 04:57:31 PM PDT 24
Peak memory 204808 kb
Host smart-147a923b-c682-49e9-b093-c206bbd5a202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643527843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.643527843
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.3188182069
Short name T57
Test name
Test status
Simulation time 80751222040 ps
CPU time 1432.63 seconds
Started Jul 04 04:53:34 PM PDT 24
Finished Jul 04 05:17:27 PM PDT 24
Peak memory 4253588 kb
Host smart-64dc90a7-927c-454e-b1c1-ad5fb1ac6de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188182069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.3188182069
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1026018119
Short name T105
Test name
Test status
Simulation time 191698018 ps
CPU time 1.31 seconds
Started Jul 04 06:37:46 PM PDT 24
Finished Jul 04 06:37:47 PM PDT 24
Peak memory 204580 kb
Host smart-8b2f36e0-eef4-4ca4-9068-cd35a153f173
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026018119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1026018119
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.4078954302
Short name T11
Test name
Test status
Simulation time 536663843 ps
CPU time 1.56 seconds
Started Jul 04 04:55:37 PM PDT 24
Finished Jul 04 04:55:39 PM PDT 24
Peak memory 209736 kb
Host smart-1edb9631-1d60-4a97-8f22-7efd72cd1727
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078954302 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.4078954302
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.1771772951
Short name T379
Test name
Test status
Simulation time 221025343 ps
CPU time 3.94 seconds
Started Jul 04 04:55:01 PM PDT 24
Finished Jul 04 04:55:05 PM PDT 24
Peak memory 204688 kb
Host smart-db71e849-b28c-4995-9ee5-f85ff2714274
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771772951 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.1771772951
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3708008776
Short name T31
Test name
Test status
Simulation time 163546278 ps
CPU time 1.53 seconds
Started Jul 04 04:58:00 PM PDT 24
Finished Jul 04 04:58:01 PM PDT 24
Peak memory 221140 kb
Host smart-5f27fd13-0bf2-4379-bd83-a6483a733f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708008776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3708008776
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1863394619
Short name T192
Test name
Test status
Simulation time 317430283 ps
CPU time 2.22 seconds
Started Jul 04 06:38:06 PM PDT 24
Finished Jul 04 06:38:08 PM PDT 24
Peak memory 204632 kb
Host smart-a3b0a583-0586-4f4a-a85b-fe2f4c93e312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863394619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1863394619
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.2905781025
Short name T25
Test name
Test status
Simulation time 4886392782 ps
CPU time 6.16 seconds
Started Jul 04 04:53:32 PM PDT 24
Finished Jul 04 04:53:38 PM PDT 24
Peak memory 213076 kb
Host smart-ebed5c3a-6ffd-4ca8-a1f3-73c5a91e9de6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905781025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.2905781025
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.455524828
Short name T61
Test name
Test status
Simulation time 539792684 ps
CPU time 1.01 seconds
Started Jul 04 04:52:23 PM PDT 24
Finished Jul 04 04:52:24 PM PDT 24
Peak memory 204324 kb
Host smart-e9f544ed-2c00-433b-8f4d-1220632497cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455524828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt
.455524828
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.915543877
Short name T20
Test name
Test status
Simulation time 1590222828 ps
CPU time 4.64 seconds
Started Jul 04 04:58:04 PM PDT 24
Finished Jul 04 04:58:08 PM PDT 24
Peak memory 212952 kb
Host smart-bf4cf187-4794-4ae7-842d-156decab29b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915543877 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.915543877
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.1239927804
Short name T103
Test name
Test status
Simulation time 11420955622 ps
CPU time 44.53 seconds
Started Jul 04 04:55:25 PM PDT 24
Finished Jul 04 04:56:10 PM PDT 24
Peak memory 204812 kb
Host smart-9493400c-01d8-4880-95fb-eb25d1d8011d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239927804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.1239927804
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.1011929211
Short name T69
Test name
Test status
Simulation time 183851642 ps
CPU time 2.42 seconds
Started Jul 04 04:52:30 PM PDT 24
Finished Jul 04 04:52:32 PM PDT 24
Peak memory 212956 kb
Host smart-8c31ba2d-3d4a-4a6b-a813-fed2dbf5e503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011929211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.1011929211
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.3827703541
Short name T66
Test name
Test status
Simulation time 13910081818 ps
CPU time 743.45 seconds
Started Jul 04 04:52:35 PM PDT 24
Finished Jul 04 05:04:59 PM PDT 24
Peak memory 1694376 kb
Host smart-d95469c3-76ab-4760-b51f-ca3e69d2d0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827703541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.3827703541
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.2483597368
Short name T67
Test name
Test status
Simulation time 15995830763 ps
CPU time 694.62 seconds
Started Jul 04 04:57:37 PM PDT 24
Finished Jul 04 05:09:12 PM PDT 24
Peak memory 2456896 kb
Host smart-1d6bd175-1b1d-4923-9522-55efb754fe4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483597368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.2483597368
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_alert_test.2462519959
Short name T336
Test name
Test status
Simulation time 16756921 ps
CPU time 0.64 seconds
Started Jul 04 04:52:10 PM PDT 24
Finished Jul 04 04:52:11 PM PDT 24
Peak memory 204356 kb
Host smart-8f2c6fcc-2f2a-4611-b479-c57d691405c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462519959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2462519959
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.2868896877
Short name T118
Test name
Test status
Simulation time 43918013203 ps
CPU time 402.82 seconds
Started Jul 04 04:56:46 PM PDT 24
Finished Jul 04 05:03:30 PM PDT 24
Peak memory 1471452 kb
Host smart-dc2db535-c8f7-4809-b21e-51bd95c0edb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868896877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.2868896877
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.3881085652
Short name T73
Test name
Test status
Simulation time 115648397 ps
CPU time 3.57 seconds
Started Jul 04 04:51:59 PM PDT 24
Finished Jul 04 04:52:03 PM PDT 24
Peak memory 204700 kb
Host smart-74ff548b-14d6-4567-a566-ca8590d7e9ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881085652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
3881085652
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3911872030
Short name T6
Test name
Test status
Simulation time 8368655759 ps
CPU time 288.32 seconds
Started Jul 04 04:56:05 PM PDT 24
Finished Jul 04 05:00:54 PM PDT 24
Peak memory 1229556 kb
Host smart-57691656-3736-46b3-a055-38967bff2dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911872030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3911872030
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.2117783819
Short name T33
Test name
Test status
Simulation time 4440140493 ps
CPU time 26 seconds
Started Jul 04 04:57:39 PM PDT 24
Finished Jul 04 04:58:05 PM PDT 24
Peak memory 328984 kb
Host smart-45900d42-eb76-4101-93e8-1e4ffbe68072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117783819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.2117783819
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.3570384111
Short name T133
Test name
Test status
Simulation time 49934040543 ps
CPU time 115.77 seconds
Started Jul 04 04:54:43 PM PDT 24
Finished Jul 04 04:56:39 PM PDT 24
Peak memory 831404 kb
Host smart-fcd7a2ea-174e-45b5-98b8-8296ebc5a00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570384111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.3570384111
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.2038899654
Short name T268
Test name
Test status
Simulation time 18787304099 ps
CPU time 2734.36 seconds
Started Jul 04 04:55:58 PM PDT 24
Finished Jul 04 05:41:33 PM PDT 24
Peak memory 4144944 kb
Host smart-a4fa4363-50af-4450-a76b-638560302cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038899654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.2038899654
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3348088295
Short name T1543
Test name
Test status
Simulation time 383721564 ps
CPU time 2.13 seconds
Started Jul 04 06:38:23 PM PDT 24
Finished Jul 04 06:38:25 PM PDT 24
Peak memory 212836 kb
Host smart-20bc4b1b-1d71-4bd9-80fd-e624d5d71327
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348088295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3348088295
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.823926434
Short name T54
Test name
Test status
Simulation time 15407820631 ps
CPU time 671.78 seconds
Started Jul 04 04:56:22 PM PDT 24
Finished Jul 04 05:07:34 PM PDT 24
Peak memory 3211056 kb
Host smart-9f52d830-c098-4457-ad93-df8ff226a39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823926434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.823926434
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1295415995
Short name T228
Test name
Test status
Simulation time 54252949 ps
CPU time 0.86 seconds
Started Jul 04 06:37:24 PM PDT 24
Finished Jul 04 06:37:25 PM PDT 24
Peak memory 204468 kb
Host smart-8216a91e-8393-4845-b5ce-cb702ba5aa5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295415995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1295415995
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.4158211713
Short name T143
Test name
Test status
Simulation time 333328865 ps
CPU time 1.16 seconds
Started Jul 04 04:54:28 PM PDT 24
Finished Jul 04 04:54:29 PM PDT 24
Peak memory 204420 kb
Host smart-3021305f-8aae-453a-a9bb-d3ad2c8aa9be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158211713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.4158211713
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.3772441045
Short name T248
Test name
Test status
Simulation time 651884632 ps
CPU time 2.59 seconds
Started Jul 04 04:55:35 PM PDT 24
Finished Jul 04 04:55:38 PM PDT 24
Peak memory 204832 kb
Host smart-71eb0ae4-70a5-455e-aca1-657ef589ee8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772441045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.3772441045
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.1851334314
Short name T234
Test name
Test status
Simulation time 139356219 ps
CPU time 0.99 seconds
Started Jul 04 04:55:51 PM PDT 24
Finished Jul 04 04:55:52 PM PDT 24
Peak memory 212696 kb
Host smart-5516cb24-3db0-435f-9ee7-f3a8ebb5706a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851334314 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.1851334314
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.2289839070
Short name T72
Test name
Test status
Simulation time 21908559836 ps
CPU time 31.52 seconds
Started Jul 04 04:55:03 PM PDT 24
Finished Jul 04 04:55:35 PM PDT 24
Peak memory 361116 kb
Host smart-c778c193-5bf1-4224-87f9-d54f9e053d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289839070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.2289839070
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.690971792
Short name T83
Test name
Test status
Simulation time 4339949959 ps
CPU time 56.25 seconds
Started Jul 04 04:53:48 PM PDT 24
Finished Jul 04 04:54:44 PM PDT 24
Peak memory 367720 kb
Host smart-43f9aa28-d1ec-410d-9344-9c034a87f3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690971792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.690971792
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.10953381
Short name T204
Test name
Test status
Simulation time 145754959 ps
CPU time 2.28 seconds
Started Jul 04 06:37:29 PM PDT 24
Finished Jul 04 06:37:32 PM PDT 24
Peak memory 204512 kb
Host smart-66de14fb-d87a-4416-b9cb-af96572b187c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10953381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.10953381
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.2747629685
Short name T34
Test name
Test status
Simulation time 7307663801 ps
CPU time 30.92 seconds
Started Jul 04 04:57:13 PM PDT 24
Finished Jul 04 04:57:44 PM PDT 24
Peak memory 375728 kb
Host smart-cd23d1f0-d6d9-404b-88f8-ea31ba84f80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747629685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.2747629685
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.506518194
Short name T201
Test name
Test status
Simulation time 171353910 ps
CPU time 2.19 seconds
Started Jul 04 06:37:46 PM PDT 24
Finished Jul 04 06:37:48 PM PDT 24
Peak memory 204476 kb
Host smart-d496ccb0-5aef-42d6-b2ae-9f7d22830650
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506518194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.506518194
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.1244699482
Short name T158
Test name
Test status
Simulation time 261988382 ps
CPU time 1.52 seconds
Started Jul 04 04:54:54 PM PDT 24
Finished Jul 04 04:54:56 PM PDT 24
Peak memory 204720 kb
Host smart-d75e3ad4-5965-4274-9e68-b11f9cd5716f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244699482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.1244699482
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.294033669
Short name T1047
Test name
Test status
Simulation time 2786264977 ps
CPU time 7.34 seconds
Started Jul 04 04:52:10 PM PDT 24
Finished Jul 04 04:52:18 PM PDT 24
Peak memory 212984 kb
Host smart-5881f202-4146-4c1c-8663-563cf377e08b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294033669 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_timeout.294033669
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.4177203783
Short name T1197
Test name
Test status
Simulation time 1518829526 ps
CPU time 2.66 seconds
Started Jul 04 04:53:37 PM PDT 24
Finished Jul 04 04:53:40 PM PDT 24
Peak memory 204684 kb
Host smart-83d5652e-7a79-4a0f-b712-876269b05212
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177203783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.4177203783
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.2988932568
Short name T531
Test name
Test status
Simulation time 9899197011 ps
CPU time 3.86 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:40 PM PDT 24
Peak memory 204872 kb
Host smart-47d6e9c6-07c3-49ea-8b3b-c510d2751856
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988932568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.2988932568
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.583071537
Short name T677
Test name
Test status
Simulation time 573661490 ps
CPU time 7.2 seconds
Started Jul 04 04:53:56 PM PDT 24
Finished Jul 04 04:54:03 PM PDT 24
Peak memory 204740 kb
Host smart-3e538bdd-42e4-48a0-b145-ac1574a220fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583071537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.583071537
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.4232967422
Short name T285
Test name
Test status
Simulation time 628274752 ps
CPU time 1.44 seconds
Started Jul 04 04:53:59 PM PDT 24
Finished Jul 04 04:54:01 PM PDT 24
Peak memory 206072 kb
Host smart-83c39143-3ea1-497d-bda0-c68001b6e71e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232967422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.4232967422
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.3426656795
Short name T239
Test name
Test status
Simulation time 274737456 ps
CPU time 2.57 seconds
Started Jul 04 04:54:16 PM PDT 24
Finished Jul 04 04:54:19 PM PDT 24
Peak memory 204728 kb
Host smart-9a338a51-1166-4b51-8016-019b6c42f76d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426656795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.3426656795
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.588129460
Short name T1478
Test name
Test status
Simulation time 1867603875 ps
CPU time 17.05 seconds
Started Jul 04 04:54:07 PM PDT 24
Finished Jul 04 04:54:25 PM PDT 24
Peak memory 216736 kb
Host smart-9212128f-ed36-454e-b36e-278ec8af56ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588129460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.588129460
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1135796376
Short name T207
Test name
Test status
Simulation time 144471043 ps
CPU time 2.15 seconds
Started Jul 04 06:37:54 PM PDT 24
Finished Jul 04 06:37:57 PM PDT 24
Peak memory 204604 kb
Host smart-189508ff-36f6-4989-95b4-ed446653d08c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135796376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1135796376
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4126204076
Short name T185
Test name
Test status
Simulation time 289858831 ps
CPU time 2.13 seconds
Started Jul 04 06:38:04 PM PDT 24
Finished Jul 04 06:38:06 PM PDT 24
Peak memory 204600 kb
Host smart-994dce4a-fd9a-423c-90b9-c71ec78e62e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126204076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.4126204076
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1553416750
Short name T1614
Test name
Test status
Simulation time 341193575 ps
CPU time 1.83 seconds
Started Jul 04 06:37:23 PM PDT 24
Finished Jul 04 06:37:25 PM PDT 24
Peak memory 204644 kb
Host smart-a6b57d48-22ba-419c-adb8-1f725e462403
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553416750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1553416750
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1508082242
Short name T1531
Test name
Test status
Simulation time 1655959178 ps
CPU time 4.71 seconds
Started Jul 04 06:37:21 PM PDT 24
Finished Jul 04 06:37:25 PM PDT 24
Peak memory 204548 kb
Host smart-b1989ec2-1f2f-47c9-8b52-08cebcb3f121
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508082242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1508082242
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1441927558
Short name T220
Test name
Test status
Simulation time 41892563 ps
CPU time 0.77 seconds
Started Jul 04 06:37:25 PM PDT 24
Finished Jul 04 06:37:26 PM PDT 24
Peak memory 204428 kb
Host smart-a9cc6995-3098-43d7-a037-16fb40e05af1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441927558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1441927558
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2315635857
Short name T1561
Test name
Test status
Simulation time 31563237 ps
CPU time 1.33 seconds
Started Jul 04 06:37:22 PM PDT 24
Finished Jul 04 06:37:24 PM PDT 24
Peak memory 204632 kb
Host smart-6bb7bb73-e403-443b-93a2-19951d9c7331
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315635857 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2315635857
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.694978248
Short name T224
Test name
Test status
Simulation time 25116761 ps
CPU time 0.85 seconds
Started Jul 04 06:37:22 PM PDT 24
Finished Jul 04 06:37:23 PM PDT 24
Peak memory 204452 kb
Host smart-0f205bb9-6d71-4cda-a532-540686eb71bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694978248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.694978248
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1118318933
Short name T1553
Test name
Test status
Simulation time 16686443 ps
CPU time 0.67 seconds
Started Jul 04 06:37:22 PM PDT 24
Finished Jul 04 06:37:23 PM PDT 24
Peak memory 204328 kb
Host smart-0e9ff27d-2c54-4aad-ae86-c65c4304a24c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118318933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1118318933
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2943982428
Short name T1632
Test name
Test status
Simulation time 79653847 ps
CPU time 1.26 seconds
Started Jul 04 06:37:22 PM PDT 24
Finished Jul 04 06:37:24 PM PDT 24
Peak memory 204624 kb
Host smart-6f170612-9f77-4969-b94d-38fd0a2eab27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943982428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2943982428
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.275496305
Short name T205
Test name
Test status
Simulation time 123892159 ps
CPU time 2.31 seconds
Started Jul 04 06:37:21 PM PDT 24
Finished Jul 04 06:37:24 PM PDT 24
Peak memory 204600 kb
Host smart-83a9be52-85e7-43b8-ae35-fd896dcd99ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275496305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.275496305
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3330897764
Short name T221
Test name
Test status
Simulation time 290573869 ps
CPU time 2.04 seconds
Started Jul 04 06:37:28 PM PDT 24
Finished Jul 04 06:37:30 PM PDT 24
Peak memory 204516 kb
Host smart-f97ca9d5-a7e0-4294-8e15-12f125a49630
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330897764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3330897764
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2219965732
Short name T1541
Test name
Test status
Simulation time 522212996 ps
CPU time 5.23 seconds
Started Jul 04 06:37:21 PM PDT 24
Finished Jul 04 06:37:27 PM PDT 24
Peak memory 204580 kb
Host smart-c18172cd-165d-4ff5-ab9f-a0d26801ea91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219965732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2219965732
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3485025838
Short name T106
Test name
Test status
Simulation time 32829352 ps
CPU time 0.75 seconds
Started Jul 04 06:37:21 PM PDT 24
Finished Jul 04 06:37:22 PM PDT 24
Peak memory 204464 kb
Host smart-c726402b-2437-4f45-b8ad-a7ba065429e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485025838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3485025838
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3046603515
Short name T1576
Test name
Test status
Simulation time 32043550 ps
CPU time 0.8 seconds
Started Jul 04 06:37:29 PM PDT 24
Finished Jul 04 06:37:29 PM PDT 24
Peak memory 204492 kb
Host smart-71403a80-f3a9-48f3-957a-7d3faf8808e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046603515 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3046603515
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.296238792
Short name T1571
Test name
Test status
Simulation time 65011407 ps
CPU time 0.75 seconds
Started Jul 04 06:37:21 PM PDT 24
Finished Jul 04 06:37:22 PM PDT 24
Peak memory 204480 kb
Host smart-40ce7e90-5c8e-48cd-b1d6-397fae3e65c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296238792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.296238792
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.2070472190
Short name T1570
Test name
Test status
Simulation time 24307580 ps
CPU time 0.67 seconds
Started Jul 04 06:37:21 PM PDT 24
Finished Jul 04 06:37:22 PM PDT 24
Peak memory 204324 kb
Host smart-fa22c185-b59e-43dc-8426-6407db56368b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070472190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2070472190
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2182048727
Short name T1564
Test name
Test status
Simulation time 62618170 ps
CPU time 0.89 seconds
Started Jul 04 06:37:30 PM PDT 24
Finished Jul 04 06:37:31 PM PDT 24
Peak memory 204348 kb
Host smart-b629c83d-0de6-4a94-bbe7-9834fcdfb182
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182048727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.2182048727
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2914649246
Short name T198
Test name
Test status
Simulation time 83621571 ps
CPU time 1.52 seconds
Started Jul 04 06:37:22 PM PDT 24
Finished Jul 04 06:37:24 PM PDT 24
Peak memory 204584 kb
Host smart-d6f38c68-d88b-43c0-9f8f-16b811591b02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914649246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2914649246
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1185092793
Short name T1560
Test name
Test status
Simulation time 37760720 ps
CPU time 1 seconds
Started Jul 04 06:37:54 PM PDT 24
Finished Jul 04 06:37:55 PM PDT 24
Peak memory 204524 kb
Host smart-e58cd925-91cf-497d-8b27-647a827e8a95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185092793 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1185092793
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3988120326
Short name T1568
Test name
Test status
Simulation time 59899910 ps
CPU time 0.67 seconds
Started Jul 04 06:37:56 PM PDT 24
Finished Jul 04 06:37:56 PM PDT 24
Peak memory 204400 kb
Host smart-ba2bfa95-334d-4ebb-838a-95dd51c34ce0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988120326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3988120326
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.914445399
Short name T1548
Test name
Test status
Simulation time 19746636 ps
CPU time 0.67 seconds
Started Jul 04 06:37:55 PM PDT 24
Finished Jul 04 06:37:56 PM PDT 24
Peak memory 204320 kb
Host smart-c7e3040d-3f93-475f-9d9b-74aedf4c784a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914445399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.914445399
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3486780101
Short name T113
Test name
Test status
Simulation time 334448579 ps
CPU time 0.89 seconds
Started Jul 04 06:37:53 PM PDT 24
Finished Jul 04 06:37:54 PM PDT 24
Peak memory 204428 kb
Host smart-f6a742ba-05ca-44ce-9831-22003408e61f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486780101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.3486780101
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.192701049
Short name T1546
Test name
Test status
Simulation time 75396332 ps
CPU time 2.05 seconds
Started Jul 04 06:37:54 PM PDT 24
Finished Jul 04 06:37:56 PM PDT 24
Peak memory 204652 kb
Host smart-11dd1d06-5bc1-4565-88da-d0b23545b5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192701049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.192701049
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3000565314
Short name T1587
Test name
Test status
Simulation time 99995721 ps
CPU time 1.36 seconds
Started Jul 04 06:37:54 PM PDT 24
Finished Jul 04 06:37:55 PM PDT 24
Peak memory 204604 kb
Host smart-1c09d58f-22a3-45f2-93af-ebd4c21c9436
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000565314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3000565314
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.4196439410
Short name T1556
Test name
Test status
Simulation time 22786029 ps
CPU time 0.87 seconds
Started Jul 04 06:38:02 PM PDT 24
Finished Jul 04 06:38:03 PM PDT 24
Peak memory 204524 kb
Host smart-01d2f110-7f22-4dc3-8bc9-45c9937d057e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196439410 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.4196439410
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2786639950
Short name T223
Test name
Test status
Simulation time 18583993 ps
CPU time 0.79 seconds
Started Jul 04 06:38:03 PM PDT 24
Finished Jul 04 06:38:04 PM PDT 24
Peak memory 204460 kb
Host smart-f2b5348c-98bc-4094-8722-6e99af92c9a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786639950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2786639950
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3379798846
Short name T1616
Test name
Test status
Simulation time 80088732 ps
CPU time 0.73 seconds
Started Jul 04 06:38:02 PM PDT 24
Finished Jul 04 06:38:02 PM PDT 24
Peak memory 204388 kb
Host smart-af523d40-d407-49a8-aabd-1d7701e333a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379798846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3379798846
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3161563434
Short name T230
Test name
Test status
Simulation time 49392847 ps
CPU time 1.18 seconds
Started Jul 04 06:38:01 PM PDT 24
Finished Jul 04 06:38:02 PM PDT 24
Peak memory 204496 kb
Host smart-8ad49016-0a04-4960-b050-c6ab423f793d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161563434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.3161563434
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1256459873
Short name T1554
Test name
Test status
Simulation time 32604556 ps
CPU time 1.63 seconds
Started Jul 04 06:37:55 PM PDT 24
Finished Jul 04 06:37:57 PM PDT 24
Peak memory 204664 kb
Host smart-1aff23c5-07fd-41cb-a9e1-3c3312bdd4a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256459873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1256459873
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1906636195
Short name T1545
Test name
Test status
Simulation time 44806577 ps
CPU time 1.14 seconds
Started Jul 04 06:38:04 PM PDT 24
Finished Jul 04 06:38:05 PM PDT 24
Peak memory 204672 kb
Host smart-e974f602-6c0e-42dd-80c1-83bff98153c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906636195 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1906636195
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.502928031
Short name T217
Test name
Test status
Simulation time 18799801 ps
CPU time 0.74 seconds
Started Jul 04 06:38:01 PM PDT 24
Finished Jul 04 06:38:02 PM PDT 24
Peak memory 204424 kb
Host smart-1b5c9b38-0581-441e-b7f4-f735381ca5ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502928031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.502928031
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2736314890
Short name T1590
Test name
Test status
Simulation time 23036130 ps
CPU time 0.68 seconds
Started Jul 04 06:38:01 PM PDT 24
Finished Jul 04 06:38:02 PM PDT 24
Peak memory 204368 kb
Host smart-17072f7c-0150-40d6-9c67-10eeca0f5a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736314890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2736314890
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1415074568
Short name T1577
Test name
Test status
Simulation time 40290566 ps
CPU time 0.91 seconds
Started Jul 04 06:38:03 PM PDT 24
Finished Jul 04 06:38:04 PM PDT 24
Peak memory 204388 kb
Host smart-f7f49bad-19d1-46e9-a8ef-110ec08cf8e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415074568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.1415074568
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.760411446
Short name T186
Test name
Test status
Simulation time 43929663 ps
CPU time 2.09 seconds
Started Jul 04 06:38:05 PM PDT 24
Finished Jul 04 06:38:07 PM PDT 24
Peak memory 204628 kb
Host smart-63d64560-4c26-4381-852f-ddaccb4352ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760411446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.760411446
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2892510729
Short name T206
Test name
Test status
Simulation time 148504093 ps
CPU time 2.41 seconds
Started Jul 04 06:38:04 PM PDT 24
Finished Jul 04 06:38:07 PM PDT 24
Peak memory 204636 kb
Host smart-11945d66-94ff-4ba7-b2ea-0c4afbd3d99c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892510729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2892510729
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.4122259263
Short name T1584
Test name
Test status
Simulation time 30180877 ps
CPU time 0.92 seconds
Started Jul 04 06:38:02 PM PDT 24
Finished Jul 04 06:38:03 PM PDT 24
Peak memory 204524 kb
Host smart-8bb68773-024b-437f-9b44-13c325375cdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122259263 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.4122259263
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1263847354
Short name T225
Test name
Test status
Simulation time 24795974 ps
CPU time 0.8 seconds
Started Jul 04 06:38:02 PM PDT 24
Finished Jul 04 06:38:03 PM PDT 24
Peak memory 204512 kb
Host smart-1d8e3512-8705-4877-89ba-2add2b6e00b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263847354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1263847354
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3257122207
Short name T1536
Test name
Test status
Simulation time 33460623 ps
CPU time 0.66 seconds
Started Jul 04 06:38:02 PM PDT 24
Finished Jul 04 06:38:03 PM PDT 24
Peak memory 204404 kb
Host smart-05cdc6e1-6cfd-4390-93d2-10a1911c96f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257122207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3257122207
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.4144911947
Short name T130
Test name
Test status
Simulation time 39357074 ps
CPU time 0.89 seconds
Started Jul 04 06:38:03 PM PDT 24
Finished Jul 04 06:38:04 PM PDT 24
Peak memory 204428 kb
Host smart-5ad9b6e6-b081-4060-8a33-bc96fd6bc11f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144911947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.4144911947
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2452359114
Short name T1625
Test name
Test status
Simulation time 388360842 ps
CPU time 2.19 seconds
Started Jul 04 06:38:06 PM PDT 24
Finished Jul 04 06:38:08 PM PDT 24
Peak memory 204652 kb
Host smart-24b964a0-2547-4f5f-932f-699ed036d600
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452359114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2452359114
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3440029539
Short name T1579
Test name
Test status
Simulation time 31337865 ps
CPU time 0.83 seconds
Started Jul 04 06:38:03 PM PDT 24
Finished Jul 04 06:38:04 PM PDT 24
Peak memory 204520 kb
Host smart-8007ec32-49c4-4e75-b100-5431d0359e72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440029539 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3440029539
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2454835548
Short name T1540
Test name
Test status
Simulation time 76286130 ps
CPU time 0.81 seconds
Started Jul 04 06:38:01 PM PDT 24
Finished Jul 04 06:38:02 PM PDT 24
Peak memory 204480 kb
Host smart-f4c53180-867c-4d3d-b8ac-005f259d30bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454835548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2454835548
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3836534675
Short name T1627
Test name
Test status
Simulation time 17145878 ps
CPU time 0.7 seconds
Started Jul 04 06:38:01 PM PDT 24
Finished Jul 04 06:38:02 PM PDT 24
Peak memory 204376 kb
Host smart-f79a21a4-18bb-410d-86e4-0a428f2390ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836534675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3836534675
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1857110020
Short name T1557
Test name
Test status
Simulation time 64830166 ps
CPU time 0.96 seconds
Started Jul 04 06:38:02 PM PDT 24
Finished Jul 04 06:38:03 PM PDT 24
Peak memory 204376 kb
Host smart-ac839342-1c39-41c4-9064-9b0b0f40b061
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857110020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1857110020
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2564337235
Short name T153
Test name
Test status
Simulation time 130045687 ps
CPU time 1.47 seconds
Started Jul 04 06:38:04 PM PDT 24
Finished Jul 04 06:38:06 PM PDT 24
Peak memory 204688 kb
Host smart-6446d85b-17cd-4429-b0f1-16f860c77d77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564337235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2564337235
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3566282724
Short name T1565
Test name
Test status
Simulation time 107793427 ps
CPU time 1.42 seconds
Started Jul 04 06:38:13 PM PDT 24
Finished Jul 04 06:38:14 PM PDT 24
Peak memory 204640 kb
Host smart-37b556ad-270d-44ec-99d8-c6113eaa2a67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566282724 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3566282724
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1515886414
Short name T1640
Test name
Test status
Simulation time 45119404 ps
CPU time 0.8 seconds
Started Jul 04 06:38:11 PM PDT 24
Finished Jul 04 06:38:12 PM PDT 24
Peak memory 204376 kb
Host smart-5c08bc71-cf9b-45bf-8036-764bd13494b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515886414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1515886414
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1133958050
Short name T1533
Test name
Test status
Simulation time 18158650 ps
CPU time 0.66 seconds
Started Jul 04 06:38:13 PM PDT 24
Finished Jul 04 06:38:14 PM PDT 24
Peak memory 204384 kb
Host smart-4363666f-e8ca-4f1d-b536-cd4d8aab6bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133958050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1133958050
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2611823989
Short name T1624
Test name
Test status
Simulation time 27808972 ps
CPU time 1.09 seconds
Started Jul 04 06:38:11 PM PDT 24
Finished Jul 04 06:38:12 PM PDT 24
Peak memory 204492 kb
Host smart-582f390c-299d-4fce-b842-a23808a015dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611823989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2611823989
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1455122469
Short name T1619
Test name
Test status
Simulation time 49529840 ps
CPU time 1.51 seconds
Started Jul 04 06:38:01 PM PDT 24
Finished Jul 04 06:38:03 PM PDT 24
Peak memory 204624 kb
Host smart-c8d6b66d-b178-4196-9994-f56b90b6e433
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455122469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1455122469
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1956517903
Short name T210
Test name
Test status
Simulation time 143129529 ps
CPU time 1.51 seconds
Started Jul 04 06:38:12 PM PDT 24
Finished Jul 04 06:38:14 PM PDT 24
Peak memory 204600 kb
Host smart-c0880f91-0711-4ce6-b1e8-12b0721b5553
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956517903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.1956517903
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.582937484
Short name T1605
Test name
Test status
Simulation time 92219087 ps
CPU time 1.25 seconds
Started Jul 04 06:38:24 PM PDT 24
Finished Jul 04 06:38:26 PM PDT 24
Peak memory 212848 kb
Host smart-662d4272-6b2e-45cb-8eda-66f1ed3726a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582937484 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.582937484
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1070721609
Short name T222
Test name
Test status
Simulation time 18853990 ps
CPU time 0.76 seconds
Started Jul 04 06:38:11 PM PDT 24
Finished Jul 04 06:38:12 PM PDT 24
Peak memory 204388 kb
Host smart-f541befb-f4a5-4134-a1d2-17f9ddce1aaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070721609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1070721609
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.3176761884
Short name T1582
Test name
Test status
Simulation time 41800417 ps
CPU time 0.63 seconds
Started Jul 04 06:38:13 PM PDT 24
Finished Jul 04 06:38:14 PM PDT 24
Peak memory 204432 kb
Host smart-69f92dbb-e63f-4453-8232-10a4343207b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176761884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3176761884
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2423651208
Short name T231
Test name
Test status
Simulation time 23030531 ps
CPU time 0.9 seconds
Started Jul 04 06:38:09 PM PDT 24
Finished Jul 04 06:38:10 PM PDT 24
Peak memory 204412 kb
Host smart-6b172ba7-9d54-4a05-afa5-8e8b22899d85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423651208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.2423651208
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.4013113300
Short name T202
Test name
Test status
Simulation time 1039078574 ps
CPU time 1.66 seconds
Started Jul 04 06:38:11 PM PDT 24
Finished Jul 04 06:38:13 PM PDT 24
Peak memory 204648 kb
Host smart-3c99df13-edeb-4cae-933b-340a14eee0c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013113300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.4013113300
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2876500365
Short name T199
Test name
Test status
Simulation time 480967315 ps
CPU time 2.3 seconds
Started Jul 04 06:38:13 PM PDT 24
Finished Jul 04 06:38:16 PM PDT 24
Peak memory 204648 kb
Host smart-62425bdb-92f5-4008-be55-f8cbb8155b72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876500365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2876500365
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3114573298
Short name T1637
Test name
Test status
Simulation time 157157651 ps
CPU time 0.96 seconds
Started Jul 04 06:38:18 PM PDT 24
Finished Jul 04 06:38:19 PM PDT 24
Peak memory 204488 kb
Host smart-9f102844-cf81-4d42-b33f-988721069a2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114573298 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3114573298
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4011926819
Short name T1603
Test name
Test status
Simulation time 28400359 ps
CPU time 0.77 seconds
Started Jul 04 06:38:20 PM PDT 24
Finished Jul 04 06:38:21 PM PDT 24
Peak memory 204464 kb
Host smart-d5fef3d5-c45e-414c-8bcc-68dca0c3d3eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011926819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.4011926819
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.3744371003
Short name T1608
Test name
Test status
Simulation time 21133050 ps
CPU time 0.72 seconds
Started Jul 04 06:38:18 PM PDT 24
Finished Jul 04 06:38:18 PM PDT 24
Peak memory 204368 kb
Host smart-c860ea6c-eb90-4501-aabe-f4c31f9029ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744371003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.3744371003
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.38576197
Short name T1542
Test name
Test status
Simulation time 22677539 ps
CPU time 0.85 seconds
Started Jul 04 06:38:20 PM PDT 24
Finished Jul 04 06:38:21 PM PDT 24
Peak memory 204404 kb
Host smart-acd368a1-32e5-41bf-bf95-ff83fa278bb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38576197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_out
standing.38576197
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2310974065
Short name T1611
Test name
Test status
Simulation time 81137200 ps
CPU time 1.28 seconds
Started Jul 04 06:38:20 PM PDT 24
Finished Jul 04 06:38:21 PM PDT 24
Peak memory 204668 kb
Host smart-643cf7fd-05d9-4367-95d5-e9ee014fac55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310974065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2310974065
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.321011722
Short name T208
Test name
Test status
Simulation time 248703536 ps
CPU time 2.14 seconds
Started Jul 04 06:38:19 PM PDT 24
Finished Jul 04 06:38:21 PM PDT 24
Peak memory 204596 kb
Host smart-b6e779f6-81df-4f32-8c4e-3b5d8d06c4ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321011722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.321011722
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1802473946
Short name T1634
Test name
Test status
Simulation time 66263690 ps
CPU time 0.96 seconds
Started Jul 04 06:38:18 PM PDT 24
Finished Jul 04 06:38:19 PM PDT 24
Peak memory 204564 kb
Host smart-3db22dd3-4020-4d63-9129-7969c6cdc5e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802473946 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1802473946
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.310732718
Short name T1580
Test name
Test status
Simulation time 144774692 ps
CPU time 0.75 seconds
Started Jul 04 06:38:18 PM PDT 24
Finished Jul 04 06:38:19 PM PDT 24
Peak memory 204468 kb
Host smart-e1c10ac3-9b83-4aed-b194-d469a1ab04b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310732718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.310732718
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3333991783
Short name T1612
Test name
Test status
Simulation time 42466392 ps
CPU time 0.67 seconds
Started Jul 04 06:38:18 PM PDT 24
Finished Jul 04 06:38:19 PM PDT 24
Peak memory 204400 kb
Host smart-661d82d2-2b67-4f18-8a26-aa8f2a23b815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333991783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3333991783
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1671488016
Short name T1552
Test name
Test status
Simulation time 121947736 ps
CPU time 0.86 seconds
Started Jul 04 06:38:18 PM PDT 24
Finished Jul 04 06:38:19 PM PDT 24
Peak memory 204376 kb
Host smart-02fb2699-e4b8-40b3-81e8-50741c089926
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671488016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.1671488016
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1644376456
Short name T1606
Test name
Test status
Simulation time 136184731 ps
CPU time 1.48 seconds
Started Jul 04 06:38:18 PM PDT 24
Finished Jul 04 06:38:20 PM PDT 24
Peak memory 204656 kb
Host smart-5cb73b76-5d19-4273-85c7-85c300986989
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644376456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1644376456
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.751313499
Short name T1639
Test name
Test status
Simulation time 55499499 ps
CPU time 1.34 seconds
Started Jul 04 06:38:18 PM PDT 24
Finished Jul 04 06:38:20 PM PDT 24
Peak memory 204616 kb
Host smart-f3a6fd4b-23dd-4553-8a97-7263ea04fcbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751313499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.751313499
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1470460143
Short name T1544
Test name
Test status
Simulation time 37543869 ps
CPU time 0.83 seconds
Started Jul 04 06:38:25 PM PDT 24
Finished Jul 04 06:38:26 PM PDT 24
Peak memory 204504 kb
Host smart-15176218-5f10-4fab-8fa1-3af8c69f4ee0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470460143 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1470460143
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3919793030
Short name T226
Test name
Test status
Simulation time 29453289 ps
CPU time 0.76 seconds
Started Jul 04 06:38:18 PM PDT 24
Finished Jul 04 06:38:19 PM PDT 24
Peak memory 204448 kb
Host smart-9a6f85a3-cd87-47ca-b688-9b79f2e2398b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919793030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3919793030
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1003213682
Short name T1607
Test name
Test status
Simulation time 26309779 ps
CPU time 0.65 seconds
Started Jul 04 06:38:18 PM PDT 24
Finished Jul 04 06:38:19 PM PDT 24
Peak memory 204384 kb
Host smart-abb5e2b9-426f-43bd-9e93-40189eaafed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003213682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1003213682
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.439384428
Short name T112
Test name
Test status
Simulation time 57875909 ps
CPU time 1.15 seconds
Started Jul 04 06:38:20 PM PDT 24
Finished Jul 04 06:38:21 PM PDT 24
Peak memory 204556 kb
Host smart-771147e3-eb95-4850-84ec-0073f426243b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439384428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_ou
tstanding.439384428
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2506915635
Short name T193
Test name
Test status
Simulation time 565278857 ps
CPU time 2.46 seconds
Started Jul 04 06:38:17 PM PDT 24
Finished Jul 04 06:38:20 PM PDT 24
Peak memory 204576 kb
Host smart-4c1b2f94-42c4-4533-893a-204626f56381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506915635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2506915635
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1934332985
Short name T109
Test name
Test status
Simulation time 360969663 ps
CPU time 1.26 seconds
Started Jul 04 06:37:38 PM PDT 24
Finished Jul 04 06:37:40 PM PDT 24
Peak memory 204568 kb
Host smart-2593c885-c038-4d1e-9227-f253e40753dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934332985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1934332985
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3217435948
Short name T1588
Test name
Test status
Simulation time 381484598 ps
CPU time 2.64 seconds
Started Jul 04 06:37:36 PM PDT 24
Finished Jul 04 06:37:39 PM PDT 24
Peak memory 204584 kb
Host smart-96611034-1436-4b4b-bfa7-dcbfba8164cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217435948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3217435948
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2455535266
Short name T215
Test name
Test status
Simulation time 18577585 ps
CPU time 0.69 seconds
Started Jul 04 06:37:37 PM PDT 24
Finished Jul 04 06:37:37 PM PDT 24
Peak memory 204484 kb
Host smart-a4904aab-2f03-4840-92ac-e1b6a11a5fd9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455535266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2455535266
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3327949683
Short name T191
Test name
Test status
Simulation time 54874845 ps
CPU time 0.81 seconds
Started Jul 04 06:37:37 PM PDT 24
Finished Jul 04 06:37:38 PM PDT 24
Peak memory 204504 kb
Host smart-82fc84e3-1a91-454d-947a-5a2165de952b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327949683 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3327949683
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2778307448
Short name T1595
Test name
Test status
Simulation time 72691332 ps
CPU time 0.79 seconds
Started Jul 04 06:37:38 PM PDT 24
Finished Jul 04 06:37:39 PM PDT 24
Peak memory 204452 kb
Host smart-fa5cf1ba-8dfd-45d9-b686-1c5a14df823a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778307448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2778307448
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1920283931
Short name T1592
Test name
Test status
Simulation time 19280706 ps
CPU time 0.67 seconds
Started Jul 04 06:37:37 PM PDT 24
Finished Jul 04 06:37:38 PM PDT 24
Peak memory 204384 kb
Host smart-b39277b2-cfb1-4307-97f3-2075fb22b797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920283931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1920283931
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.291383149
Short name T229
Test name
Test status
Simulation time 28839551 ps
CPU time 1.1 seconds
Started Jul 04 06:37:37 PM PDT 24
Finished Jul 04 06:37:39 PM PDT 24
Peak memory 204532 kb
Host smart-5f967bc8-7ce1-4610-aec5-99d7c5c455a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291383149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_out
standing.291383149
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1570632564
Short name T195
Test name
Test status
Simulation time 239887716 ps
CPU time 1.72 seconds
Started Jul 04 06:37:29 PM PDT 24
Finished Jul 04 06:37:30 PM PDT 24
Peak memory 212840 kb
Host smart-3e1a1f23-d5a6-40ca-b135-254830ea67aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570632564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1570632564
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.533428849
Short name T1638
Test name
Test status
Simulation time 49811536 ps
CPU time 0.69 seconds
Started Jul 04 06:38:27 PM PDT 24
Finished Jul 04 06:38:28 PM PDT 24
Peak memory 204328 kb
Host smart-55b41870-7691-4189-a5ed-36e2517de5ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533428849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.533428849
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.3968752698
Short name T1623
Test name
Test status
Simulation time 17514732 ps
CPU time 0.68 seconds
Started Jul 04 06:38:29 PM PDT 24
Finished Jul 04 06:38:30 PM PDT 24
Peak memory 204292 kb
Host smart-c813daff-b97d-4127-9830-bba5319ff4dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968752698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3968752698
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1020026262
Short name T1535
Test name
Test status
Simulation time 45036570 ps
CPU time 0.72 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:27 PM PDT 24
Peak memory 204392 kb
Host smart-3fcbccad-32bc-48e2-9e72-42d394270d61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020026262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1020026262
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2779351981
Short name T1573
Test name
Test status
Simulation time 43832927 ps
CPU time 0.68 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:27 PM PDT 24
Peak memory 204364 kb
Host smart-0fd39e2c-3605-4c5e-8052-63a8213557df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779351981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2779351981
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.2095906668
Short name T1581
Test name
Test status
Simulation time 17126925 ps
CPU time 0.65 seconds
Started Jul 04 06:38:24 PM PDT 24
Finished Jul 04 06:38:25 PM PDT 24
Peak memory 204436 kb
Host smart-6e8011a0-13ab-4ee7-b5e8-ce3e538fa2fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095906668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2095906668
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.491787852
Short name T1628
Test name
Test status
Simulation time 36906492 ps
CPU time 0.68 seconds
Started Jul 04 06:38:25 PM PDT 24
Finished Jul 04 06:38:26 PM PDT 24
Peak memory 204364 kb
Host smart-a2753037-2267-41cf-b244-3728305fda84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491787852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.491787852
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.337200965
Short name T1562
Test name
Test status
Simulation time 38602772 ps
CPU time 0.65 seconds
Started Jul 04 06:38:27 PM PDT 24
Finished Jul 04 06:38:28 PM PDT 24
Peak memory 204376 kb
Host smart-4432869f-2d4c-4c83-8bc8-ac979267869e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337200965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.337200965
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.963674631
Short name T1549
Test name
Test status
Simulation time 19668247 ps
CPU time 0.64 seconds
Started Jul 04 06:38:24 PM PDT 24
Finished Jul 04 06:38:25 PM PDT 24
Peak memory 204184 kb
Host smart-696c792f-6ced-4ce1-b434-69210b5df642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963674631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.963674631
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.3356780696
Short name T1551
Test name
Test status
Simulation time 18587898 ps
CPU time 0.7 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:27 PM PDT 24
Peak memory 204360 kb
Host smart-95c61713-ba76-4ca3-a638-789bdfc65a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356780696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3356780696
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.1515978653
Short name T1620
Test name
Test status
Simulation time 50898406 ps
CPU time 0.67 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:26 PM PDT 24
Peak memory 204384 kb
Host smart-2346704c-c92c-4562-b0d0-41cd04bedfaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515978653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1515978653
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3570618752
Short name T1598
Test name
Test status
Simulation time 287552946 ps
CPU time 2.95 seconds
Started Jul 04 06:37:50 PM PDT 24
Finished Jul 04 06:37:53 PM PDT 24
Peak memory 204576 kb
Host smart-1e9b6c87-06fd-46c8-beab-bc9c0394348c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570618752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3570618752
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2989110085
Short name T216
Test name
Test status
Simulation time 24959023 ps
CPU time 0.8 seconds
Started Jul 04 06:37:36 PM PDT 24
Finished Jul 04 06:37:37 PM PDT 24
Peak memory 204452 kb
Host smart-7f2033c6-a710-42d2-8c82-0bb859099adf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989110085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2989110085
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3311544258
Short name T1596
Test name
Test status
Simulation time 34131585 ps
CPU time 1 seconds
Started Jul 04 06:37:47 PM PDT 24
Finished Jul 04 06:37:49 PM PDT 24
Peak memory 204528 kb
Host smart-b7820d7a-74d7-4060-92ad-8410957910a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311544258 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3311544258
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.4261497254
Short name T227
Test name
Test status
Simulation time 50782154 ps
CPU time 0.77 seconds
Started Jul 04 06:37:47 PM PDT 24
Finished Jul 04 06:37:48 PM PDT 24
Peak memory 204400 kb
Host smart-3d097943-1cd2-4c0b-b361-f506c1d821d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261497254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.4261497254
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.502633220
Short name T1591
Test name
Test status
Simulation time 19058506 ps
CPU time 0.68 seconds
Started Jul 04 06:37:37 PM PDT 24
Finished Jul 04 06:37:38 PM PDT 24
Peak memory 204372 kb
Host smart-470936a7-3a05-4910-9ff1-fd96b80afad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502633220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.502633220
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1709664004
Short name T1617
Test name
Test status
Simulation time 102952314 ps
CPU time 0.85 seconds
Started Jul 04 06:37:50 PM PDT 24
Finished Jul 04 06:37:51 PM PDT 24
Peak memory 204440 kb
Host smart-14b048bf-d116-4fe4-89d7-ac0b92e38bfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709664004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1709664004
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1555045247
Short name T203
Test name
Test status
Simulation time 71665907 ps
CPU time 1.15 seconds
Started Jul 04 06:37:36 PM PDT 24
Finished Jul 04 06:37:38 PM PDT 24
Peak memory 204656 kb
Host smart-2bb87843-e3b3-4b8a-a2d0-c5a4e27938ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555045247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1555045247
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3597591354
Short name T196
Test name
Test status
Simulation time 122570851 ps
CPU time 2.18 seconds
Started Jul 04 06:37:38 PM PDT 24
Finished Jul 04 06:37:40 PM PDT 24
Peak memory 204628 kb
Host smart-2d2db9dd-7747-46be-ba6e-69560df7eff1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597591354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3597591354
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1418522323
Short name T1602
Test name
Test status
Simulation time 23058519 ps
CPU time 0.69 seconds
Started Jul 04 06:38:29 PM PDT 24
Finished Jul 04 06:38:30 PM PDT 24
Peak memory 204292 kb
Host smart-648a500e-3679-4bb2-9713-9cba5479ad3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418522323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1418522323
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.1183499830
Short name T1558
Test name
Test status
Simulation time 25256884 ps
CPU time 0.64 seconds
Started Jul 04 06:38:27 PM PDT 24
Finished Jul 04 06:38:28 PM PDT 24
Peak memory 204380 kb
Host smart-814ed521-1e4f-464b-89a0-7d2c9deccbb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183499830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.1183499830
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.4063937535
Short name T1583
Test name
Test status
Simulation time 24841352 ps
CPU time 0.66 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:28 PM PDT 24
Peak memory 204376 kb
Host smart-c08e09ab-c9ba-4a69-8a44-0e68186b759a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063937535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.4063937535
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.1735733054
Short name T1597
Test name
Test status
Simulation time 24653358 ps
CPU time 0.68 seconds
Started Jul 04 06:38:25 PM PDT 24
Finished Jul 04 06:38:26 PM PDT 24
Peak memory 204348 kb
Host smart-c33925b4-14ad-4e63-9d04-f60d552c21de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735733054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1735733054
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.2914479964
Short name T1586
Test name
Test status
Simulation time 17430217 ps
CPU time 0.66 seconds
Started Jul 04 06:38:25 PM PDT 24
Finished Jul 04 06:38:26 PM PDT 24
Peak memory 204604 kb
Host smart-622734f0-d9ce-4c09-b487-11fbbbfdbb99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914479964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2914479964
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3626943666
Short name T1574
Test name
Test status
Simulation time 57012995 ps
CPU time 0.72 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:27 PM PDT 24
Peak memory 204404 kb
Host smart-81c5368c-c79a-48db-a977-84dff7a286f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626943666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3626943666
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.3231764425
Short name T1604
Test name
Test status
Simulation time 118078847 ps
CPU time 0.66 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:27 PM PDT 24
Peak memory 204604 kb
Host smart-99241b12-f821-4b3d-a9ce-610563bd6138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231764425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3231764425
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1966113569
Short name T1631
Test name
Test status
Simulation time 19892590 ps
CPU time 0.63 seconds
Started Jul 04 06:38:27 PM PDT 24
Finished Jul 04 06:38:28 PM PDT 24
Peak memory 204372 kb
Host smart-d13fffb3-4201-4b38-959d-49b1c7820e47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966113569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1966113569
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.4029837408
Short name T135
Test name
Test status
Simulation time 35650470 ps
CPU time 0.69 seconds
Started Jul 04 06:38:27 PM PDT 24
Finished Jul 04 06:38:28 PM PDT 24
Peak memory 204340 kb
Host smart-5376deb3-0183-4c3e-97f8-d58b73b8b7cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029837408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.4029837408
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.293488326
Short name T1626
Test name
Test status
Simulation time 51592765 ps
CPU time 0.66 seconds
Started Jul 04 06:38:29 PM PDT 24
Finished Jul 04 06:38:30 PM PDT 24
Peak memory 204292 kb
Host smart-8a375079-7b9e-4b34-85eb-6d6f56583115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293488326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.293488326
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.822561689
Short name T1633
Test name
Test status
Simulation time 28450469 ps
CPU time 1.27 seconds
Started Jul 04 06:37:46 PM PDT 24
Finished Jul 04 06:37:47 PM PDT 24
Peak memory 204532 kb
Host smart-436df885-1675-4aa6-8688-ebab94fedbb9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822561689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.822561689
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.509159087
Short name T1559
Test name
Test status
Simulation time 113324442 ps
CPU time 4.48 seconds
Started Jul 04 06:37:48 PM PDT 24
Finished Jul 04 06:37:53 PM PDT 24
Peak memory 204580 kb
Host smart-cfb97fe3-a011-45fb-9b83-a803d607c0e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509159087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.509159087
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.4242468485
Short name T1629
Test name
Test status
Simulation time 140797833 ps
CPU time 0.75 seconds
Started Jul 04 06:37:48 PM PDT 24
Finished Jul 04 06:37:49 PM PDT 24
Peak memory 204476 kb
Host smart-6484ffe3-9356-4227-bd2f-62694b87108c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242468485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.4242468485
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1868954295
Short name T154
Test name
Test status
Simulation time 78963652 ps
CPU time 0.98 seconds
Started Jul 04 06:37:47 PM PDT 24
Finished Jul 04 06:37:48 PM PDT 24
Peak memory 204484 kb
Host smart-60118c83-26dd-49b1-bd3a-0e450f975dd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868954295 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1868954295
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2205838450
Short name T1555
Test name
Test status
Simulation time 17280438 ps
CPU time 0.72 seconds
Started Jul 04 06:37:48 PM PDT 24
Finished Jul 04 06:37:49 PM PDT 24
Peak memory 204384 kb
Host smart-7546f1ab-4c92-41c3-b3e3-7cd635ba6620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205838450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2205838450
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1870630396
Short name T1550
Test name
Test status
Simulation time 21791090 ps
CPU time 0.68 seconds
Started Jul 04 06:37:46 PM PDT 24
Finished Jul 04 06:37:47 PM PDT 24
Peak memory 204372 kb
Host smart-f91350aa-d1de-4b48-9dda-5ac4a1d10328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870630396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1870630396
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.4293444813
Short name T107
Test name
Test status
Simulation time 105036715 ps
CPU time 1.17 seconds
Started Jul 04 06:37:47 PM PDT 24
Finished Jul 04 06:37:49 PM PDT 24
Peak memory 204588 kb
Host smart-866a8572-75e2-4cd3-bb5a-edb6890f80ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293444813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.4293444813
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.930966069
Short name T1641
Test name
Test status
Simulation time 361762754 ps
CPU time 1.9 seconds
Started Jul 04 06:37:47 PM PDT 24
Finished Jul 04 06:37:49 PM PDT 24
Peak memory 204688 kb
Host smart-250394ad-d5bf-420c-8ba3-b98a1d86d8a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930966069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.930966069
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2322213108
Short name T209
Test name
Test status
Simulation time 262790568 ps
CPU time 1.46 seconds
Started Jul 04 06:37:46 PM PDT 24
Finished Jul 04 06:37:48 PM PDT 24
Peak memory 204580 kb
Host smart-42ef00e6-7ea6-4f8b-8d94-7730444b5997
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322213108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.2322213108
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.256870171
Short name T1621
Test name
Test status
Simulation time 21279524 ps
CPU time 0.72 seconds
Started Jul 04 06:38:27 PM PDT 24
Finished Jul 04 06:38:28 PM PDT 24
Peak memory 204380 kb
Host smart-36723663-454f-4b71-ac44-c37db7a6dff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256870171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.256870171
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.1004891916
Short name T1593
Test name
Test status
Simulation time 51694885 ps
CPU time 0.66 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:27 PM PDT 24
Peak memory 204348 kb
Host smart-08d3a43d-136e-44a0-b5c8-0b60da11e1c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004891916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1004891916
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.806345237
Short name T1534
Test name
Test status
Simulation time 42923691 ps
CPU time 0.66 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:27 PM PDT 24
Peak memory 204332 kb
Host smart-aae85149-4e30-4c2e-bc73-ff6cfedddf4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806345237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.806345237
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.3728369199
Short name T1600
Test name
Test status
Simulation time 20023330 ps
CPU time 0.71 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:28 PM PDT 24
Peak memory 204396 kb
Host smart-ec7942d0-8959-47cf-956c-f3f20df31241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728369199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3728369199
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.2199336916
Short name T1585
Test name
Test status
Simulation time 14685880 ps
CPU time 0.66 seconds
Started Jul 04 06:38:25 PM PDT 24
Finished Jul 04 06:38:25 PM PDT 24
Peak memory 204368 kb
Host smart-1ff853e7-c87e-4430-8d3e-7a361a99c916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199336916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2199336916
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.656057448
Short name T1578
Test name
Test status
Simulation time 47743110 ps
CPU time 0.72 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:27 PM PDT 24
Peak memory 204348 kb
Host smart-fe50ca20-381b-42f7-8aac-ec1d73abccbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656057448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.656057448
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.2696827109
Short name T1599
Test name
Test status
Simulation time 18072266 ps
CPU time 0.73 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:27 PM PDT 24
Peak memory 204372 kb
Host smart-2807ddfb-3d57-4811-a0d7-a99c63862dc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696827109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2696827109
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3458834759
Short name T1610
Test name
Test status
Simulation time 20745902 ps
CPU time 0.72 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:28 PM PDT 24
Peak memory 204320 kb
Host smart-dadc5e57-39fd-4366-a3ef-22f84ca40df5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458834759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3458834759
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2153815072
Short name T1566
Test name
Test status
Simulation time 30497753 ps
CPU time 0.68 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:27 PM PDT 24
Peak memory 204396 kb
Host smart-305a6e5e-f02b-45c2-89af-5221da2870a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153815072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2153815072
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.581796707
Short name T1575
Test name
Test status
Simulation time 32313607 ps
CPU time 0.7 seconds
Started Jul 04 06:38:26 PM PDT 24
Finished Jul 04 06:38:27 PM PDT 24
Peak memory 204364 kb
Host smart-5432eb55-d971-45ce-8e57-143edbebbb1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581796707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.581796707
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.226076993
Short name T1547
Test name
Test status
Simulation time 124836756 ps
CPU time 1.81 seconds
Started Jul 04 06:37:50 PM PDT 24
Finished Jul 04 06:37:52 PM PDT 24
Peak memory 204660 kb
Host smart-9f006198-2aa0-4397-bc7d-4958a1179661
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226076993 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.226076993
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.656338840
Short name T1563
Test name
Test status
Simulation time 22161726 ps
CPU time 0.69 seconds
Started Jul 04 06:37:49 PM PDT 24
Finished Jul 04 06:37:50 PM PDT 24
Peak memory 204428 kb
Host smart-f86bd7f9-733d-49c4-befb-c9c8577cf027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656338840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.656338840
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2531050046
Short name T1532
Test name
Test status
Simulation time 48495422 ps
CPU time 0.75 seconds
Started Jul 04 06:37:46 PM PDT 24
Finished Jul 04 06:37:47 PM PDT 24
Peak memory 204384 kb
Host smart-c5e0eff3-7642-47f0-8858-386cf42709d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531050046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2531050046
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.459483650
Short name T1539
Test name
Test status
Simulation time 39299605 ps
CPU time 0.88 seconds
Started Jul 04 06:37:47 PM PDT 24
Finished Jul 04 06:37:48 PM PDT 24
Peak memory 204452 kb
Host smart-0adfd1b1-b8e9-44b3-af1a-6ca7296d29fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459483650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_out
standing.459483650
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1211756667
Short name T1609
Test name
Test status
Simulation time 25888889 ps
CPU time 1.22 seconds
Started Jul 04 06:37:46 PM PDT 24
Finished Jul 04 06:37:48 PM PDT 24
Peak memory 204632 kb
Host smart-667d214b-dae9-4425-a8df-30b88dbfa0e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211756667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1211756667
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.30610961
Short name T197
Test name
Test status
Simulation time 95047017 ps
CPU time 1.39 seconds
Started Jul 04 06:37:47 PM PDT 24
Finished Jul 04 06:37:49 PM PDT 24
Peak memory 204592 kb
Host smart-6a2a3f30-2b41-422a-a721-fe95b66cedd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30610961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.30610961
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1076525221
Short name T1594
Test name
Test status
Simulation time 140224400 ps
CPU time 0.97 seconds
Started Jul 04 06:37:47 PM PDT 24
Finished Jul 04 06:37:48 PM PDT 24
Peak memory 204484 kb
Host smart-524caee2-d688-431b-b8f6-5b406bc1bfd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076525221 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1076525221
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1959635348
Short name T219
Test name
Test status
Simulation time 46897073 ps
CPU time 0.69 seconds
Started Jul 04 06:37:47 PM PDT 24
Finished Jul 04 06:37:48 PM PDT 24
Peak memory 204416 kb
Host smart-7932c6f9-58a1-46f7-99d2-616d270cc604
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959635348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1959635348
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.3001229929
Short name T1618
Test name
Test status
Simulation time 51065908 ps
CPU time 0.67 seconds
Started Jul 04 06:37:46 PM PDT 24
Finished Jul 04 06:37:47 PM PDT 24
Peak memory 204372 kb
Host smart-c36bde28-9dc0-4442-aef3-eb698f86d481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001229929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.3001229929
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.100294814
Short name T104
Test name
Test status
Simulation time 101886723 ps
CPU time 0.84 seconds
Started Jul 04 06:37:50 PM PDT 24
Finished Jul 04 06:37:51 PM PDT 24
Peak memory 204448 kb
Host smart-4f7b9a84-cba2-45be-a384-10068514ca5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100294814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_out
standing.100294814
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1193740070
Short name T194
Test name
Test status
Simulation time 62351405 ps
CPU time 1.56 seconds
Started Jul 04 06:37:50 PM PDT 24
Finished Jul 04 06:37:52 PM PDT 24
Peak memory 204680 kb
Host smart-e6806d9b-4989-43bc-970d-c6ba67d35fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193740070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1193740070
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.576562072
Short name T200
Test name
Test status
Simulation time 174234073 ps
CPU time 1.33 seconds
Started Jul 04 06:37:46 PM PDT 24
Finished Jul 04 06:37:48 PM PDT 24
Peak memory 204572 kb
Host smart-e2aad6a2-1fd9-412a-ac9f-7f327908cba5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576562072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.576562072
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2065411049
Short name T1538
Test name
Test status
Simulation time 55377227 ps
CPU time 0.92 seconds
Started Jul 04 06:37:53 PM PDT 24
Finished Jul 04 06:37:54 PM PDT 24
Peak memory 204496 kb
Host smart-38ddf489-866f-48f1-b792-69e590d02420
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065411049 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2065411049
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1703256162
Short name T1537
Test name
Test status
Simulation time 22872490 ps
CPU time 0.72 seconds
Started Jul 04 06:37:55 PM PDT 24
Finished Jul 04 06:37:56 PM PDT 24
Peak memory 204400 kb
Host smart-40e17070-bd18-4edf-9035-5eb883581038
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703256162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1703256162
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.723124011
Short name T1630
Test name
Test status
Simulation time 18658198 ps
CPU time 0.67 seconds
Started Jul 04 06:37:47 PM PDT 24
Finished Jul 04 06:37:48 PM PDT 24
Peak memory 204328 kb
Host smart-ecb7c64d-7799-46d5-859d-a309cb39d146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723124011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.723124011
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.228628848
Short name T1622
Test name
Test status
Simulation time 21235016 ps
CPU time 0.88 seconds
Started Jul 04 06:37:55 PM PDT 24
Finished Jul 04 06:37:56 PM PDT 24
Peak memory 204448 kb
Host smart-a859cb50-a9f0-435b-8eec-acb492952cfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228628848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out
standing.228628848
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3304516673
Short name T1635
Test name
Test status
Simulation time 274743775 ps
CPU time 1.94 seconds
Started Jul 04 06:37:47 PM PDT 24
Finished Jul 04 06:37:49 PM PDT 24
Peak memory 204576 kb
Host smart-2a868c65-5838-4f19-bc7b-0ff1d5a5a973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304516673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3304516673
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.919593873
Short name T214
Test name
Test status
Simulation time 24717420 ps
CPU time 0.87 seconds
Started Jul 04 06:37:57 PM PDT 24
Finished Jul 04 06:37:58 PM PDT 24
Peak memory 204572 kb
Host smart-5ccbc73f-5407-454e-bf67-dcc300c2008e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919593873 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.919593873
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1936662782
Short name T218
Test name
Test status
Simulation time 28844125 ps
CPU time 0.69 seconds
Started Jul 04 06:37:54 PM PDT 24
Finished Jul 04 06:37:55 PM PDT 24
Peak memory 204468 kb
Host smart-9687e5a8-dc51-4e4e-aec9-56e605a37dda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936662782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1936662782
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1823311220
Short name T1572
Test name
Test status
Simulation time 27459457 ps
CPU time 0.68 seconds
Started Jul 04 06:37:54 PM PDT 24
Finished Jul 04 06:37:55 PM PDT 24
Peak memory 204380 kb
Host smart-eff87d9c-0148-4a78-85e3-594f771d075f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823311220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1823311220
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3069964454
Short name T108
Test name
Test status
Simulation time 137103270 ps
CPU time 0.88 seconds
Started Jul 04 06:37:53 PM PDT 24
Finished Jul 04 06:37:54 PM PDT 24
Peak memory 204440 kb
Host smart-5c27220a-70aa-460a-8e3a-2829e11a2c7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069964454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.3069964454
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1767601210
Short name T1569
Test name
Test status
Simulation time 36025861 ps
CPU time 1.74 seconds
Started Jul 04 06:37:53 PM PDT 24
Finished Jul 04 06:37:55 PM PDT 24
Peak memory 204584 kb
Host smart-b98cc3c7-921d-414e-8f23-11ba62f33e6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767601210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1767601210
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1658438699
Short name T1636
Test name
Test status
Simulation time 87557936 ps
CPU time 2.12 seconds
Started Jul 04 06:37:54 PM PDT 24
Finished Jul 04 06:37:56 PM PDT 24
Peak memory 204624 kb
Host smart-93cc5bb9-a068-49e0-8a8e-02496b19bdaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658438699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1658438699
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3639975571
Short name T1601
Test name
Test status
Simulation time 72862799 ps
CPU time 0.79 seconds
Started Jul 04 06:37:54 PM PDT 24
Finished Jul 04 06:37:55 PM PDT 24
Peak memory 204548 kb
Host smart-f95184bc-1d57-4baa-8f84-12aac3d25720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639975571 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3639975571
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.991292944
Short name T110
Test name
Test status
Simulation time 83820238 ps
CPU time 0.78 seconds
Started Jul 04 06:37:54 PM PDT 24
Finished Jul 04 06:37:55 PM PDT 24
Peak memory 204428 kb
Host smart-fc7f5f3f-063b-4a4c-a607-374ca27523f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991292944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.991292944
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2753791561
Short name T1613
Test name
Test status
Simulation time 17137308 ps
CPU time 0.7 seconds
Started Jul 04 06:37:54 PM PDT 24
Finished Jul 04 06:37:54 PM PDT 24
Peak memory 204400 kb
Host smart-d199ee58-4319-40db-84d2-c780f026df77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753791561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2753791561
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4030241189
Short name T1567
Test name
Test status
Simulation time 82993038 ps
CPU time 1.22 seconds
Started Jul 04 06:37:58 PM PDT 24
Finished Jul 04 06:37:59 PM PDT 24
Peak memory 204656 kb
Host smart-bb10f92e-52e0-41fe-8dc9-a25337b20789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030241189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.4030241189
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1917996273
Short name T1615
Test name
Test status
Simulation time 131324032 ps
CPU time 2.75 seconds
Started Jul 04 06:37:54 PM PDT 24
Finished Jul 04 06:37:57 PM PDT 24
Peak memory 204644 kb
Host smart-9a3867ee-029b-4043-b3af-139f206c743a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917996273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1917996273
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2227569827
Short name T1589
Test name
Test status
Simulation time 139439379 ps
CPU time 1.48 seconds
Started Jul 04 06:37:53 PM PDT 24
Finished Jul 04 06:37:55 PM PDT 24
Peak memory 204512 kb
Host smart-600f86b7-60fa-4274-affd-7aead9deef49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227569827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2227569827
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.479104901
Short name T628
Test name
Test status
Simulation time 22790147 ps
CPU time 0.64 seconds
Started Jul 04 04:52:01 PM PDT 24
Finished Jul 04 04:52:02 PM PDT 24
Peak memory 204280 kb
Host smart-9707a8a3-0113-4762-8f93-74518191399a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479104901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.479104901
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.57252876
Short name T1158
Test name
Test status
Simulation time 869177631 ps
CPU time 3.78 seconds
Started Jul 04 04:51:59 PM PDT 24
Finished Jul 04 04:52:03 PM PDT 24
Peak memory 212924 kb
Host smart-bc7adc96-7a3e-4cf9-846e-c5352151d0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57252876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.57252876
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.1465801010
Short name T518
Test name
Test status
Simulation time 376752178 ps
CPU time 18.95 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:52:19 PM PDT 24
Peak memory 281548 kb
Host smart-198db82e-7baa-495d-b84b-5ce462c048f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465801010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.1465801010
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3170564814
Short name T1071
Test name
Test status
Simulation time 3020231236 ps
CPU time 229.58 seconds
Started Jul 04 04:51:59 PM PDT 24
Finished Jul 04 04:55:49 PM PDT 24
Peak memory 926268 kb
Host smart-7f9b0f2a-3a07-4602-bd5d-d510cd710f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170564814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3170564814
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.3583262400
Short name T745
Test name
Test status
Simulation time 3456122917 ps
CPU time 76.23 seconds
Started Jul 04 04:52:01 PM PDT 24
Finished Jul 04 04:53:17 PM PDT 24
Peak memory 739516 kb
Host smart-f197d22e-d57f-4f4e-a097-fb082922ecba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583262400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3583262400
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.2748632210
Short name T549
Test name
Test status
Simulation time 128664742 ps
CPU time 0.99 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:52:01 PM PDT 24
Peak memory 204356 kb
Host smart-54cb0ec9-d3f3-4829-bfec-26d36359c640
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748632210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.2748632210
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2115002356
Short name T973
Test name
Test status
Simulation time 15712314800 ps
CPU time 92.24 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:53:32 PM PDT 24
Peak memory 1184484 kb
Host smart-10ce8a7a-46fd-42e5-8043-72b152646d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115002356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2115002356
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.1021923517
Short name T878
Test name
Test status
Simulation time 1194141464 ps
CPU time 4.96 seconds
Started Jul 04 04:52:02 PM PDT 24
Finished Jul 04 04:52:07 PM PDT 24
Peak memory 204740 kb
Host smart-6428b3c4-d2df-428d-bf8a-b6ea5cf977d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021923517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1021923517
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.2321646221
Short name T902
Test name
Test status
Simulation time 1691515065 ps
CPU time 24.68 seconds
Started Jul 04 04:51:59 PM PDT 24
Finished Jul 04 04:52:24 PM PDT 24
Peak memory 329736 kb
Host smart-746e0e3e-36ec-417c-9768-8dee66936d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321646221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.2321646221
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.3000146062
Short name T1256
Test name
Test status
Simulation time 29450663 ps
CPU time 0.69 seconds
Started Jul 04 04:51:54 PM PDT 24
Finished Jul 04 04:51:55 PM PDT 24
Peak memory 204436 kb
Host smart-929cee4f-1114-4360-86ca-b3ba37bd76c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000146062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3000146062
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.2276383065
Short name T758
Test name
Test status
Simulation time 6813021198 ps
CPU time 57.46 seconds
Started Jul 04 04:51:53 PM PDT 24
Finished Jul 04 04:52:51 PM PDT 24
Peak memory 204816 kb
Host smart-53985bdc-e795-4869-be00-e84eb3e0ad34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276383065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.2276383065
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.3156966335
Short name T1327
Test name
Test status
Simulation time 1586657824 ps
CPU time 13.48 seconds
Started Jul 04 04:51:53 PM PDT 24
Finished Jul 04 04:52:07 PM PDT 24
Peak memory 356128 kb
Host smart-7ace5177-3d2e-4178-8565-afde79ec708f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156966335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.3156966335
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.3866030812
Short name T1416
Test name
Test status
Simulation time 7724649117 ps
CPU time 98.55 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:53:39 PM PDT 24
Peak memory 420360 kb
Host smart-5db5addd-24a4-4ec8-8f3b-bbd8610e8392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866030812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.3866030812
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.437820021
Short name T282
Test name
Test status
Simulation time 58296184743 ps
CPU time 646.35 seconds
Started Jul 04 04:52:04 PM PDT 24
Finished Jul 04 05:02:51 PM PDT 24
Peak memory 2129624 kb
Host smart-7dc9d4cc-11b7-4d32-b606-1237f052a303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437820021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.437820021
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1578843985
Short name T1398
Test name
Test status
Simulation time 733127018 ps
CPU time 11.19 seconds
Started Jul 04 04:52:02 PM PDT 24
Finished Jul 04 04:52:13 PM PDT 24
Peak memory 221052 kb
Host smart-7898cea7-8eeb-43fd-b054-c8856896057e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578843985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1578843985
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.3740941344
Short name T188
Test name
Test status
Simulation time 65487583 ps
CPU time 0.95 seconds
Started Jul 04 04:52:02 PM PDT 24
Finished Jul 04 04:52:03 PM PDT 24
Peak memory 223128 kb
Host smart-d837cd7e-7c54-4ac2-8112-e2ca6567ea23
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740941344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.3740941344
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1945381193
Short name T127
Test name
Test status
Simulation time 2541852015 ps
CPU time 6 seconds
Started Jul 04 04:51:58 PM PDT 24
Finished Jul 04 04:52:04 PM PDT 24
Peak memory 213064 kb
Host smart-7cdb730d-afb5-4936-87b7-492b2e7f58c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945381193 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1945381193
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2666569857
Short name T174
Test name
Test status
Simulation time 659821013 ps
CPU time 1.4 seconds
Started Jul 04 04:51:58 PM PDT 24
Finished Jul 04 04:52:00 PM PDT 24
Peak memory 204692 kb
Host smart-54c1e197-be99-4cdc-b4ee-d4be04153af4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666569857 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2666569857
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.2126434889
Short name T660
Test name
Test status
Simulation time 197251495 ps
CPU time 1 seconds
Started Jul 04 04:51:59 PM PDT 24
Finished Jul 04 04:52:00 PM PDT 24
Peak memory 204516 kb
Host smart-0eba577c-7e00-4c83-90c8-8ff703c09aca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126434889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.2126434889
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.1508835711
Short name T949
Test name
Test status
Simulation time 461939197 ps
CPU time 2.36 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:52:03 PM PDT 24
Peak memory 204684 kb
Host smart-86b39bb9-3df5-494b-932c-48b23daea2d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508835711 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.1508835711
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.3323288882
Short name T367
Test name
Test status
Simulation time 2269539742 ps
CPU time 1.18 seconds
Started Jul 04 04:51:59 PM PDT 24
Finished Jul 04 04:52:00 PM PDT 24
Peak memory 204516 kb
Host smart-a99ac42d-a699-40cd-9942-9c9b20f8c48c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323288882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.3323288882
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1971416281
Short name T665
Test name
Test status
Simulation time 417930666 ps
CPU time 3.27 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:52:03 PM PDT 24
Peak memory 204692 kb
Host smart-af918cb3-267b-41e2-aa5d-25e2307a31ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971416281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1971416281
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.1460268434
Short name T751
Test name
Test status
Simulation time 964921310 ps
CPU time 5.21 seconds
Started Jul 04 04:52:03 PM PDT 24
Finished Jul 04 04:52:09 PM PDT 24
Peak memory 212920 kb
Host smart-034d0a93-0c9e-4c5c-afc7-a7b5c7d5eb81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460268434 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.1460268434
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.3281896166
Short name T170
Test name
Test status
Simulation time 8648193848 ps
CPU time 13.25 seconds
Started Jul 04 04:51:59 PM PDT 24
Finished Jul 04 04:52:12 PM PDT 24
Peak memory 315256 kb
Host smart-9e89123f-cbbf-4e8b-ad62-19f03f34a157
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281896166 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.3281896166
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.3636957741
Short name T906
Test name
Test status
Simulation time 968528434 ps
CPU time 36.5 seconds
Started Jul 04 04:51:58 PM PDT 24
Finished Jul 04 04:52:35 PM PDT 24
Peak memory 204676 kb
Host smart-767b0008-87cd-4949-9362-99e1ea7b79dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636957741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.3636957741
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.1086364931
Short name T369
Test name
Test status
Simulation time 324310930 ps
CPU time 14.05 seconds
Started Jul 04 04:52:01 PM PDT 24
Finished Jul 04 04:52:15 PM PDT 24
Peak memory 204688 kb
Host smart-598229c6-cfd5-4f1a-864b-e8267475ba37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086364931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.1086364931
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.2123143992
Short name T303
Test name
Test status
Simulation time 30851075281 ps
CPU time 33.04 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:52:33 PM PDT 24
Peak memory 684704 kb
Host smart-0a192c8d-e117-4c3d-9ddf-e9c75017da76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123143992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.2123143992
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.1361644140
Short name T1074
Test name
Test status
Simulation time 19829282746 ps
CPU time 401.44 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:58:42 PM PDT 24
Peak memory 2524140 kb
Host smart-46a9fdba-0efc-4aef-88a7-32fa5cd06281
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361644140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.1361644140
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.4034185997
Short name T789
Test name
Test status
Simulation time 1334231167 ps
CPU time 7.21 seconds
Started Jul 04 04:52:02 PM PDT 24
Finished Jul 04 04:52:10 PM PDT 24
Peak memory 218728 kb
Host smart-7fe6478c-8602-4b9a-8162-a52179f778d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034185997 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.4034185997
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.255470052
Short name T1083
Test name
Test status
Simulation time 295117528 ps
CPU time 4.9 seconds
Started Jul 04 04:51:59 PM PDT 24
Finished Jul 04 04:52:04 PM PDT 24
Peak memory 204740 kb
Host smart-e97eef70-3031-4c38-8cc0-342b66994ea9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255470052 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.255470052
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_alert_test.358960907
Short name T810
Test name
Test status
Simulation time 27470928 ps
CPU time 0.68 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:52:08 PM PDT 24
Peak memory 204368 kb
Host smart-e9cadd7e-6c10-45cc-87f5-50d654a56aa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358960907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.358960907
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3257083732
Short name T755
Test name
Test status
Simulation time 153127585 ps
CPU time 6.08 seconds
Started Jul 04 04:52:05 PM PDT 24
Finished Jul 04 04:52:11 PM PDT 24
Peak memory 213036 kb
Host smart-ab178f26-145c-4775-95f6-b2fc9201b7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257083732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3257083732
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.3405018489
Short name T1408
Test name
Test status
Simulation time 150801006 ps
CPU time 3.51 seconds
Started Jul 04 04:52:01 PM PDT 24
Finished Jul 04 04:52:05 PM PDT 24
Peak memory 225200 kb
Host smart-26304719-3e7f-4ac4-abb0-5ca41fa36d61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405018489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.3405018489
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.2433396303
Short name T87
Test name
Test status
Simulation time 7665815782 ps
CPU time 115.2 seconds
Started Jul 04 04:52:01 PM PDT 24
Finished Jul 04 04:53:56 PM PDT 24
Peak memory 626880 kb
Host smart-6a707367-0d63-48e5-8fc7-efcd690554c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433396303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2433396303
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.162854511
Short name T1100
Test name
Test status
Simulation time 7241194650 ps
CPU time 193.8 seconds
Started Jul 04 04:51:58 PM PDT 24
Finished Jul 04 04:55:12 PM PDT 24
Peak memory 820372 kb
Host smart-00107397-4920-46c6-9b19-f7d4546882ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162854511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.162854511
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.3859676181
Short name T238
Test name
Test status
Simulation time 423999862 ps
CPU time 0.93 seconds
Started Jul 04 04:51:57 PM PDT 24
Finished Jul 04 04:51:58 PM PDT 24
Peak memory 204408 kb
Host smart-e66de188-0a09-44ae-9967-18b4635cbfab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859676181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.3859676181
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.2163208378
Short name T353
Test name
Test status
Simulation time 110105021 ps
CPU time 6.51 seconds
Started Jul 04 04:52:03 PM PDT 24
Finished Jul 04 04:52:10 PM PDT 24
Peak memory 220712 kb
Host smart-526b55f8-f738-4afa-ba5d-efa58a96f927
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163208378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
2163208378
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.2757043380
Short name T598
Test name
Test status
Simulation time 18221365586 ps
CPU time 138.75 seconds
Started Jul 04 04:51:59 PM PDT 24
Finished Jul 04 04:54:18 PM PDT 24
Peak memory 1341444 kb
Host smart-f3bbeea8-869a-4705-99e1-1cddcfe79aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757043380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2757043380
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.358273784
Short name T1175
Test name
Test status
Simulation time 541125664 ps
CPU time 2.91 seconds
Started Jul 04 04:52:08 PM PDT 24
Finished Jul 04 04:52:12 PM PDT 24
Peak memory 204716 kb
Host smart-da97f803-a00c-4e32-ae97-478c83530007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358273784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.358273784
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.1056906336
Short name T481
Test name
Test status
Simulation time 3585151361 ps
CPU time 89.25 seconds
Started Jul 04 04:52:08 PM PDT 24
Finished Jul 04 04:53:37 PM PDT 24
Peak memory 328388 kb
Host smart-db2ab178-2a95-48e5-bbce-850e52a08ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056906336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.1056906336
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.2331369852
Short name T706
Test name
Test status
Simulation time 42799818 ps
CPU time 0.68 seconds
Started Jul 04 04:52:01 PM PDT 24
Finished Jul 04 04:52:02 PM PDT 24
Peak memory 204428 kb
Host smart-50c82aa2-1ac0-4d42-9138-96fc28627c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331369852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2331369852
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.4009723699
Short name T591
Test name
Test status
Simulation time 77516651360 ps
CPU time 148.94 seconds
Started Jul 04 04:52:06 PM PDT 24
Finished Jul 04 04:54:35 PM PDT 24
Peak memory 204864 kb
Host smart-8ac4a099-0c5d-401c-8218-32b53ad0c8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009723699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.4009723699
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.4136054073
Short name T487
Test name
Test status
Simulation time 6049719489 ps
CPU time 100.96 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:53:41 PM PDT 24
Peak memory 753104 kb
Host smart-5643be80-fed9-4388-8372-fab92bf8ba94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136054073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.4136054073
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2566107048
Short name T1514
Test name
Test status
Simulation time 5195124271 ps
CPU time 30.16 seconds
Started Jul 04 04:51:57 PM PDT 24
Finished Jul 04 04:52:28 PM PDT 24
Peak memory 361696 kb
Host smart-cce1b099-bfdf-4792-98cb-c0ecd8432322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566107048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2566107048
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.1796027610
Short name T535
Test name
Test status
Simulation time 11134802032 ps
CPU time 223.98 seconds
Started Jul 04 04:52:03 PM PDT 24
Finished Jul 04 04:55:47 PM PDT 24
Peak memory 779628 kb
Host smart-a0cb47d3-0621-4724-b32b-2eb3302034f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796027610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.1796027610
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2374752364
Short name T1240
Test name
Test status
Simulation time 2459844788 ps
CPU time 51.47 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:52:52 PM PDT 24
Peak memory 214404 kb
Host smart-9f5d7c63-b0b9-471b-b794-b8f76f2be85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374752364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2374752364
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2287362744
Short name T189
Test name
Test status
Simulation time 69418739 ps
CPU time 0.88 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:52:09 PM PDT 24
Peak memory 222088 kb
Host smart-ff1384e8-743c-4a7d-8808-30c2e628dc95
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287362744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2287362744
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.1187466459
Short name T403
Test name
Test status
Simulation time 4078446940 ps
CPU time 6.04 seconds
Started Jul 04 04:52:05 PM PDT 24
Finished Jul 04 04:52:11 PM PDT 24
Peak memory 212976 kb
Host smart-313ac041-e114-4a62-aad4-e1150b6ac790
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187466459 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1187466459
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.4131249821
Short name T536
Test name
Test status
Simulation time 899223443 ps
CPU time 1.68 seconds
Started Jul 04 04:52:08 PM PDT 24
Finished Jul 04 04:52:10 PM PDT 24
Peak memory 210512 kb
Host smart-7304dbdf-7d1b-4827-90d8-d0d5b2c34731
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131249821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.4131249821
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.3474423498
Short name T1361
Test name
Test status
Simulation time 266068543 ps
CPU time 1.45 seconds
Started Jul 04 04:52:06 PM PDT 24
Finished Jul 04 04:52:07 PM PDT 24
Peak memory 212912 kb
Host smart-ac7ac425-d9c5-42b6-a9ca-f5571ede9736
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474423498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.3474423498
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.72462050
Short name T1390
Test name
Test status
Simulation time 325292959 ps
CPU time 1.37 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:52:09 PM PDT 24
Peak memory 204468 kb
Host smart-54c0788d-ffb2-4678-ba76-df096eab373c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72462050 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.72462050
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.2463784331
Short name T1313
Test name
Test status
Simulation time 1413061002 ps
CPU time 1.35 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:52:08 PM PDT 24
Peak memory 204500 kb
Host smart-9ca76385-0225-407a-abe1-9a3fe232fdae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463784331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.2463784331
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.2303098281
Short name T13
Test name
Test status
Simulation time 8236386047 ps
CPU time 10.61 seconds
Started Jul 04 04:52:06 PM PDT 24
Finished Jul 04 04:52:17 PM PDT 24
Peak memory 213540 kb
Host smart-03d51b12-465c-4751-bee2-9834b0aa6731
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303098281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.2303098281
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.3148195823
Short name T546
Test name
Test status
Simulation time 279908840 ps
CPU time 3.12 seconds
Started Jul 04 04:52:14 PM PDT 24
Finished Jul 04 04:52:18 PM PDT 24
Peak memory 204692 kb
Host smart-6a8d3a43-df08-41e2-8479-47ba50458ae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148195823 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.3148195823
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3045074032
Short name T836
Test name
Test status
Simulation time 3257958516 ps
CPU time 5.33 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:52:13 PM PDT 24
Peak memory 213000 kb
Host smart-2cf947c9-26f3-467b-85ae-f58de4637bcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045074032 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3045074032
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.3702364593
Short name T1104
Test name
Test status
Simulation time 19894236251 ps
CPU time 54 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:53:02 PM PDT 24
Peak memory 882440 kb
Host smart-d40d764b-7249-4cba-af68-ee0e77a95b83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702364593 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3702364593
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.3755728666
Short name T175
Test name
Test status
Simulation time 4310987519 ps
CPU time 22.84 seconds
Started Jul 04 04:51:58 PM PDT 24
Finished Jul 04 04:52:21 PM PDT 24
Peak memory 205156 kb
Host smart-be63dc3b-5c53-4c7d-9c0b-229d4c301598
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755728666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.3755728666
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.1690515598
Short name T298
Test name
Test status
Simulation time 1305023168 ps
CPU time 58.78 seconds
Started Jul 04 04:52:01 PM PDT 24
Finished Jul 04 04:53:00 PM PDT 24
Peak memory 205500 kb
Host smart-7c0d9df9-9f63-4a00-a3f1-dadfe9e9e462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690515598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.1690515598
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.555058827
Short name T872
Test name
Test status
Simulation time 8866816168 ps
CPU time 18.03 seconds
Started Jul 04 04:51:58 PM PDT 24
Finished Jul 04 04:52:16 PM PDT 24
Peak memory 204740 kb
Host smart-0a41347c-7b9b-433b-a606-66af876ef625
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555058827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_wr.555058827
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.3748921662
Short name T672
Test name
Test status
Simulation time 5844176301 ps
CPU time 23.41 seconds
Started Jul 04 04:52:00 PM PDT 24
Finished Jul 04 04:52:24 PM PDT 24
Peak memory 463992 kb
Host smart-22859680-3587-473a-ab32-40c58112f520
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748921662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.3748921662
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.2808342084
Short name T19
Test name
Test status
Simulation time 1534507552 ps
CPU time 18.33 seconds
Started Jul 04 04:52:09 PM PDT 24
Finished Jul 04 04:52:28 PM PDT 24
Peak memory 204712 kb
Host smart-640f046f-c342-44f2-b783-f97cc8e2ea7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808342084 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.2808342084
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_alert_test.1490081773
Short name T500
Test name
Test status
Simulation time 39808183 ps
CPU time 0.64 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:53:40 PM PDT 24
Peak memory 204152 kb
Host smart-2f715436-3054-4023-aed8-8a4130fa9367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490081773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.1490081773
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.824318956
Short name T1251
Test name
Test status
Simulation time 204748380 ps
CPU time 7.42 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:43 PM PDT 24
Peak memory 204792 kb
Host smart-568ccc7d-a4e6-41b5-a6b5-9122e4bd6863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824318956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.824318956
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.970297658
Short name T505
Test name
Test status
Simulation time 274931042 ps
CPU time 6.07 seconds
Started Jul 04 04:53:33 PM PDT 24
Finished Jul 04 04:53:39 PM PDT 24
Peak memory 240436 kb
Host smart-6ddb23d4-3111-46a7-814b-4494765907f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970297658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.970297658
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1225113276
Short name T1312
Test name
Test status
Simulation time 2503924156 ps
CPU time 85.41 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:55:00 PM PDT 24
Peak memory 639344 kb
Host smart-ec9cee41-7ce8-4644-985b-4303671ce696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225113276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1225113276
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.4007002299
Short name T885
Test name
Test status
Simulation time 16822225111 ps
CPU time 30.94 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:54:07 PM PDT 24
Peak memory 228200 kb
Host smart-ca3cd020-0859-41ad-a856-19ea314e8d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007002299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.4007002299
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3883920038
Short name T615
Test name
Test status
Simulation time 1841812272 ps
CPU time 1.1 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:53:41 PM PDT 24
Peak memory 204412 kb
Host smart-6db2c0e1-2d23-4cd1-91af-a9a2acc1ef6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883920038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3883920038
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.2316118282
Short name T922
Test name
Test status
Simulation time 628824464 ps
CPU time 5.7 seconds
Started Jul 04 04:53:33 PM PDT 24
Finished Jul 04 04:53:39 PM PDT 24
Peak memory 239652 kb
Host smart-be02fd5d-7379-4223-9810-41bb13e0430b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316118282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.2316118282
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2694906119
Short name T1302
Test name
Test status
Simulation time 10176857196 ps
CPU time 142.46 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:55:58 PM PDT 24
Peak memory 1332796 kb
Host smart-bdae1f2a-0511-475f-b12f-9b1ffba5a74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694906119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2694906119
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.734577083
Short name T1505
Test name
Test status
Simulation time 813356719 ps
CPU time 6.6 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:53:46 PM PDT 24
Peak memory 204540 kb
Host smart-a462924e-66eb-458a-a9fc-90f62a48bc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734577083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.734577083
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.1806995570
Short name T886
Test name
Test status
Simulation time 4426114842 ps
CPU time 112.8 seconds
Started Jul 04 04:53:33 PM PDT 24
Finished Jul 04 04:55:26 PM PDT 24
Peak memory 489312 kb
Host smart-15379656-fbca-4f62-9eed-07345f8e54ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806995570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.1806995570
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.2762511604
Short name T611
Test name
Test status
Simulation time 47122926 ps
CPU time 0.69 seconds
Started Jul 04 04:53:33 PM PDT 24
Finished Jul 04 04:53:34 PM PDT 24
Peak memory 204408 kb
Host smart-ea7521e3-8dbc-4815-9544-5f0f39a3e04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762511604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.2762511604
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.678041582
Short name T725
Test name
Test status
Simulation time 984526038 ps
CPU time 10.07 seconds
Started Jul 04 04:53:32 PM PDT 24
Finished Jul 04 04:53:42 PM PDT 24
Peak memory 222332 kb
Host smart-8308ea4d-c0f5-432a-9cda-637e5d4a8b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678041582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.678041582
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.1883163878
Short name T418
Test name
Test status
Simulation time 57353082 ps
CPU time 1.08 seconds
Started Jul 04 04:53:33 PM PDT 24
Finished Jul 04 04:53:35 PM PDT 24
Peak memory 222380 kb
Host smart-6b5ef721-8ffe-47e1-815d-cb8c0a3a04de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883163878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.1883163878
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.2979657442
Short name T1221
Test name
Test status
Simulation time 4651785761 ps
CPU time 24.43 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:54:00 PM PDT 24
Peak memory 352672 kb
Host smart-2b27cc1f-a086-4eed-bd35-c87fac57dd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979657442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.2979657442
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.9305555
Short name T132
Test name
Test status
Simulation time 31216322674 ps
CPU time 300.84 seconds
Started Jul 04 04:53:33 PM PDT 24
Finished Jul 04 04:58:34 PM PDT 24
Peak memory 1162500 kb
Host smart-174d1a3f-b570-45b1-bb4d-091bf7633dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9305555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.9305555
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.2720743744
Short name T686
Test name
Test status
Simulation time 1501711377 ps
CPU time 6.96 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:43 PM PDT 24
Peak memory 212880 kb
Host smart-5709d0fa-f90e-49c8-be32-3fc5dea541ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720743744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2720743744
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.3329413999
Short name T1371
Test name
Test status
Simulation time 5327465845 ps
CPU time 3.73 seconds
Started Jul 04 04:53:32 PM PDT 24
Finished Jul 04 04:53:36 PM PDT 24
Peak memory 213016 kb
Host smart-ca132c51-a6db-4250-8adc-08b6eff808fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329413999 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3329413999
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.707598763
Short name T236
Test name
Test status
Simulation time 311925635 ps
CPU time 0.94 seconds
Started Jul 04 04:53:37 PM PDT 24
Finished Jul 04 04:53:38 PM PDT 24
Peak memory 212684 kb
Host smart-f5daeefb-d11e-4d16-9eda-2630960afa31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707598763 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_acq.707598763
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.824601275
Short name T259
Test name
Test status
Simulation time 509519518 ps
CPU time 1.15 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:37 PM PDT 24
Peak memory 204608 kb
Host smart-7f40a4e2-efba-4cb6-8d49-cecec4ac8d13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824601275 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_fifo_reset_tx.824601275
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.724257017
Short name T1309
Test name
Test status
Simulation time 492961464 ps
CPU time 2.77 seconds
Started Jul 04 04:53:34 PM PDT 24
Finished Jul 04 04:53:37 PM PDT 24
Peak memory 204720 kb
Host smart-403a43d7-9d1e-4044-99da-95dbd7d73021
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724257017 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.724257017
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.262661117
Short name T312
Test name
Test status
Simulation time 143965961 ps
CPU time 1.23 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:37 PM PDT 24
Peak memory 204504 kb
Host smart-fc7fe92d-f125-4f0c-a214-58b6577b84a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262661117 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.262661117
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.2859348774
Short name T1405
Test name
Test status
Simulation time 367913548 ps
CPU time 3 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:38 PM PDT 24
Peak memory 204792 kb
Host smart-ea48b52d-0d34-426e-9374-dbf9e5e72d52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859348774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.2859348774
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.2875816252
Short name T818
Test name
Test status
Simulation time 1215398220 ps
CPU time 6.69 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:53:47 PM PDT 24
Peak memory 220992 kb
Host smart-9e8b6345-de73-4c3a-b667-e7faa0262051
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875816252 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.2875816252
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.2296293915
Short name T548
Test name
Test status
Simulation time 21332987447 ps
CPU time 140.97 seconds
Started Jul 04 04:53:33 PM PDT 24
Finished Jul 04 04:55:54 PM PDT 24
Peak memory 1900820 kb
Host smart-3c7fc812-d916-413c-9f4d-84d8e0704f85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296293915 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.2296293915
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2204454331
Short name T882
Test name
Test status
Simulation time 1236503322 ps
CPU time 8.72 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:45 PM PDT 24
Peak memory 204784 kb
Host smart-775941eb-40e7-4097-a16c-a807ca196539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204454331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2204454331
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.1143617418
Short name T358
Test name
Test status
Simulation time 2299666576 ps
CPU time 7.87 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:44 PM PDT 24
Peak memory 209448 kb
Host smart-d36066d6-b6d7-41cf-a676-1727ee025b16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143617418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.1143617418
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.3005810515
Short name T306
Test name
Test status
Simulation time 44390423234 ps
CPU time 33.7 seconds
Started Jul 04 04:53:34 PM PDT 24
Finished Jul 04 04:54:08 PM PDT 24
Peak memory 680308 kb
Host smart-1dce3ccf-5890-4683-9330-05128aac2bf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005810515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.3005810515
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.253314741
Short name T1042
Test name
Test status
Simulation time 21013470957 ps
CPU time 231.58 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:57:27 PM PDT 24
Peak memory 917352 kb
Host smart-198ec642-a0f4-4c70-93d1-c2854be041d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253314741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_t
arget_stretch.253314741
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.2910306552
Short name T577
Test name
Test status
Simulation time 915039084 ps
CPU time 9.83 seconds
Started Jul 04 04:53:36 PM PDT 24
Finished Jul 04 04:53:47 PM PDT 24
Peak memory 204672 kb
Host smart-77e89bb0-23bc-4c2f-baec-3337957ad59a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910306552 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.2910306552
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.3819236645
Short name T981
Test name
Test status
Simulation time 68454151 ps
CPU time 0.68 seconds
Started Jul 04 04:53:41 PM PDT 24
Finished Jul 04 04:53:43 PM PDT 24
Peak memory 204356 kb
Host smart-6a58e171-6f86-4012-8ee2-371fa384aaf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819236645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3819236645
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.2490476739
Short name T470
Test name
Test status
Simulation time 605619497 ps
CPU time 1.83 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:38 PM PDT 24
Peak memory 212904 kb
Host smart-dcecedd5-0459-4ec9-8762-c7d91d598d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490476739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2490476739
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.3405033169
Short name T1530
Test name
Test status
Simulation time 297908694 ps
CPU time 15.43 seconds
Started Jul 04 04:53:34 PM PDT 24
Finished Jul 04 04:53:50 PM PDT 24
Peak memory 263820 kb
Host smart-0cd922ec-14d4-456e-b342-0fd2d6696072
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405033169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.3405033169
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1730030501
Short name T1174
Test name
Test status
Simulation time 9404926678 ps
CPU time 145.46 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:56:01 PM PDT 24
Peak memory 722604 kb
Host smart-670f5a88-9c44-4a12-8347-a2f7640ccb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730030501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1730030501
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.3961670665
Short name T802
Test name
Test status
Simulation time 2880379764 ps
CPU time 74.43 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:54:50 PM PDT 24
Peak memory 474196 kb
Host smart-a1e654e3-ffe3-4020-b788-1001ef4b66c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961670665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3961670665
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1256018530
Short name T237
Test name
Test status
Simulation time 93401599 ps
CPU time 0.86 seconds
Started Jul 04 04:53:30 PM PDT 24
Finished Jul 04 04:53:31 PM PDT 24
Peak memory 204324 kb
Host smart-890c88aa-c8bc-4c10-b1ee-e24c923d2e62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256018530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.1256018530
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.1244876485
Short name T1445
Test name
Test status
Simulation time 377301803 ps
CPU time 5.29 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:53:45 PM PDT 24
Peak memory 204716 kb
Host smart-16acabb1-075a-405b-85a7-aea5dc454d2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244876485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.1244876485
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.2214161650
Short name T1027
Test name
Test status
Simulation time 3730459631 ps
CPU time 233.87 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:57:30 PM PDT 24
Peak memory 1051264 kb
Host smart-88ee5d7d-d78f-4682-85a1-45230a4a2625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214161650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.2214161650
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.1691334063
Short name T1173
Test name
Test status
Simulation time 1497868756 ps
CPU time 5.7 seconds
Started Jul 04 04:53:38 PM PDT 24
Finished Jul 04 04:53:44 PM PDT 24
Peak memory 204684 kb
Host smart-836ebc39-10da-4ea9-a9cf-b45af489a2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691334063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.1691334063
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.3709813677
Short name T1293
Test name
Test status
Simulation time 9820196287 ps
CPU time 34.99 seconds
Started Jul 04 04:53:38 PM PDT 24
Finished Jul 04 04:54:13 PM PDT 24
Peak memory 439396 kb
Host smart-d00d7928-ba36-4e45-8427-0ddb98f2fa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709813677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3709813677
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.1981082362
Short name T1275
Test name
Test status
Simulation time 93532685 ps
CPU time 0.68 seconds
Started Jul 04 04:53:37 PM PDT 24
Finished Jul 04 04:53:38 PM PDT 24
Peak memory 204380 kb
Host smart-4c16e4d7-1d41-40bc-a00a-724470cbae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981082362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1981082362
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.348443965
Short name T30
Test name
Test status
Simulation time 6758590549 ps
CPU time 44.49 seconds
Started Jul 04 04:53:33 PM PDT 24
Finished Jul 04 04:54:18 PM PDT 24
Peak memory 597564 kb
Host smart-18d04d93-f901-4245-a64c-6db65c6412e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348443965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.348443965
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.2310873714
Short name T1324
Test name
Test status
Simulation time 74022473 ps
CPU time 1.76 seconds
Started Jul 04 04:53:33 PM PDT 24
Finished Jul 04 04:53:35 PM PDT 24
Peak memory 212844 kb
Host smart-86fc1c66-8194-4541-b7d0-80edad283b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310873714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.2310873714
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.706321782
Short name T1446
Test name
Test status
Simulation time 3341284478 ps
CPU time 34.06 seconds
Started Jul 04 04:53:36 PM PDT 24
Finished Jul 04 04:54:11 PM PDT 24
Peak memory 359724 kb
Host smart-f7a94b9b-446a-4ad1-ab1a-4271a05c7951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706321782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.706321782
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.3419492992
Short name T270
Test name
Test status
Simulation time 114453223818 ps
CPU time 569.44 seconds
Started Jul 04 04:53:37 PM PDT 24
Finished Jul 04 05:03:07 PM PDT 24
Peak memory 2419844 kb
Host smart-5cd4279a-d31c-4ddc-b450-767423721da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419492992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.3419492992
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.2974800698
Short name T1508
Test name
Test status
Simulation time 890070225 ps
CPU time 14.66 seconds
Started Jul 04 04:53:37 PM PDT 24
Finished Jul 04 04:53:52 PM PDT 24
Peak memory 212952 kb
Host smart-02f5e68b-b5c7-450e-86e1-6f8bd4da11c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974800698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2974800698
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.1960917303
Short name T1440
Test name
Test status
Simulation time 1728658106 ps
CPU time 4.67 seconds
Started Jul 04 04:53:38 PM PDT 24
Finished Jul 04 04:53:43 PM PDT 24
Peak memory 212836 kb
Host smart-0a10a15c-d312-4924-b938-2092445371f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960917303 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.1960917303
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.607627145
Short name T86
Test name
Test status
Simulation time 690534106 ps
CPU time 1.34 seconds
Started Jul 04 04:53:36 PM PDT 24
Finished Jul 04 04:53:38 PM PDT 24
Peak memory 204612 kb
Host smart-2e8e6b8c-fd18-4ebd-a6a5-a9407a3f3c88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607627145 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_acq.607627145
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1659927223
Short name T776
Test name
Test status
Simulation time 280954413 ps
CPU time 1.6 seconds
Started Jul 04 04:53:36 PM PDT 24
Finished Jul 04 04:53:39 PM PDT 24
Peak memory 206704 kb
Host smart-e686a25d-f3ea-4017-a7a3-8730d6bd9ab7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659927223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.1659927223
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.3872236677
Short name T399
Test name
Test status
Simulation time 352676504 ps
CPU time 0.99 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:53:41 PM PDT 24
Peak memory 204496 kb
Host smart-ea102796-8dcd-4798-b465-e37cea02de9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872236677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.3872236677
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.158957056
Short name T1249
Test name
Test status
Simulation time 1220911606 ps
CPU time 6.19 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:42 PM PDT 24
Peak memory 212724 kb
Host smart-1721fc16-8e36-4840-a334-704281ddf551
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158957056 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_intr_smoke.158957056
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.1410358817
Short name T290
Test name
Test status
Simulation time 3191700457 ps
CPU time 4.13 seconds
Started Jul 04 04:53:37 PM PDT 24
Finished Jul 04 04:53:41 PM PDT 24
Peak memory 204776 kb
Host smart-eb37e3e0-bbe3-4376-bfe2-278bffd61304
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410358817 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.1410358817
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.1626498020
Short name T460
Test name
Test status
Simulation time 1082159668 ps
CPU time 18.57 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:53:58 PM PDT 24
Peak memory 204704 kb
Host smart-c45ec5db-6f41-492b-b856-49730704cdbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626498020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.1626498020
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1353003897
Short name T1155
Test name
Test status
Simulation time 7470414458 ps
CPU time 43.1 seconds
Started Jul 04 04:53:37 PM PDT 24
Finished Jul 04 04:54:20 PM PDT 24
Peak memory 204840 kb
Host smart-28ead513-b4f4-4d82-9eb8-cac86ac53ab2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353003897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1353003897
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.1277028734
Short name T362
Test name
Test status
Simulation time 29098494416 ps
CPU time 162.96 seconds
Started Jul 04 04:53:37 PM PDT 24
Finished Jul 04 04:56:21 PM PDT 24
Peak memory 2318740 kb
Host smart-eb977a82-4596-46a2-aa6c-5c44589229c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277028734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.1277028734
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.2996325550
Short name T594
Test name
Test status
Simulation time 36764306404 ps
CPU time 225.34 seconds
Started Jul 04 04:53:38 PM PDT 24
Finished Jul 04 04:57:24 PM PDT 24
Peak memory 2178264 kb
Host smart-e7f28b18-35cb-4a05-a784-df8fb6f306ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996325550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.2996325550
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.7951647
Short name T517
Test name
Test status
Simulation time 1275503734 ps
CPU time 7.45 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:44 PM PDT 24
Peak memory 212944 kb
Host smart-8a15566a-df05-4404-ac1b-7fca61fecc53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7951647 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_timeout.7951647
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.1033914993
Short name T1010
Test name
Test status
Simulation time 377166864 ps
CPU time 5.13 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:53:45 PM PDT 24
Peak memory 204720 kb
Host smart-599b06c6-e078-4bcc-b4b7-d80add37eb5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033914993 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.1033914993
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3006317302
Short name T438
Test name
Test status
Simulation time 15274269 ps
CPU time 0.61 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:53:40 PM PDT 24
Peak memory 204336 kb
Host smart-d696bc08-fd74-4b74-8fd2-97d190ddce4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006317302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3006317302
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.1421885943
Short name T1195
Test name
Test status
Simulation time 480519564 ps
CPU time 1.77 seconds
Started Jul 04 04:53:38 PM PDT 24
Finished Jul 04 04:53:40 PM PDT 24
Peak memory 212940 kb
Host smart-9dd1e03b-19ac-4539-9b98-856ffc3a1ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421885943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.1421885943
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.786686300
Short name T1126
Test name
Test status
Simulation time 859869435 ps
CPU time 10.97 seconds
Started Jul 04 04:53:36 PM PDT 24
Finished Jul 04 04:53:48 PM PDT 24
Peak memory 240912 kb
Host smart-988c34c6-4606-4860-8d7b-3fcb1f20e8eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786686300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empt
y.786686300
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.1030371873
Short name T717
Test name
Test status
Simulation time 4690005216 ps
CPU time 65.96 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:54:42 PM PDT 24
Peak memory 503808 kb
Host smart-48f47fea-6bbd-4ea9-b587-01783a1df32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030371873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.1030371873
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.3435498815
Short name T1376
Test name
Test status
Simulation time 13006955974 ps
CPU time 42.7 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:54:22 PM PDT 24
Peak memory 563332 kb
Host smart-c001ad51-c754-4cdf-b4ef-c322736c6dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435498815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3435498815
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.3432986125
Short name T644
Test name
Test status
Simulation time 144242531 ps
CPU time 0.83 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:37 PM PDT 24
Peak memory 204356 kb
Host smart-0e6e1ae2-c96e-4e5f-9a43-b839481a7238
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432986125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.3432986125
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3520890569
Short name T1217
Test name
Test status
Simulation time 704373951 ps
CPU time 9.62 seconds
Started Jul 04 04:53:33 PM PDT 24
Finished Jul 04 04:53:43 PM PDT 24
Peak memory 234572 kb
Host smart-6ed29f5d-6b02-4072-8456-d6a6343a9eb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520890569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3520890569
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.2008343997
Short name T160
Test name
Test status
Simulation time 29972544522 ps
CPU time 99.7 seconds
Started Jul 04 04:53:38 PM PDT 24
Finished Jul 04 04:55:18 PM PDT 24
Peak memory 1102016 kb
Host smart-09ab0b1e-6a55-4410-8997-462997266df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008343997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2008343997
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.588944880
Short name T659
Test name
Test status
Simulation time 358036119 ps
CPU time 8.46 seconds
Started Jul 04 04:53:40 PM PDT 24
Finished Jul 04 04:53:50 PM PDT 24
Peak memory 204780 kb
Host smart-873e1d82-c3cf-460b-b26c-4aa815da8e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588944880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.588944880
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.2326586809
Short name T352
Test name
Test status
Simulation time 1635680708 ps
CPU time 30.18 seconds
Started Jul 04 04:53:38 PM PDT 24
Finished Jul 04 04:54:09 PM PDT 24
Peak memory 348800 kb
Host smart-0bb33246-8719-4445-a58c-f94f60bfd8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326586809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2326586809
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.421965269
Short name T240
Test name
Test status
Simulation time 27635841 ps
CPU time 0.69 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:36 PM PDT 24
Peak memory 204420 kb
Host smart-3f91a1f6-3489-46bb-a0ae-b67b0dfcdf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421965269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.421965269
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.3524343189
Short name T1125
Test name
Test status
Simulation time 1350931509 ps
CPU time 16.67 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:53:57 PM PDT 24
Peak memory 313724 kb
Host smart-bd6a7d11-1247-4c45-8af8-03f1733527c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524343189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.3524343189
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.3197287326
Short name T1373
Test name
Test status
Simulation time 5842836202 ps
CPU time 251.16 seconds
Started Jul 04 04:53:37 PM PDT 24
Finished Jul 04 04:57:49 PM PDT 24
Peak memory 204780 kb
Host smart-2e8d59d1-719c-44b5-a571-4476c4d7cd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197287326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.3197287326
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.108504030
Short name T1258
Test name
Test status
Simulation time 1693714858 ps
CPU time 33.9 seconds
Started Jul 04 04:53:41 PM PDT 24
Finished Jul 04 04:54:16 PM PDT 24
Peak memory 358720 kb
Host smart-52f4b980-1ac0-40d0-a571-e690b8e966ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108504030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.108504030
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.643499496
Short name T131
Test name
Test status
Simulation time 6103617859 ps
CPU time 181.04 seconds
Started Jul 04 04:53:36 PM PDT 24
Finished Jul 04 04:56:38 PM PDT 24
Peak memory 1040088 kb
Host smart-c045eda0-a02d-41a4-acc6-d1f25ac8b190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643499496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.643499496
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3643615564
Short name T1472
Test name
Test status
Simulation time 2348867639 ps
CPU time 12.12 seconds
Started Jul 04 04:53:36 PM PDT 24
Finished Jul 04 04:53:49 PM PDT 24
Peak memory 214528 kb
Host smart-bb0cbf2e-03aa-4728-90b7-48b0d76d0622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643615564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3643615564
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2815567871
Short name T793
Test name
Test status
Simulation time 898903886 ps
CPU time 5.03 seconds
Started Jul 04 04:53:41 PM PDT 24
Finished Jul 04 04:53:47 PM PDT 24
Peak memory 212952 kb
Host smart-bc2ec582-8e7d-4bbf-8fc6-95f475dd70a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815567871 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2815567871
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.3256267463
Short name T953
Test name
Test status
Simulation time 231024056 ps
CPU time 0.99 seconds
Started Jul 04 04:53:40 PM PDT 24
Finished Jul 04 04:53:42 PM PDT 24
Peak memory 204532 kb
Host smart-801434fd-41d6-475e-954c-3f569bb5e9fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256267463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.3256267463
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.722786161
Short name T1527
Test name
Test status
Simulation time 683258441 ps
CPU time 1.24 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:53:41 PM PDT 24
Peak memory 204688 kb
Host smart-8ef3dd73-e50b-4cff-bc9a-061cc294e92c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722786161 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.722786161
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.3693637763
Short name T666
Test name
Test status
Simulation time 5375339061 ps
CPU time 2.3 seconds
Started Jul 04 04:53:36 PM PDT 24
Finished Jul 04 04:53:39 PM PDT 24
Peak memory 204832 kb
Host smart-1c315721-2daa-4144-a3c0-b98e2957074e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693637763 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.3693637763
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.1436801849
Short name T1449
Test name
Test status
Simulation time 192106376 ps
CPU time 1.02 seconds
Started Jul 04 04:53:41 PM PDT 24
Finished Jul 04 04:53:43 PM PDT 24
Peak memory 204508 kb
Host smart-5cd78f5b-5d34-4b27-8973-4b4d2753170f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436801849 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.1436801849
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3726994992
Short name T1157
Test name
Test status
Simulation time 407672197 ps
CPU time 5.08 seconds
Started Jul 04 04:53:41 PM PDT 24
Finished Jul 04 04:53:47 PM PDT 24
Peak memory 204704 kb
Host smart-8ff5a4ce-72bc-4016-8b2e-6399edc1459f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726994992 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3726994992
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3939327138
Short name T261
Test name
Test status
Simulation time 897826783 ps
CPU time 4.96 seconds
Started Jul 04 04:53:37 PM PDT 24
Finished Jul 04 04:53:43 PM PDT 24
Peak memory 207720 kb
Host smart-44744c4c-8133-480d-823e-c334a29e6b92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939327138 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3939327138
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.4215561016
Short name T808
Test name
Test status
Simulation time 17277788090 ps
CPU time 329.42 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:59:05 PM PDT 24
Peak memory 4169772 kb
Host smart-03f0fd9e-001e-492e-8d5f-afa8a1cb183f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215561016 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.4215561016
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.3009561819
Short name T486
Test name
Test status
Simulation time 1068383801 ps
CPU time 15.32 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:53:55 PM PDT 24
Peak memory 204652 kb
Host smart-4410df65-e1b5-48ea-a458-02f52150c493
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009561819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.3009561819
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1581004876
Short name T1038
Test name
Test status
Simulation time 5963647603 ps
CPU time 23.98 seconds
Started Jul 04 04:53:40 PM PDT 24
Finished Jul 04 04:54:05 PM PDT 24
Peak memory 222700 kb
Host smart-9fbb4173-29d4-444b-9440-595af7b3c36e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581004876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1581004876
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.1319381448
Short name T602
Test name
Test status
Simulation time 51357470957 ps
CPU time 741.98 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 05:05:58 PM PDT 24
Peak memory 5234672 kb
Host smart-c5f69ddb-5c2c-4fc3-947b-4a97de28d3ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319381448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.1319381448
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.1981022502
Short name T760
Test name
Test status
Simulation time 12822463088 ps
CPU time 536.55 seconds
Started Jul 04 04:53:33 PM PDT 24
Finished Jul 04 05:02:30 PM PDT 24
Peak memory 3081124 kb
Host smart-f05217f9-c620-46c3-acbe-f7bbd4764db9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981022502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.1981022502
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.33904518
Short name T738
Test name
Test status
Simulation time 2143637339 ps
CPU time 7.23 seconds
Started Jul 04 04:53:38 PM PDT 24
Finished Jul 04 04:53:45 PM PDT 24
Peak memory 211052 kb
Host smart-81df246e-1edd-40e7-b0ab-122c24578a27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33904518 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_timeout.33904518
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.3335979791
Short name T138
Test name
Test status
Simulation time 68049544 ps
CPU time 1.56 seconds
Started Jul 04 04:53:39 PM PDT 24
Finished Jul 04 04:53:42 PM PDT 24
Peak memory 204744 kb
Host smart-3b5f726f-ab48-4500-b3a1-a072ec3301f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335979791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.3335979791
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.869227483
Short name T426
Test name
Test status
Simulation time 43886011 ps
CPU time 0.63 seconds
Started Jul 04 04:53:48 PM PDT 24
Finished Jul 04 04:53:49 PM PDT 24
Peak memory 204356 kb
Host smart-4cd39653-aca4-4ab9-aa41-36050a75213c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869227483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.869227483
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.4052498065
Short name T40
Test name
Test status
Simulation time 104868472 ps
CPU time 3.34 seconds
Started Jul 04 04:53:45 PM PDT 24
Finished Jul 04 04:53:49 PM PDT 24
Peak memory 221136 kb
Host smart-7b05228b-efb5-44c4-867c-ec8ea6917629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052498065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.4052498065
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.365516147
Short name T976
Test name
Test status
Simulation time 4363462329 ps
CPU time 25.63 seconds
Started Jul 04 04:53:40 PM PDT 24
Finished Jul 04 04:54:07 PM PDT 24
Peak memory 316748 kb
Host smart-d71c6d33-099e-4d35-9523-f257710e480d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365516147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empt
y.365516147
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1761576944
Short name T137
Test name
Test status
Simulation time 2654793274 ps
CPU time 95.45 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:55:10 PM PDT 24
Peak memory 846560 kb
Host smart-91f45496-03bf-4778-9516-3b139e7f0038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761576944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1761576944
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.901452691
Short name T571
Test name
Test status
Simulation time 4771004418 ps
CPU time 61.65 seconds
Started Jul 04 04:53:40 PM PDT 24
Finished Jul 04 04:54:43 PM PDT 24
Peak memory 587024 kb
Host smart-bcc4ee71-9f22-418e-a19b-9310de712e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901452691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.901452691
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.1658313656
Short name T427
Test name
Test status
Simulation time 120246100 ps
CPU time 0.9 seconds
Started Jul 04 04:53:41 PM PDT 24
Finished Jul 04 04:53:43 PM PDT 24
Peak memory 204356 kb
Host smart-39b127f0-423e-490a-9248-40a0fee3d789
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658313656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.1658313656
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.660237114
Short name T1154
Test name
Test status
Simulation time 222030390 ps
CPU time 10.91 seconds
Started Jul 04 04:53:45 PM PDT 24
Finished Jul 04 04:53:56 PM PDT 24
Peak memory 204648 kb
Host smart-83ea6ce6-12bf-4f15-a0f2-53ec809f86e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660237114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.
660237114
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.3162493561
Short name T537
Test name
Test status
Simulation time 8100987614 ps
CPU time 277.74 seconds
Started Jul 04 04:53:41 PM PDT 24
Finished Jul 04 04:58:20 PM PDT 24
Peak memory 1196760 kb
Host smart-a86d39f5-cbf3-435d-bd9f-e298f9a0c70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162493561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3162493561
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.273642385
Short name T1066
Test name
Test status
Simulation time 1493629792 ps
CPU time 13.76 seconds
Started Jul 04 04:53:48 PM PDT 24
Finished Jul 04 04:54:02 PM PDT 24
Peak memory 204788 kb
Host smart-d080d27c-b5df-404f-ab38-76da3c255191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273642385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.273642385
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.1066163731
Short name T978
Test name
Test status
Simulation time 17369350649 ps
CPU time 19 seconds
Started Jul 04 04:53:43 PM PDT 24
Finished Jul 04 04:54:02 PM PDT 24
Peak memory 309188 kb
Host smart-1c441c73-1eb4-466c-ab5a-ec66c0db5d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066163731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.1066163731
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.2156388827
Short name T934
Test name
Test status
Simulation time 56242715 ps
CPU time 0.67 seconds
Started Jul 04 04:53:40 PM PDT 24
Finished Jul 04 04:53:42 PM PDT 24
Peak memory 204420 kb
Host smart-88362592-058e-4b8a-a722-c5f5bb2a2214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156388827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.2156388827
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.3193469546
Short name T1213
Test name
Test status
Simulation time 7892594559 ps
CPU time 184.25 seconds
Started Jul 04 04:53:41 PM PDT 24
Finished Jul 04 04:56:46 PM PDT 24
Peak memory 531048 kb
Host smart-20798411-fbc4-4f12-807f-faaa486be1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193469546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.3193469546
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.1653426046
Short name T294
Test name
Test status
Simulation time 71354870 ps
CPU time 1.37 seconds
Started Jul 04 04:53:40 PM PDT 24
Finished Jul 04 04:53:43 PM PDT 24
Peak memory 205024 kb
Host smart-ff3ce2b1-499d-4460-baff-6205befe00e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653426046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.1653426046
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.3075671505
Short name T251
Test name
Test status
Simulation time 2378301198 ps
CPU time 16.95 seconds
Started Jul 04 04:53:42 PM PDT 24
Finished Jul 04 04:53:59 PM PDT 24
Peak memory 263948 kb
Host smart-f0e4b065-4e47-4f0c-b969-0701816954a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075671505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3075671505
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.3082836091
Short name T863
Test name
Test status
Simulation time 762182708 ps
CPU time 11.01 seconds
Started Jul 04 04:53:41 PM PDT 24
Finished Jul 04 04:53:52 PM PDT 24
Peak memory 218784 kb
Host smart-a14aa8d8-625d-47bb-ab83-b420d2131e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082836091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.3082836091
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.1409642532
Short name T671
Test name
Test status
Simulation time 601754529 ps
CPU time 3.13 seconds
Started Jul 04 04:53:48 PM PDT 24
Finished Jul 04 04:53:51 PM PDT 24
Peak memory 204696 kb
Host smart-240e5c4b-d4f3-4b7d-a2d1-5f21b93766d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409642532 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1409642532
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.2632857951
Short name T772
Test name
Test status
Simulation time 636709585 ps
CPU time 1.21 seconds
Started Jul 04 04:53:47 PM PDT 24
Finished Jul 04 04:53:48 PM PDT 24
Peak memory 204532 kb
Host smart-662d599c-666c-4d86-8cd4-cb7f9edd0c52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632857951 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.2632857951
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.3129400619
Short name T1159
Test name
Test status
Simulation time 536905670 ps
CPU time 1.24 seconds
Started Jul 04 04:53:48 PM PDT 24
Finished Jul 04 04:53:49 PM PDT 24
Peak memory 212912 kb
Host smart-d464f96e-8209-48ea-8ab5-19d79d67f02b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129400619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.3129400619
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.1581918950
Short name T1049
Test name
Test status
Simulation time 2178087682 ps
CPU time 2.6 seconds
Started Jul 04 04:53:47 PM PDT 24
Finished Jul 04 04:53:50 PM PDT 24
Peak memory 204764 kb
Host smart-201b2c12-e541-4a82-914f-a31e3e8a0913
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581918950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.1581918950
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.2770446546
Short name T299
Test name
Test status
Simulation time 139829939 ps
CPU time 1.28 seconds
Started Jul 04 04:53:48 PM PDT 24
Finished Jul 04 04:53:50 PM PDT 24
Peak memory 204508 kb
Host smart-0376e9b1-39fc-4287-8c63-c1f3b75a47a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770446546 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.2770446546
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.1013118044
Short name T249
Test name
Test status
Simulation time 583288552 ps
CPU time 2.48 seconds
Started Jul 04 04:53:46 PM PDT 24
Finished Jul 04 04:53:49 PM PDT 24
Peak memory 204728 kb
Host smart-c48d5be8-e10f-46bd-9594-aa5c16cb8112
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013118044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.1013118044
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.1760648568
Short name T1506
Test name
Test status
Simulation time 7337497572 ps
CPU time 5.36 seconds
Started Jul 04 04:53:46 PM PDT 24
Finished Jul 04 04:53:51 PM PDT 24
Peak memory 217660 kb
Host smart-e4f3430a-8130-440f-b66d-e14317e2ea49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760648568 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.1760648568
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.1344022533
Short name T1387
Test name
Test status
Simulation time 21014389001 ps
CPU time 46.42 seconds
Started Jul 04 04:53:46 PM PDT 24
Finished Jul 04 04:54:33 PM PDT 24
Peak memory 1100084 kb
Host smart-e716edb2-de8b-407d-84a2-95b64d0d1bb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344022533 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.1344022533
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.1055788369
Short name T729
Test name
Test status
Simulation time 3247191210 ps
CPU time 11.46 seconds
Started Jul 04 04:53:38 PM PDT 24
Finished Jul 04 04:53:50 PM PDT 24
Peak memory 204736 kb
Host smart-5aff36d0-af35-439e-951b-319727283a93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055788369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.1055788369
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.668125013
Short name T816
Test name
Test status
Simulation time 1080204740 ps
CPU time 5.35 seconds
Started Jul 04 04:53:41 PM PDT 24
Finished Jul 04 04:53:47 PM PDT 24
Peak memory 204624 kb
Host smart-f3e84fe0-8785-49c9-96de-1134cb192eb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668125013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_rd.668125013
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.3007344059
Short name T1509
Test name
Test status
Simulation time 36715115425 ps
CPU time 81.08 seconds
Started Jul 04 04:53:47 PM PDT 24
Finished Jul 04 04:55:09 PM PDT 24
Peak memory 373080 kb
Host smart-1f1b1292-7c8f-4d8e-93c8-80332a6b8053
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007344059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.3007344059
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.3098352898
Short name T1121
Test name
Test status
Simulation time 1257822420 ps
CPU time 7.21 seconds
Started Jul 04 04:53:47 PM PDT 24
Finished Jul 04 04:53:55 PM PDT 24
Peak memory 212900 kb
Host smart-602f18c5-05c0-450d-b782-cad1dfbf5eac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098352898 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.3098352898
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.2007237785
Short name T450
Test name
Test status
Simulation time 140498338 ps
CPU time 1.8 seconds
Started Jul 04 04:53:47 PM PDT 24
Finished Jul 04 04:53:49 PM PDT 24
Peak memory 204712 kb
Host smart-01b2c726-f685-479a-8063-f60eccb3ae89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007237785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.2007237785
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3510832384
Short name T1120
Test name
Test status
Simulation time 18421818 ps
CPU time 0.65 seconds
Started Jul 04 04:53:53 PM PDT 24
Finished Jul 04 04:53:54 PM PDT 24
Peak memory 204352 kb
Host smart-a7125db5-4b6c-42b3-a5f1-31c84d0df04b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510832384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3510832384
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.3407721660
Short name T56
Test name
Test status
Simulation time 348723332 ps
CPU time 2.24 seconds
Started Jul 04 04:53:50 PM PDT 24
Finished Jul 04 04:53:52 PM PDT 24
Peak memory 221136 kb
Host smart-dab85c32-ff8e-457d-aea9-6e65ff0ee652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407721660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.3407721660
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.2528104748
Short name T94
Test name
Test status
Simulation time 639036635 ps
CPU time 6.71 seconds
Started Jul 04 04:53:48 PM PDT 24
Finished Jul 04 04:53:55 PM PDT 24
Peak memory 262424 kb
Host smart-be5b7330-bfea-4e7c-84fc-da17d8daad47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528104748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.2528104748
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.571413409
Short name T1272
Test name
Test status
Simulation time 8773651071 ps
CPU time 48.49 seconds
Started Jul 04 04:53:48 PM PDT 24
Finished Jul 04 04:54:37 PM PDT 24
Peak memory 520844 kb
Host smart-436ba82d-3fe8-490d-a13a-777fe018103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571413409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.571413409
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1051255898
Short name T1169
Test name
Test status
Simulation time 125675422 ps
CPU time 0.95 seconds
Started Jul 04 04:53:47 PM PDT 24
Finished Jul 04 04:53:48 PM PDT 24
Peak memory 204376 kb
Host smart-be8da737-b870-4ef6-9157-3b78c7d467f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051255898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.1051255898
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.159228431
Short name T1308
Test name
Test status
Simulation time 558415483 ps
CPU time 4.12 seconds
Started Jul 04 04:53:47 PM PDT 24
Finished Jul 04 04:53:51 PM PDT 24
Peak memory 224520 kb
Host smart-6ddda57f-9a55-4251-9d0d-2c6a64447668
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159228431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.
159228431
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.2722523055
Short name T1496
Test name
Test status
Simulation time 4491966174 ps
CPU time 132.07 seconds
Started Jul 04 04:53:44 PM PDT 24
Finished Jul 04 04:55:57 PM PDT 24
Peak memory 1281252 kb
Host smart-096084b5-2a5e-44f5-86d3-e9f448926aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722523055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2722523055
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.2765985950
Short name T1134
Test name
Test status
Simulation time 3552098421 ps
CPU time 74.29 seconds
Started Jul 04 04:53:55 PM PDT 24
Finished Jul 04 04:55:10 PM PDT 24
Peak memory 363400 kb
Host smart-25bc5a7a-0d22-44b8-8e29-d129971fe87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765985950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.2765985950
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.1905095551
Short name T664
Test name
Test status
Simulation time 206231299 ps
CPU time 0.65 seconds
Started Jul 04 04:53:47 PM PDT 24
Finished Jul 04 04:53:48 PM PDT 24
Peak memory 204384 kb
Host smart-d6b13d54-e32e-424e-83f0-4ebdaccd8791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905095551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1905095551
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.2578198315
Short name T1264
Test name
Test status
Simulation time 18080058747 ps
CPU time 163.89 seconds
Started Jul 04 04:53:44 PM PDT 24
Finished Jul 04 04:56:28 PM PDT 24
Peak memory 213048 kb
Host smart-67cf6989-1dbc-4fce-8553-81aa522dc779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578198315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2578198315
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.962188539
Short name T498
Test name
Test status
Simulation time 5842167961 ps
CPU time 204.94 seconds
Started Jul 04 04:53:41 PM PDT 24
Finished Jul 04 04:57:07 PM PDT 24
Peak memory 1480004 kb
Host smart-f0c4971c-9f20-4639-ac79-b3dd98c425bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962188539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.962188539
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.310414298
Short name T173
Test name
Test status
Simulation time 9796807455 ps
CPU time 54.42 seconds
Started Jul 04 04:53:46 PM PDT 24
Finished Jul 04 04:54:41 PM PDT 24
Peak memory 311052 kb
Host smart-1fa382cf-9926-40c5-bfa9-5d5d7dd56588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310414298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.310414298
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.2646297270
Short name T1519
Test name
Test status
Simulation time 7160973779 ps
CPU time 44.02 seconds
Started Jul 04 04:53:48 PM PDT 24
Finished Jul 04 04:54:33 PM PDT 24
Peak memory 541004 kb
Host smart-b423741e-8378-4b92-8403-0d0ddb82c4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646297270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.2646297270
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.2413014620
Short name T754
Test name
Test status
Simulation time 8263694768 ps
CPU time 21.18 seconds
Started Jul 04 04:53:48 PM PDT 24
Finished Jul 04 04:54:10 PM PDT 24
Peak memory 229360 kb
Host smart-df82344b-2d43-434e-a29b-10dafd21136d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413014620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.2413014620
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.4083454623
Short name T469
Test name
Test status
Simulation time 2065381720 ps
CPU time 3.34 seconds
Started Jul 04 04:53:47 PM PDT 24
Finished Jul 04 04:53:50 PM PDT 24
Peak memory 204700 kb
Host smart-ecaf739a-478d-40dd-a88f-6f99c9664845
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083454623 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.4083454623
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.3491646005
Short name T1122
Test name
Test status
Simulation time 403325243 ps
CPU time 1.01 seconds
Started Jul 04 04:53:49 PM PDT 24
Finished Jul 04 04:53:50 PM PDT 24
Peak memory 204512 kb
Host smart-2fa203b3-885f-46d2-9949-92a30f1568b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491646005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.3491646005
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.135339557
Short name T582
Test name
Test status
Simulation time 212793858 ps
CPU time 1.11 seconds
Started Jul 04 04:53:48 PM PDT 24
Finished Jul 04 04:53:50 PM PDT 24
Peak memory 204564 kb
Host smart-e29542de-3dec-47f6-94ec-874add50eb6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135339557 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_fifo_reset_tx.135339557
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.248521947
Short name T412
Test name
Test status
Simulation time 1487441346 ps
CPU time 2.24 seconds
Started Jul 04 04:53:53 PM PDT 24
Finished Jul 04 04:53:55 PM PDT 24
Peak memory 204692 kb
Host smart-42c95022-e5ea-4d2b-b1e1-b19a597cf588
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248521947 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.248521947
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.742203949
Short name T455
Test name
Test status
Simulation time 1068333713 ps
CPU time 1.17 seconds
Started Jul 04 04:53:56 PM PDT 24
Finished Jul 04 04:53:57 PM PDT 24
Peak memory 204500 kb
Host smart-5d533cd2-6103-4758-8437-c8fa58450bba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742203949 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.742203949
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.3785869765
Short name T1289
Test name
Test status
Simulation time 2030658920 ps
CPU time 6.15 seconds
Started Jul 04 04:53:49 PM PDT 24
Finished Jul 04 04:53:55 PM PDT 24
Peak memory 208696 kb
Host smart-cd4634bf-f2fb-43a4-ac2e-1f5664964767
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785869765 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.3785869765
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.1773610754
Short name T559
Test name
Test status
Simulation time 22094909578 ps
CPU time 463.17 seconds
Started Jul 04 04:53:50 PM PDT 24
Finished Jul 04 05:01:34 PM PDT 24
Peak memory 5422856 kb
Host smart-751c19cc-c904-4a30-9dd2-ebc52484b8c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773610754 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1773610754
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.2122435980
Short name T901
Test name
Test status
Simulation time 6253808152 ps
CPU time 19.43 seconds
Started Jul 04 04:53:49 PM PDT 24
Finished Jul 04 04:54:09 PM PDT 24
Peak memory 204820 kb
Host smart-bf290f0c-d33d-422d-91d8-d2d414ea43da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122435980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.2122435980
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.2269910417
Short name T400
Test name
Test status
Simulation time 1734236847 ps
CPU time 14.16 seconds
Started Jul 04 04:53:50 PM PDT 24
Finished Jul 04 04:54:04 PM PDT 24
Peak memory 213740 kb
Host smart-821210a6-8744-4d55-abac-17bb1ceede6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269910417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.2269910417
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3526183546
Short name T835
Test name
Test status
Simulation time 31815662941 ps
CPU time 302.12 seconds
Started Jul 04 04:53:51 PM PDT 24
Finished Jul 04 04:58:53 PM PDT 24
Peak memory 3069132 kb
Host smart-9a24efd2-acec-49ea-9a6d-bee7c260a4a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526183546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3526183546
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.4186517727
Short name T741
Test name
Test status
Simulation time 24678428176 ps
CPU time 1188.55 seconds
Started Jul 04 04:53:47 PM PDT 24
Finished Jul 04 05:13:36 PM PDT 24
Peak memory 5119392 kb
Host smart-345a79e6-4dab-49a9-8d94-13c9690ad462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186517727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.4186517727
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.2599810413
Short name T662
Test name
Test status
Simulation time 2887958456 ps
CPU time 7.93 seconds
Started Jul 04 04:53:48 PM PDT 24
Finished Jul 04 04:53:56 PM PDT 24
Peak memory 213028 kb
Host smart-8bc40f0c-0a6c-4339-97cb-c8f8fb20f443
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599810413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.2599810413
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.1943037943
Short name T1355
Test name
Test status
Simulation time 51059149 ps
CPU time 1.07 seconds
Started Jul 04 04:53:53 PM PDT 24
Finished Jul 04 04:53:54 PM PDT 24
Peak memory 204720 kb
Host smart-c65e3f1c-4d59-4dc3-a328-0862dd5ba8f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943037943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.1943037943
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.2839677258
Short name T423
Test name
Test status
Simulation time 15274353 ps
CPU time 0.64 seconds
Started Jul 04 04:54:08 PM PDT 24
Finished Jul 04 04:54:09 PM PDT 24
Peak memory 204376 kb
Host smart-05c918d3-e8c4-49bc-930b-92b02fc4c81e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839677258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2839677258
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.4018026638
Short name T840
Test name
Test status
Simulation time 328322127 ps
CPU time 5.36 seconds
Started Jul 04 04:54:02 PM PDT 24
Finished Jul 04 04:54:08 PM PDT 24
Peak memory 249888 kb
Host smart-d6b1a7b9-a1b0-49ec-bd1d-a7f11d9f36ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018026638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.4018026638
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.2685802167
Short name T642
Test name
Test status
Simulation time 265605474 ps
CPU time 13.12 seconds
Started Jul 04 04:53:52 PM PDT 24
Finished Jul 04 04:54:06 PM PDT 24
Peak memory 247360 kb
Host smart-3c316c2f-4133-41d6-9646-edc346334dfa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685802167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.2685802167
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.76173348
Short name T1140
Test name
Test status
Simulation time 13329498824 ps
CPU time 56.58 seconds
Started Jul 04 04:53:57 PM PDT 24
Finished Jul 04 04:54:54 PM PDT 24
Peak memory 463908 kb
Host smart-03b91b22-303d-4926-8d4e-70561354c170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76173348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.76173348
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.2837462433
Short name T870
Test name
Test status
Simulation time 8335404662 ps
CPU time 67.48 seconds
Started Jul 04 04:53:56 PM PDT 24
Finished Jul 04 04:55:03 PM PDT 24
Peak memory 727752 kb
Host smart-f4938ad2-be3f-4e55-b79a-8fc44de083dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837462433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.2837462433
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.1270530466
Short name T765
Test name
Test status
Simulation time 143994808 ps
CPU time 0.87 seconds
Started Jul 04 04:53:57 PM PDT 24
Finished Jul 04 04:53:58 PM PDT 24
Peak memory 204360 kb
Host smart-c75b6ec3-573e-40e2-84f3-8ddb48dcbed0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270530466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.1270530466
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.258749798
Short name T641
Test name
Test status
Simulation time 145784088 ps
CPU time 8.79 seconds
Started Jul 04 04:53:55 PM PDT 24
Finished Jul 04 04:54:04 PM PDT 24
Peak memory 230412 kb
Host smart-8863577e-3954-4e6c-b76e-a8711a7b6c02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258749798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.
258749798
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.621996754
Short name T1421
Test name
Test status
Simulation time 9469792574 ps
CPU time 134.2 seconds
Started Jul 04 04:53:52 PM PDT 24
Finished Jul 04 04:56:06 PM PDT 24
Peak memory 1268168 kb
Host smart-562a53e7-f7d6-4a22-8f10-47e4f397ae08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621996754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.621996754
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.1954194324
Short name T1096
Test name
Test status
Simulation time 1196497294 ps
CPU time 4.4 seconds
Started Jul 04 04:54:04 PM PDT 24
Finished Jul 04 04:54:08 PM PDT 24
Peak memory 204676 kb
Host smart-326044a0-7477-4ab0-b6e2-4d4c25cee447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954194324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1954194324
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.2319368806
Short name T907
Test name
Test status
Simulation time 1544716642 ps
CPU time 23.53 seconds
Started Jul 04 04:54:03 PM PDT 24
Finished Jul 04 04:54:27 PM PDT 24
Peak memory 316300 kb
Host smart-f3600f8c-0a3b-42bd-8ffa-81d7860f2b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319368806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.2319368806
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.3452295503
Short name T151
Test name
Test status
Simulation time 21594686 ps
CPU time 0.69 seconds
Started Jul 04 04:53:54 PM PDT 24
Finished Jul 04 04:53:55 PM PDT 24
Peak memory 204388 kb
Host smart-19348938-408f-4262-add2-d0253da131b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452295503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.3452295503
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.1490487275
Short name T413
Test name
Test status
Simulation time 232859095 ps
CPU time 9.74 seconds
Started Jul 04 04:54:03 PM PDT 24
Finished Jul 04 04:54:13 PM PDT 24
Peak memory 212840 kb
Host smart-f3dee3cd-512a-4846-b2fe-e7393d0464a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490487275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.1490487275
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.2201334803
Short name T365
Test name
Test status
Simulation time 2961143292 ps
CPU time 25.49 seconds
Started Jul 04 04:53:55 PM PDT 24
Finished Jul 04 04:54:20 PM PDT 24
Peak memory 382076 kb
Host smart-b7e67340-c6a8-45a6-b0d3-fea0f9344991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201334803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.2201334803
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.1197264597
Short name T122
Test name
Test status
Simulation time 38028174713 ps
CPU time 1052.73 seconds
Started Jul 04 04:54:01 PM PDT 24
Finished Jul 04 05:11:35 PM PDT 24
Peak memory 3540068 kb
Host smart-fddd1811-3573-4967-8da8-d34bed6d0357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197264597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.1197264597
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.1405713552
Short name T51
Test name
Test status
Simulation time 895047902 ps
CPU time 15.02 seconds
Started Jul 04 04:54:01 PM PDT 24
Finished Jul 04 04:54:17 PM PDT 24
Peak memory 220840 kb
Host smart-2037964e-2477-4e43-bbde-a2cd5c14a2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405713552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.1405713552
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.3975991374
Short name T681
Test name
Test status
Simulation time 1286407961 ps
CPU time 3.82 seconds
Started Jul 04 04:54:01 PM PDT 24
Finished Jul 04 04:54:06 PM PDT 24
Peak memory 212892 kb
Host smart-34efe32a-7b6a-4d8b-84cc-818d576a8e52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975991374 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.3975991374
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2164540450
Short name T394
Test name
Test status
Simulation time 565625935 ps
CPU time 1.21 seconds
Started Jul 04 04:54:00 PM PDT 24
Finished Jul 04 04:54:01 PM PDT 24
Peak memory 204784 kb
Host smart-be68d325-7b21-486f-87f0-d689bb52c6e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164540450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.2164540450
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.2144869113
Short name T1057
Test name
Test status
Simulation time 569356046 ps
CPU time 2.81 seconds
Started Jul 04 04:54:01 PM PDT 24
Finished Jul 04 04:54:04 PM PDT 24
Peak memory 204732 kb
Host smart-17f606be-abb6-492f-9621-e8f9b0ed341a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144869113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.2144869113
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.1154588178
Short name T1383
Test name
Test status
Simulation time 126506334 ps
CPU time 1.18 seconds
Started Jul 04 04:54:00 PM PDT 24
Finished Jul 04 04:54:02 PM PDT 24
Peak memory 204416 kb
Host smart-54fcccdb-2900-41a5-8ec2-51c98e0db345
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154588178 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.1154588178
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2201547394
Short name T1238
Test name
Test status
Simulation time 454813665 ps
CPU time 3.44 seconds
Started Jul 04 04:54:02 PM PDT 24
Finished Jul 04 04:54:06 PM PDT 24
Peak memory 204692 kb
Host smart-51f3d9ce-e6ad-4791-94dc-fc6e0917dc58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201547394 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2201547394
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.328069697
Short name T351
Test name
Test status
Simulation time 1175609134 ps
CPU time 6.54 seconds
Started Jul 04 04:53:59 PM PDT 24
Finished Jul 04 04:54:06 PM PDT 24
Peak memory 212924 kb
Host smart-456310a4-fb3a-4ea7-9661-bfff9180b122
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328069697 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_intr_smoke.328069697
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.3492381748
Short name T1222
Test name
Test status
Simulation time 14017466041 ps
CPU time 249.98 seconds
Started Jul 04 04:54:06 PM PDT 24
Finished Jul 04 04:58:16 PM PDT 24
Peak memory 3454824 kb
Host smart-eafb7c84-e69f-45cd-87c8-4e0944c1686d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492381748 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.3492381748
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1323727017
Short name T1276
Test name
Test status
Simulation time 3897188976 ps
CPU time 35.42 seconds
Started Jul 04 04:54:00 PM PDT 24
Finished Jul 04 04:54:36 PM PDT 24
Peak memory 204852 kb
Host smart-c281f25f-4e2d-4cbe-8c97-23ebfe4b16dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323727017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1323727017
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.2086107700
Short name T1363
Test name
Test status
Simulation time 1196941533 ps
CPU time 4.33 seconds
Started Jul 04 04:53:59 PM PDT 24
Finished Jul 04 04:54:04 PM PDT 24
Peak memory 204700 kb
Host smart-8239f8a5-5207-4787-8303-2624b500b877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086107700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.2086107700
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.1098721373
Short name T763
Test name
Test status
Simulation time 43708994428 ps
CPU time 660.69 seconds
Started Jul 04 04:54:03 PM PDT 24
Finished Jul 04 05:05:04 PM PDT 24
Peak memory 5456260 kb
Host smart-39d601bd-1d2a-4a21-8fea-1ad94fe1efbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098721373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.1098721373
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.3449107993
Short name T1058
Test name
Test status
Simulation time 19134440791 ps
CPU time 2388.85 seconds
Started Jul 04 04:54:02 PM PDT 24
Finished Jul 04 05:33:51 PM PDT 24
Peak memory 3979672 kb
Host smart-5385df8f-e68c-4efa-8625-9c0d1f3a8012
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449107993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.3449107993
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.2879872713
Short name T711
Test name
Test status
Simulation time 2282649833 ps
CPU time 6.79 seconds
Started Jul 04 04:54:02 PM PDT 24
Finished Jul 04 04:54:09 PM PDT 24
Peak memory 219980 kb
Host smart-2b034cdc-e9c1-402b-aa6a-f02c96d2e3f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879872713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.2879872713
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.2517374665
Short name T782
Test name
Test status
Simulation time 473003237 ps
CPU time 6.43 seconds
Started Jul 04 04:54:02 PM PDT 24
Finished Jul 04 04:54:08 PM PDT 24
Peak memory 204664 kb
Host smart-9d99dd96-45ef-430b-9b78-08b3e01617d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517374665 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.2517374665
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.3962582667
Short name T785
Test name
Test status
Simulation time 47786159 ps
CPU time 0.64 seconds
Started Jul 04 04:54:17 PM PDT 24
Finished Jul 04 04:54:18 PM PDT 24
Peak memory 204400 kb
Host smart-c1302bec-46ed-49e9-89dc-834f5f07430e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962582667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3962582667
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1590407795
Short name T1273
Test name
Test status
Simulation time 559193409 ps
CPU time 1.73 seconds
Started Jul 04 04:54:08 PM PDT 24
Finished Jul 04 04:54:10 PM PDT 24
Peak memory 212924 kb
Host smart-82d42efa-9be4-4f8a-9faa-73c31f688a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590407795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1590407795
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.3146681330
Short name T141
Test name
Test status
Simulation time 1232616828 ps
CPU time 14.65 seconds
Started Jul 04 04:54:07 PM PDT 24
Finished Jul 04 04:54:22 PM PDT 24
Peak memory 258292 kb
Host smart-db98bd11-ba84-4a61-b796-339a157c496d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146681330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.3146681330
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2052597913
Short name T1181
Test name
Test status
Simulation time 2332821000 ps
CPU time 70.32 seconds
Started Jul 04 04:54:09 PM PDT 24
Finished Jul 04 04:55:20 PM PDT 24
Peak memory 740244 kb
Host smart-d13068a2-2789-4cfa-9d50-6d5a65ce133f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052597913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2052597913
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.966306143
Short name T2
Test name
Test status
Simulation time 2662219739 ps
CPU time 195.71 seconds
Started Jul 04 04:54:07 PM PDT 24
Finished Jul 04 04:57:23 PM PDT 24
Peak memory 819660 kb
Host smart-392f4f17-e5b7-4bbc-9828-7eef5be01311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966306143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.966306143
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.2382027732
Short name T550
Test name
Test status
Simulation time 297969324 ps
CPU time 1.04 seconds
Started Jul 04 04:54:08 PM PDT 24
Finished Jul 04 04:54:09 PM PDT 24
Peak memory 204412 kb
Host smart-27ea485b-bb6c-4ab0-a19f-eb73836a77c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382027732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.2382027732
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.349543755
Short name T1455
Test name
Test status
Simulation time 293146489 ps
CPU time 4.08 seconds
Started Jul 04 04:54:08 PM PDT 24
Finished Jul 04 04:54:12 PM PDT 24
Peak memory 231536 kb
Host smart-203fbdfd-3495-4981-bfdb-05daca9d38c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349543755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
349543755
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.1603956643
Short name T655
Test name
Test status
Simulation time 4488625116 ps
CPU time 310.51 seconds
Started Jul 04 04:54:07 PM PDT 24
Finished Jul 04 04:59:17 PM PDT 24
Peak memory 1250008 kb
Host smart-f317a50e-e019-49f4-ba08-b2e48d4cab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603956643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.1603956643
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.1505486887
Short name T252
Test name
Test status
Simulation time 595948373 ps
CPU time 9 seconds
Started Jul 04 04:54:17 PM PDT 24
Finished Jul 04 04:54:26 PM PDT 24
Peak memory 204824 kb
Host smart-db70da2a-5f5d-486d-b872-3fe59d36109c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505486887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.1505486887
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.3487424317
Short name T859
Test name
Test status
Simulation time 960717648 ps
CPU time 18.42 seconds
Started Jul 04 04:54:15 PM PDT 24
Finished Jul 04 04:54:34 PM PDT 24
Peak memory 284056 kb
Host smart-65d8b7c9-1f49-4f18-a4cb-d19e9de5c7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487424317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.3487424317
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.1249956867
Short name T1068
Test name
Test status
Simulation time 20831362 ps
CPU time 0.7 seconds
Started Jul 04 04:54:10 PM PDT 24
Finished Jul 04 04:54:11 PM PDT 24
Peak memory 204404 kb
Host smart-1ddc93da-3340-446e-9437-60213f09ea3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249956867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1249956867
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.311313945
Short name T752
Test name
Test status
Simulation time 268178191 ps
CPU time 7.45 seconds
Started Jul 04 04:54:06 PM PDT 24
Finished Jul 04 04:54:14 PM PDT 24
Peak memory 218256 kb
Host smart-df3122ec-f834-4986-b6b4-3d08f1c6895d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311313945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.311313945
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.154471317
Short name T880
Test name
Test status
Simulation time 23226297856 ps
CPU time 323.64 seconds
Started Jul 04 04:54:09 PM PDT 24
Finished Jul 04 04:59:33 PM PDT 24
Peak memory 204664 kb
Host smart-1578efbc-71b1-4025-bf05-ec1713726365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154471317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.154471317
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3507450320
Short name T1161
Test name
Test status
Simulation time 1362954268 ps
CPU time 65.98 seconds
Started Jul 04 04:54:09 PM PDT 24
Finished Jul 04 04:55:16 PM PDT 24
Peak memory 326480 kb
Host smart-e9265f91-d0be-4038-851f-92585740d710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507450320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3507450320
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.1368342541
Short name T90
Test name
Test status
Simulation time 32564176855 ps
CPU time 1200.52 seconds
Started Jul 04 04:54:06 PM PDT 24
Finished Jul 04 05:14:07 PM PDT 24
Peak memory 3444128 kb
Host smart-e65c6895-0ce8-4c7a-b250-2ba49b0a06cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368342541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.1368342541
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.1163686331
Short name T456
Test name
Test status
Simulation time 1666117389 ps
CPU time 14.27 seconds
Started Jul 04 04:54:06 PM PDT 24
Finished Jul 04 04:54:20 PM PDT 24
Peak memory 221016 kb
Host smart-4842cc23-2089-4bef-ae32-fce390737de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163686331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.1163686331
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.1354208224
Short name T1294
Test name
Test status
Simulation time 678760885 ps
CPU time 3.82 seconds
Started Jul 04 04:54:15 PM PDT 24
Finished Jul 04 04:54:19 PM PDT 24
Peak memory 204756 kb
Host smart-6b7cdd79-7d1c-4630-96a8-f8adb05a4b6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354208224 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1354208224
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1107442120
Short name T950
Test name
Test status
Simulation time 185631091 ps
CPU time 1.35 seconds
Started Jul 04 04:54:15 PM PDT 24
Finished Jul 04 04:54:17 PM PDT 24
Peak memory 204700 kb
Host smart-56ce9cc9-113c-4504-a08c-eb8f241c061f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107442120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.1107442120
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.4033962254
Short name T1431
Test name
Test status
Simulation time 541130193 ps
CPU time 0.95 seconds
Started Jul 04 04:54:14 PM PDT 24
Finished Jul 04 04:54:16 PM PDT 24
Peak memory 204504 kb
Host smart-628b0ab0-1f23-4bdd-886e-8d07c099eff9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033962254 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.4033962254
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.2544514448
Short name T764
Test name
Test status
Simulation time 161816746 ps
CPU time 1.3 seconds
Started Jul 04 04:54:16 PM PDT 24
Finished Jul 04 04:54:17 PM PDT 24
Peak memory 204460 kb
Host smart-d5d2389e-8b9c-471c-ac0b-2df90f65bf95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544514448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.2544514448
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.978486539
Short name T1225
Test name
Test status
Simulation time 242698365 ps
CPU time 1.26 seconds
Started Jul 04 04:54:17 PM PDT 24
Finished Jul 04 04:54:18 PM PDT 24
Peak memory 204412 kb
Host smart-f6165f2f-16fc-4421-a20b-8fe3b15a0156
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978486539 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.978486539
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.105016517
Short name T1255
Test name
Test status
Simulation time 621252002 ps
CPU time 3.71 seconds
Started Jul 04 04:54:16 PM PDT 24
Finished Jul 04 04:54:20 PM PDT 24
Peak memory 204728 kb
Host smart-7bb823c5-2c80-4ac3-aee2-3d91c2148413
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105016517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_intr_smoke.105016517
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.2880503779
Short name T1339
Test name
Test status
Simulation time 32006776164 ps
CPU time 77.6 seconds
Started Jul 04 04:54:14 PM PDT 24
Finished Jul 04 04:55:31 PM PDT 24
Peak memory 1522232 kb
Host smart-904418e5-2142-4949-8662-117137e76813
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880503779 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.2880503779
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.2223945449
Short name T1020
Test name
Test status
Simulation time 837716863 ps
CPU time 14.39 seconds
Started Jul 04 04:54:08 PM PDT 24
Finished Jul 04 04:54:22 PM PDT 24
Peak memory 204724 kb
Host smart-57f4b15e-1e3f-4d9e-8593-cee4c87f30c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223945449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.2223945449
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.4121689499
Short name T786
Test name
Test status
Simulation time 39634808132 ps
CPU time 80.29 seconds
Started Jul 04 04:54:09 PM PDT 24
Finished Jul 04 04:55:30 PM PDT 24
Peak memory 1255192 kb
Host smart-40cbfd71-4cba-43e0-838d-376f572d56d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121689499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.4121689499
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.431408258
Short name T283
Test name
Test status
Simulation time 15576746066 ps
CPU time 234.53 seconds
Started Jul 04 04:54:15 PM PDT 24
Finished Jul 04 04:58:10 PM PDT 24
Peak memory 974332 kb
Host smart-adca1539-7145-4af5-837d-f8500e17cc01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431408258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_t
arget_stretch.431408258
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.4289075130
Short name T750
Test name
Test status
Simulation time 2615331283 ps
CPU time 7.62 seconds
Started Jul 04 04:54:14 PM PDT 24
Finished Jul 04 04:54:22 PM PDT 24
Peak memory 213016 kb
Host smart-dafae499-4f6f-4b6f-b709-192d233615ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289075130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.4289075130
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.22067655
Short name T957
Test name
Test status
Simulation time 169959967 ps
CPU time 2.84 seconds
Started Jul 04 04:54:15 PM PDT 24
Finished Jul 04 04:54:18 PM PDT 24
Peak memory 204704 kb
Host smart-907d80ab-5b75-4ccf-bf6a-a1d5e9bde6e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22067655 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.22067655
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.3533598375
Short name T1375
Test name
Test status
Simulation time 40377163 ps
CPU time 0.63 seconds
Started Jul 04 04:54:22 PM PDT 24
Finished Jul 04 04:54:23 PM PDT 24
Peak memory 204340 kb
Host smart-79fe8961-5775-4a62-b19d-6f00d5ccaf4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533598375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3533598375
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.1788853232
Short name T436
Test name
Test status
Simulation time 629126542 ps
CPU time 5.36 seconds
Started Jul 04 04:54:15 PM PDT 24
Finished Jul 04 04:54:20 PM PDT 24
Peak memory 216240 kb
Host smart-6177aa0e-6163-4768-9316-3daa994bdbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788853232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.1788853232
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2683058167
Short name T1443
Test name
Test status
Simulation time 261209918 ps
CPU time 12.47 seconds
Started Jul 04 04:54:16 PM PDT 24
Finished Jul 04 04:54:29 PM PDT 24
Peak memory 228204 kb
Host smart-e9c23aef-241f-4dca-8e13-73a19d7dc093
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683058167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2683058167
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3492384516
Short name T609
Test name
Test status
Simulation time 2718087519 ps
CPU time 81 seconds
Started Jul 04 04:54:22 PM PDT 24
Finished Jul 04 04:55:43 PM PDT 24
Peak memory 785040 kb
Host smart-2155bc81-56d7-4f80-a5cb-5c9f603cc4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492384516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3492384516
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.122611096
Short name T539
Test name
Test status
Simulation time 9287497062 ps
CPU time 62.63 seconds
Started Jul 04 04:54:22 PM PDT 24
Finished Jul 04 04:55:25 PM PDT 24
Peak memory 714580 kb
Host smart-f02e49cd-6b66-4732-9831-b5b360a837d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122611096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.122611096
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.2539065990
Short name T592
Test name
Test status
Simulation time 502623558 ps
CPU time 1.16 seconds
Started Jul 04 04:54:15 PM PDT 24
Finished Jul 04 04:54:17 PM PDT 24
Peak memory 204576 kb
Host smart-c7f654df-9279-41e0-b890-679c3bd37559
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539065990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.2539065990
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.2984572685
Short name T695
Test name
Test status
Simulation time 697248822 ps
CPU time 3.79 seconds
Started Jul 04 04:54:16 PM PDT 24
Finished Jul 04 04:54:20 PM PDT 24
Peak memory 204708 kb
Host smart-448c390e-f4d7-44c4-b17e-9a0d91215830
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984572685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.2984572685
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.1775001815
Short name T286
Test name
Test status
Simulation time 7215083541 ps
CPU time 103.89 seconds
Started Jul 04 04:54:16 PM PDT 24
Finished Jul 04 04:56:00 PM PDT 24
Peak memory 1070464 kb
Host smart-6dc92bee-224f-4efe-90e2-3d212868883d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775001815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1775001815
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1432454563
Short name T514
Test name
Test status
Simulation time 522590200 ps
CPU time 19.7 seconds
Started Jul 04 04:54:22 PM PDT 24
Finished Jul 04 04:54:42 PM PDT 24
Peak memory 204716 kb
Host smart-8b55c6c8-98d1-4464-840c-4bcc75143891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432454563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1432454563
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.711173969
Short name T962
Test name
Test status
Simulation time 1855616238 ps
CPU time 32.73 seconds
Started Jul 04 04:54:22 PM PDT 24
Finished Jul 04 04:54:55 PM PDT 24
Peak memory 432024 kb
Host smart-5a1fb6b1-cd02-436b-9806-255d6d05571d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711173969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.711173969
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.2912168712
Short name T404
Test name
Test status
Simulation time 27142691 ps
CPU time 0.73 seconds
Started Jul 04 04:54:15 PM PDT 24
Finished Jul 04 04:54:16 PM PDT 24
Peak memory 204408 kb
Host smart-63480ffd-10c5-4ed5-9809-6331466ffcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912168712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.2912168712
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.791190073
Short name T1085
Test name
Test status
Simulation time 24671886653 ps
CPU time 127.51 seconds
Started Jul 04 04:54:17 PM PDT 24
Finished Jul 04 04:56:24 PM PDT 24
Peak memory 204896 kb
Host smart-bf500f2b-35c9-4cf8-b689-fbd2429fa8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791190073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.791190073
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.3320448181
Short name T643
Test name
Test status
Simulation time 244636502 ps
CPU time 5.24 seconds
Started Jul 04 04:54:16 PM PDT 24
Finished Jul 04 04:54:22 PM PDT 24
Peak memory 204712 kb
Host smart-2c1341e9-3a2d-4596-8900-53fd50ff4599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320448181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.3320448181
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1724349938
Short name T139
Test name
Test status
Simulation time 1804854256 ps
CPU time 34.62 seconds
Started Jul 04 04:54:16 PM PDT 24
Finished Jul 04 04:54:51 PM PDT 24
Peak memory 347972 kb
Host smart-3ae0d19a-a3e5-40ab-89a1-ef57be20468f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724349938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1724349938
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.266826403
Short name T121
Test name
Test status
Simulation time 16734130010 ps
CPU time 355.66 seconds
Started Jul 04 04:54:14 PM PDT 24
Finished Jul 04 05:00:10 PM PDT 24
Peak memory 2256488 kb
Host smart-5e963af2-4052-4db5-815c-631c94b3363a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266826403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.266826403
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.172550626
Short name T775
Test name
Test status
Simulation time 1548657296 ps
CPU time 13.58 seconds
Started Jul 04 04:54:17 PM PDT 24
Finished Jul 04 04:54:31 PM PDT 24
Peak memory 220368 kb
Host smart-f4f6d978-6708-4ce9-a5f2-91a95bde5a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172550626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.172550626
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.3844985373
Short name T1145
Test name
Test status
Simulation time 342637935 ps
CPU time 2.23 seconds
Started Jul 04 04:54:21 PM PDT 24
Finished Jul 04 04:54:23 PM PDT 24
Peak memory 204688 kb
Host smart-012821c6-988b-4bfd-a2aa-86817f83aaff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844985373 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.3844985373
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.3930318539
Short name T476
Test name
Test status
Simulation time 212548492 ps
CPU time 0.93 seconds
Started Jul 04 04:54:21 PM PDT 24
Finished Jul 04 04:54:22 PM PDT 24
Peak memory 204596 kb
Host smart-37bacd39-30fe-46ff-acb2-7cd653e06f82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930318539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.3930318539
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.4198542159
Short name T502
Test name
Test status
Simulation time 200921576 ps
CPU time 1.25 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 04:54:25 PM PDT 24
Peak memory 212908 kb
Host smart-729d51ad-6912-4f7c-a7ec-3649157f9b7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198542159 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.4198542159
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.4168783044
Short name T798
Test name
Test status
Simulation time 1904612500 ps
CPU time 2.69 seconds
Started Jul 04 04:54:20 PM PDT 24
Finished Jul 04 04:54:23 PM PDT 24
Peak memory 204744 kb
Host smart-dfba4de8-d4fa-4f74-9f41-7a58ea206c1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168783044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.4168783044
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.962146190
Short name T1062
Test name
Test status
Simulation time 100465302 ps
CPU time 1.05 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 04:54:25 PM PDT 24
Peak memory 204564 kb
Host smart-b4f6484f-e38c-44e2-b474-5440936ccc65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962146190 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.962146190
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.1031927479
Short name T610
Test name
Test status
Simulation time 1485844797 ps
CPU time 2.48 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 04:54:26 PM PDT 24
Peak memory 204668 kb
Host smart-55d89e81-12ee-479b-9c2c-8c1f6a3521dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031927479 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.1031927479
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.3703929010
Short name T605
Test name
Test status
Simulation time 909044259 ps
CPU time 4.99 seconds
Started Jul 04 04:54:15 PM PDT 24
Finished Jul 04 04:54:21 PM PDT 24
Peak memory 212940 kb
Host smart-7a46ee7c-69f8-499b-afec-3c060204c68d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703929010 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.3703929010
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.4192856139
Short name T1332
Test name
Test status
Simulation time 24033432817 ps
CPU time 195.13 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 04:57:39 PM PDT 24
Peak memory 2231856 kb
Host smart-1959a575-273f-4af6-bb01-f023ac4fb59a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192856139 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.4192856139
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.4216444550
Short name T451
Test name
Test status
Simulation time 1111373344 ps
CPU time 13.9 seconds
Started Jul 04 04:54:15 PM PDT 24
Finished Jul 04 04:54:30 PM PDT 24
Peak memory 204604 kb
Host smart-3586f38e-5975-442a-a1ad-7d92269e0db4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216444550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.4216444550
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.2610737804
Short name T1129
Test name
Test status
Simulation time 5478901956 ps
CPU time 61.98 seconds
Started Jul 04 04:54:19 PM PDT 24
Finished Jul 04 04:55:21 PM PDT 24
Peak memory 209644 kb
Host smart-6a035b30-8e14-44b7-b843-9ca5956a8657
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610737804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.2610737804
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.2022045364
Short name T876
Test name
Test status
Simulation time 30202096613 ps
CPU time 78.35 seconds
Started Jul 04 04:54:17 PM PDT 24
Finished Jul 04 04:55:36 PM PDT 24
Peak memory 1357160 kb
Host smart-2cc31dcf-0bca-4a46-920e-6ece399c706b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022045364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.2022045364
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.2058397390
Short name T1093
Test name
Test status
Simulation time 21276740267 ps
CPU time 1244.52 seconds
Started Jul 04 04:54:15 PM PDT 24
Finished Jul 04 05:15:00 PM PDT 24
Peak memory 5111808 kb
Host smart-2b7fc3ae-5a2b-48bf-96ab-0691fdc04af9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058397390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.2058397390
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.2082804212
Short name T944
Test name
Test status
Simulation time 6094224595 ps
CPU time 8.15 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 04:54:31 PM PDT 24
Peak memory 221148 kb
Host smart-67ccac82-0326-47aa-b38a-ebacd5d57018
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082804212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.2082804212
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.2830005996
Short name T1483
Test name
Test status
Simulation time 653476354 ps
CPU time 8.09 seconds
Started Jul 04 04:54:21 PM PDT 24
Finished Jul 04 04:54:30 PM PDT 24
Peak memory 204712 kb
Host smart-7330b4e4-6c8b-4699-80e6-b55afa20ee42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830005996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.2830005996
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.635595944
Short name T673
Test name
Test status
Simulation time 184584928 ps
CPU time 0.62 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 04:54:24 PM PDT 24
Peak memory 204312 kb
Host smart-94a6b1ce-4089-4697-879d-697a824c99d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635595944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.635595944
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.2382479382
Short name T570
Test name
Test status
Simulation time 277691784 ps
CPU time 1.88 seconds
Started Jul 04 04:54:19 PM PDT 24
Finished Jul 04 04:54:21 PM PDT 24
Peak memory 213012 kb
Host smart-1c90fb2c-927c-496b-812b-8aee6cb1b4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382479382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.2382479382
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.54725558
Short name T739
Test name
Test status
Simulation time 417148040 ps
CPU time 21.75 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 04:54:45 PM PDT 24
Peak memory 289688 kb
Host smart-82e02173-9279-4c41-80a8-34a8b6a9b0fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54725558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empty
.54725558
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.3648989504
Short name T1203
Test name
Test status
Simulation time 8641952600 ps
CPU time 59.39 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 04:55:23 PM PDT 24
Peak memory 612076 kb
Host smart-9611a529-399c-4853-832f-7f2cdbba4cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648989504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.3648989504
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.1295355389
Short name T540
Test name
Test status
Simulation time 2876582161 ps
CPU time 99.68 seconds
Started Jul 04 04:54:21 PM PDT 24
Finished Jul 04 04:56:01 PM PDT 24
Peak memory 523132 kb
Host smart-622c1c86-62f4-40dd-b31e-c3788977e64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295355389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.1295355389
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.452252574
Short name T1438
Test name
Test status
Simulation time 1117796936 ps
CPU time 0.93 seconds
Started Jul 04 04:54:24 PM PDT 24
Finished Jul 04 04:54:26 PM PDT 24
Peak memory 204408 kb
Host smart-fe667a5f-8718-4321-9c70-2ba9817425d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452252574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fm
t.452252574
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.563195543
Short name T1487
Test name
Test status
Simulation time 217855491 ps
CPU time 6.95 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 04:54:30 PM PDT 24
Peak memory 222960 kb
Host smart-03a3003b-17fe-4fff-8dc1-7a8deaed0123
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563195543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.
563195543
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3802299452
Short name T1407
Test name
Test status
Simulation time 14323486010 ps
CPU time 390.98 seconds
Started Jul 04 04:54:20 PM PDT 24
Finished Jul 04 05:00:51 PM PDT 24
Peak memory 1485280 kb
Host smart-26892fff-65de-43df-9547-f6e3e6f245fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802299452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3802299452
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.3855827365
Short name T1032
Test name
Test status
Simulation time 558017631 ps
CPU time 3.92 seconds
Started Jul 04 04:54:24 PM PDT 24
Finished Jul 04 04:54:28 PM PDT 24
Peak memory 204704 kb
Host smart-a5648fdd-fbf4-47b1-b7c0-e09259462980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855827365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.3855827365
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.1172532473
Short name T1411
Test name
Test status
Simulation time 4314081318 ps
CPU time 94.74 seconds
Started Jul 04 04:54:24 PM PDT 24
Finished Jul 04 04:55:59 PM PDT 24
Peak memory 326180 kb
Host smart-a28fa88f-0672-48a4-9004-dc8e5c2cf449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172532473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.1172532473
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.4277768290
Short name T504
Test name
Test status
Simulation time 88715878 ps
CPU time 0.69 seconds
Started Jul 04 04:54:22 PM PDT 24
Finished Jul 04 04:54:23 PM PDT 24
Peak memory 204408 kb
Host smart-eb55bab6-9f81-44e2-90fe-c033c38bf380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277768290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.4277768290
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.4255843145
Short name T343
Test name
Test status
Simulation time 6418925242 ps
CPU time 33.95 seconds
Started Jul 04 04:54:26 PM PDT 24
Finished Jul 04 04:55:00 PM PDT 24
Peak memory 212996 kb
Host smart-4269a8c9-a1ab-41cb-bd83-8e3113fb1621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255843145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.4255843145
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.4271196952
Short name T1039
Test name
Test status
Simulation time 1607422590 ps
CPU time 3.93 seconds
Started Jul 04 04:54:25 PM PDT 24
Finished Jul 04 04:54:29 PM PDT 24
Peak memory 232420 kb
Host smart-d6540645-b2fe-40c9-a436-5e8b73aa365f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271196952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.4271196952
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1707597989
Short name T568
Test name
Test status
Simulation time 2126396418 ps
CPU time 39.95 seconds
Started Jul 04 04:54:20 PM PDT 24
Finished Jul 04 04:55:00 PM PDT 24
Peak memory 443696 kb
Host smart-2c390a4d-12e9-4108-8b98-9ae301c5fc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707597989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1707597989
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.1445414299
Short name T983
Test name
Test status
Simulation time 8308524180 ps
CPU time 768.22 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 05:07:12 PM PDT 24
Peak memory 2110688 kb
Host smart-9d257ffc-9315-4a23-849a-dfa802714127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445414299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.1445414299
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.1007391037
Short name T272
Test name
Test status
Simulation time 634703814 ps
CPU time 12.95 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 04:54:36 PM PDT 24
Peak memory 212892 kb
Host smart-c13b271e-27a9-41ae-9a7a-6dd2f532dfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007391037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1007391037
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.985748650
Short name T945
Test name
Test status
Simulation time 2491164167 ps
CPU time 3.69 seconds
Started Jul 04 04:54:21 PM PDT 24
Finished Jul 04 04:54:25 PM PDT 24
Peak memory 213004 kb
Host smart-e70d8122-90c1-4141-9176-d3bdaed1dcca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985748650 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.985748650
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.2306978507
Short name T884
Test name
Test status
Simulation time 234481650 ps
CPU time 1.53 seconds
Started Jul 04 04:54:26 PM PDT 24
Finished Jul 04 04:54:28 PM PDT 24
Peak memory 217416 kb
Host smart-85abbc30-b08a-4f91-a960-74beb8cd2d0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306978507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.2306978507
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.548627602
Short name T522
Test name
Test status
Simulation time 220628919 ps
CPU time 1.34 seconds
Started Jul 04 04:54:20 PM PDT 24
Finished Jul 04 04:54:21 PM PDT 24
Peak memory 206472 kb
Host smart-648e32da-cddd-40f9-9397-28ab4023c6e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548627602 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_fifo_reset_tx.548627602
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.874378958
Short name T1367
Test name
Test status
Simulation time 2000793050 ps
CPU time 2.39 seconds
Started Jul 04 04:54:21 PM PDT 24
Finished Jul 04 04:54:24 PM PDT 24
Peak memory 204720 kb
Host smart-680397d5-4a69-46e1-a415-c249035e6c96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874378958 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.874378958
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.1496999636
Short name T1091
Test name
Test status
Simulation time 861347908 ps
CPU time 1.16 seconds
Started Jul 04 04:54:26 PM PDT 24
Finished Jul 04 04:54:27 PM PDT 24
Peak memory 204496 kb
Host smart-75862acb-5402-449c-8315-d3d362d10ce5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496999636 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.1496999636
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.1772626623
Short name T28
Test name
Test status
Simulation time 407474114 ps
CPU time 3.28 seconds
Started Jul 04 04:54:20 PM PDT 24
Finished Jul 04 04:54:23 PM PDT 24
Peak memory 204696 kb
Host smart-36a8011d-15e7-4911-a618-eb79b75c6e37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772626623 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.1772626623
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.3298526765
Short name T166
Test name
Test status
Simulation time 5164294056 ps
CPU time 5.87 seconds
Started Jul 04 04:54:22 PM PDT 24
Finished Jul 04 04:54:29 PM PDT 24
Peak memory 217504 kb
Host smart-05736b6b-d183-4b9b-9ac8-d2a68332cb91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298526765 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.3298526765
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.951075026
Short name T480
Test name
Test status
Simulation time 14198256586 ps
CPU time 21.65 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 04:54:45 PM PDT 24
Peak memory 498740 kb
Host smart-ff21166b-b652-4205-ab94-b2d7329aaa35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951075026 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.951075026
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.3393638581
Short name T26
Test name
Test status
Simulation time 4757190941 ps
CPU time 49.33 seconds
Started Jul 04 04:54:22 PM PDT 24
Finished Jul 04 04:55:11 PM PDT 24
Peak memory 204864 kb
Host smart-485154d1-8ad1-4753-a21c-edf2abd0b887
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393638581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.3393638581
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.676419414
Short name T1314
Test name
Test status
Simulation time 1059573710 ps
CPU time 19.11 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 04:54:43 PM PDT 24
Peak memory 214668 kb
Host smart-bdf2dce1-0cc3-4496-b037-3038cc3b5d51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676419414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_rd.676419414
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.3069669127
Short name T247
Test name
Test status
Simulation time 33971432913 ps
CPU time 47.53 seconds
Started Jul 04 04:54:19 PM PDT 24
Finished Jul 04 04:55:07 PM PDT 24
Peak memory 954884 kb
Host smart-82ed383b-9933-4fb2-9aec-5af0fa7bbe63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069669127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.3069669127
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.559070787
Short name T608
Test name
Test status
Simulation time 39997318437 ps
CPU time 648.16 seconds
Started Jul 04 04:54:22 PM PDT 24
Finished Jul 04 05:05:11 PM PDT 24
Peak memory 4563296 kb
Host smart-a96f6c2c-2c52-468c-8441-0dbbfd5c63e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559070787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_t
arget_stretch.559070787
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3360718503
Short name T1136
Test name
Test status
Simulation time 29738212000 ps
CPU time 8.02 seconds
Started Jul 04 04:54:24 PM PDT 24
Finished Jul 04 04:54:32 PM PDT 24
Peak memory 221124 kb
Host smart-e28987b2-076e-4d9f-a359-6e3ed70e0f43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360718503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3360718503
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.791244310
Short name T392
Test name
Test status
Simulation time 119964046 ps
CPU time 2.52 seconds
Started Jul 04 04:54:24 PM PDT 24
Finished Jul 04 04:54:27 PM PDT 24
Peak memory 204736 kb
Host smart-b9811741-1308-4e5f-ae7f-7400c803499d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791244310 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.791244310
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.906388948
Short name T1400
Test name
Test status
Simulation time 27440849 ps
CPU time 0.61 seconds
Started Jul 04 04:54:33 PM PDT 24
Finished Jul 04 04:54:33 PM PDT 24
Peak memory 204352 kb
Host smart-a40bb1f4-61a0-46b0-89a8-2289fbfc4160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906388948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.906388948
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.3760588707
Short name T1205
Test name
Test status
Simulation time 376850110 ps
CPU time 2.55 seconds
Started Jul 04 04:54:27 PM PDT 24
Finished Jul 04 04:54:30 PM PDT 24
Peak memory 213028 kb
Host smart-1b6b58ec-51f4-48d3-81c2-98055e01ba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760588707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.3760588707
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.2703025721
Short name T529
Test name
Test status
Simulation time 1639902663 ps
CPU time 6.65 seconds
Started Jul 04 04:54:29 PM PDT 24
Finished Jul 04 04:54:36 PM PDT 24
Peak memory 277548 kb
Host smart-9fcc446b-0b27-4012-8c30-c01940f3e33b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703025721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.2703025721
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.2127668426
Short name T891
Test name
Test status
Simulation time 1393070216 ps
CPU time 28.75 seconds
Started Jul 04 04:54:27 PM PDT 24
Finished Jul 04 04:54:56 PM PDT 24
Peak memory 221020 kb
Host smart-e430d836-9e0e-4304-b2c8-8547b8e60dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127668426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2127668426
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.525775170
Short name T387
Test name
Test status
Simulation time 1561720873 ps
CPU time 106.11 seconds
Started Jul 04 04:54:28 PM PDT 24
Finished Jul 04 04:56:14 PM PDT 24
Peak memory 577568 kb
Host smart-9ec34a31-5fbb-497f-9c97-43b659cd4d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525775170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.525775170
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1346888793
Short name T62
Test name
Test status
Simulation time 456374688 ps
CPU time 0.96 seconds
Started Jul 04 04:54:29 PM PDT 24
Finished Jul 04 04:54:30 PM PDT 24
Peak memory 204372 kb
Host smart-79a3a3ab-7edf-4824-a857-a68dc5227362
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346888793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1346888793
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.3686115045
Short name T159
Test name
Test status
Simulation time 1060583995 ps
CPU time 4.6 seconds
Started Jul 04 04:54:33 PM PDT 24
Finished Jul 04 04:54:38 PM PDT 24
Peak memory 230488 kb
Host smart-2655e1b0-b4da-4c9a-a639-2eb9082fe07c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686115045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.3686115045
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.1054487273
Short name T825
Test name
Test status
Simulation time 13384727593 ps
CPU time 222.85 seconds
Started Jul 04 04:54:25 PM PDT 24
Finished Jul 04 04:58:08 PM PDT 24
Peak memory 1007600 kb
Host smart-bba65beb-e979-4d39-b9cd-3bd068a53678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054487273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.1054487273
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.620878651
Short name T1050
Test name
Test status
Simulation time 999673204 ps
CPU time 7.78 seconds
Started Jul 04 04:54:28 PM PDT 24
Finished Jul 04 04:54:36 PM PDT 24
Peak memory 204756 kb
Host smart-049276ad-96f4-41f6-8618-fbc0486c8649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620878651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.620878651
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.3961097577
Short name T76
Test name
Test status
Simulation time 6420417528 ps
CPU time 77.53 seconds
Started Jul 04 04:54:30 PM PDT 24
Finished Jul 04 04:55:48 PM PDT 24
Peak memory 358864 kb
Host smart-8f69ae3c-7d8c-491d-9c26-5dc50817eb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961097577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.3961097577
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.3745604711
Short name T554
Test name
Test status
Simulation time 84767153 ps
CPU time 0.71 seconds
Started Jul 04 04:54:23 PM PDT 24
Finished Jul 04 04:54:25 PM PDT 24
Peak memory 204368 kb
Host smart-a8d4707f-9979-4302-bc6c-3de5fbcaf040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745604711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3745604711
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.3214047336
Short name T1415
Test name
Test status
Simulation time 6976196032 ps
CPU time 77.41 seconds
Started Jul 04 04:54:31 PM PDT 24
Finished Jul 04 04:55:49 PM PDT 24
Peak memory 218464 kb
Host smart-72088c89-d5a0-4132-ac06-0bdb14eb5ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214047336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.3214047336
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.2498721999
Short name T307
Test name
Test status
Simulation time 672200247 ps
CPU time 9.91 seconds
Started Jul 04 04:54:29 PM PDT 24
Finished Jul 04 04:54:39 PM PDT 24
Peak memory 204636 kb
Host smart-032869ac-e802-47a6-98fa-e2b90075db27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498721999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.2498721999
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2571583840
Short name T843
Test name
Test status
Simulation time 1959222853 ps
CPU time 34.66 seconds
Started Jul 04 04:54:21 PM PDT 24
Finished Jul 04 04:54:56 PM PDT 24
Peak memory 330348 kb
Host smart-6ab12c79-fd91-4688-800b-04f3019b0397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571583840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2571583840
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2710185635
Short name T119
Test name
Test status
Simulation time 104642553034 ps
CPU time 1577.7 seconds
Started Jul 04 04:54:32 PM PDT 24
Finished Jul 04 05:20:50 PM PDT 24
Peak memory 4382256 kb
Host smart-a8b4f2fd-f840-4433-bd00-563c0c9a5d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710185635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2710185635
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.4036292045
Short name T975
Test name
Test status
Simulation time 3908349568 ps
CPU time 29.74 seconds
Started Jul 04 04:54:30 PM PDT 24
Finished Jul 04 04:55:01 PM PDT 24
Peak memory 212828 kb
Host smart-4c1c4492-4258-40e2-b1e2-2c85216b1103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036292045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.4036292045
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.1745166780
Short name T468
Test name
Test status
Simulation time 1374558101 ps
CPU time 2.33 seconds
Started Jul 04 04:54:29 PM PDT 24
Finished Jul 04 04:54:32 PM PDT 24
Peak memory 204708 kb
Host smart-782c44ee-2cd7-4c73-8fb5-1a7ac8f7d26f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745166780 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.1745166780
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.2697739111
Short name T331
Test name
Test status
Simulation time 215353438 ps
CPU time 1.43 seconds
Started Jul 04 04:54:33 PM PDT 24
Finished Jul 04 04:54:35 PM PDT 24
Peak memory 204480 kb
Host smart-d16158e5-7b7f-425f-8591-65fecffb6e1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697739111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.2697739111
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.2459724938
Short name T330
Test name
Test status
Simulation time 160804113 ps
CPU time 1.06 seconds
Started Jul 04 04:54:28 PM PDT 24
Finished Jul 04 04:54:29 PM PDT 24
Peak memory 204476 kb
Host smart-4451bd9d-2e2a-4b62-9b1f-6952e7862bc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459724938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.2459724938
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.2178209406
Short name T1228
Test name
Test status
Simulation time 1526949671 ps
CPU time 2.16 seconds
Started Jul 04 04:54:32 PM PDT 24
Finished Jul 04 04:54:34 PM PDT 24
Peak memory 204632 kb
Host smart-d487d8e2-d8e1-481f-a353-832400e80acf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178209406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.2178209406
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.3156360067
Short name T1185
Test name
Test status
Simulation time 2960341146 ps
CPU time 1.27 seconds
Started Jul 04 04:54:28 PM PDT 24
Finished Jul 04 04:54:29 PM PDT 24
Peak memory 204508 kb
Host smart-1b4b855a-9d83-48f2-b558-c1f06738fab0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156360067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.3156360067
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.1222633120
Short name T429
Test name
Test status
Simulation time 1398883479 ps
CPU time 4.28 seconds
Started Jul 04 04:54:30 PM PDT 24
Finished Jul 04 04:54:34 PM PDT 24
Peak memory 204784 kb
Host smart-875b486e-4348-4b5e-8543-0af1ea860228
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222633120 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.1222633120
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.2810799754
Short name T393
Test name
Test status
Simulation time 15037345216 ps
CPU time 101.79 seconds
Started Jul 04 04:54:28 PM PDT 24
Finished Jul 04 04:56:10 PM PDT 24
Peak memory 1966432 kb
Host smart-b1f9b536-b0e5-4a59-949a-5d8a4f922f69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810799754 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.2810799754
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.3472391152
Short name T177
Test name
Test status
Simulation time 5890096446 ps
CPU time 25.31 seconds
Started Jul 04 04:54:29 PM PDT 24
Finished Jul 04 04:54:54 PM PDT 24
Peak memory 204824 kb
Host smart-be249d6f-b74a-4a19-b56c-ccc039a6d008
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472391152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.3472391152
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.496020344
Short name T832
Test name
Test status
Simulation time 1775499001 ps
CPU time 26.57 seconds
Started Jul 04 04:54:29 PM PDT 24
Finished Jul 04 04:54:55 PM PDT 24
Peak memory 236520 kb
Host smart-c553066f-25fe-4aea-98e4-34f40a184322
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496020344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c
_target_stress_rd.496020344
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2816327453
Short name T905
Test name
Test status
Simulation time 58074855074 ps
CPU time 196.17 seconds
Started Jul 04 04:54:32 PM PDT 24
Finished Jul 04 04:57:49 PM PDT 24
Peak memory 2347900 kb
Host smart-54dace36-b107-4713-a456-887d3c808045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816327453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2816327453
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.2819040330
Short name T243
Test name
Test status
Simulation time 20520765919 ps
CPU time 733.06 seconds
Started Jul 04 04:54:30 PM PDT 24
Finished Jul 04 05:06:43 PM PDT 24
Peak memory 2128324 kb
Host smart-9b48cff5-b4b3-41f6-bb4c-9f7fb298646d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819040330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.2819040330
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.285966923
Short name T262
Test name
Test status
Simulation time 6795297398 ps
CPU time 6.67 seconds
Started Jul 04 04:54:31 PM PDT 24
Finished Jul 04 04:54:38 PM PDT 24
Peak memory 221100 kb
Host smart-0691b319-1294-4692-9ec0-1fcdb37a1b5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285966923 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.285966923
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.3639747634
Short name T1086
Test name
Test status
Simulation time 73039647 ps
CPU time 1.72 seconds
Started Jul 04 04:54:28 PM PDT 24
Finished Jul 04 04:54:30 PM PDT 24
Peak memory 204740 kb
Host smart-34a5d167-81ed-4e5e-bacd-1c2ce86e55df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639747634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.3639747634
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.3989943926
Short name T1306
Test name
Test status
Simulation time 504995716 ps
CPU time 4.41 seconds
Started Jul 04 04:52:06 PM PDT 24
Finished Jul 04 04:52:11 PM PDT 24
Peak memory 217476 kb
Host smart-c275ae8a-bb8b-46e4-a823-07f115b96235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989943926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.3989943926
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.96600350
Short name T1447
Test name
Test status
Simulation time 408416801 ps
CPU time 8.25 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:52:16 PM PDT 24
Peak memory 285084 kb
Host smart-bcf25374-008f-4eb0-87d3-e3ec4741fb71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96600350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty.96600350
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.4184676215
Short name T1347
Test name
Test status
Simulation time 2899942730 ps
CPU time 115.72 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:54:03 PM PDT 24
Peak memory 899024 kb
Host smart-48a7defa-b6ab-4c2d-8833-9b1eca858abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184676215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.4184676215
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1135218368
Short name T593
Test name
Test status
Simulation time 13304825068 ps
CPU time 85.25 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:53:33 PM PDT 24
Peak memory 803040 kb
Host smart-07dec1bf-5b51-4036-992c-ec547a19106a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135218368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1135218368
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.1656436455
Short name T1072
Test name
Test status
Simulation time 412068057 ps
CPU time 1.13 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:52:08 PM PDT 24
Peak memory 204344 kb
Host smart-20f36936-d477-4e3f-a96b-536bd23cf9d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656436455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.1656436455
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.185033532
Short name T860
Test name
Test status
Simulation time 740725934 ps
CPU time 3.63 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:52:12 PM PDT 24
Peak memory 204712 kb
Host smart-14f73964-f955-4db1-a6d5-fb2fe0d5763a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185033532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.185033532
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.39860040
Short name T1269
Test name
Test status
Simulation time 5444737809 ps
CPU time 167.63 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:54:56 PM PDT 24
Peak memory 1538760 kb
Host smart-e7785c02-3306-4df0-933c-f0ef7d04e283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39860040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.39860040
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.1056491287
Short name T1328
Test name
Test status
Simulation time 872755072 ps
CPU time 3.98 seconds
Started Jul 04 04:52:09 PM PDT 24
Finished Jul 04 04:52:14 PM PDT 24
Peak memory 204672 kb
Host smart-58a0c7b6-6959-4a4c-853b-380741f35a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056491287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1056491287
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.3317783773
Short name T1292
Test name
Test status
Simulation time 4105038235 ps
CPU time 96.39 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:53:43 PM PDT 24
Peak memory 373372 kb
Host smart-33fc0e12-2efe-4108-a384-7dcc12d88bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317783773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3317783773
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1626256886
Short name T1386
Test name
Test status
Simulation time 24289688 ps
CPU time 0.65 seconds
Started Jul 04 04:52:06 PM PDT 24
Finished Jul 04 04:52:07 PM PDT 24
Peak memory 204412 kb
Host smart-feb815a0-347c-4c42-bce2-adc3da598087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626256886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1626256886
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.838762828
Short name T795
Test name
Test status
Simulation time 7397264994 ps
CPU time 103.5 seconds
Started Jul 04 04:52:11 PM PDT 24
Finished Jul 04 04:53:55 PM PDT 24
Peak memory 221836 kb
Host smart-e7a9617e-94c0-4ecd-be01-8ded41a6a4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838762828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.838762828
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.2448937773
Short name T920
Test name
Test status
Simulation time 76071548 ps
CPU time 1.73 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:52:09 PM PDT 24
Peak memory 204572 kb
Host smart-b4b09843-336b-4617-886d-f49f6a312650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448937773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.2448937773
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.4077781167
Short name T1521
Test name
Test status
Simulation time 3063498968 ps
CPU time 10.86 seconds
Started Jul 04 04:52:08 PM PDT 24
Finished Jul 04 04:52:19 PM PDT 24
Peak memory 262876 kb
Host smart-5c00e91a-a7f6-4e1e-b5df-5473bb4086bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077781167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.4077781167
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.1234679789
Short name T928
Test name
Test status
Simulation time 15465813675 ps
CPU time 779.57 seconds
Started Jul 04 04:52:08 PM PDT 24
Finished Jul 04 05:05:08 PM PDT 24
Peak memory 2701908 kb
Host smart-7816d423-5686-4c91-913d-cc4d698cc4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234679789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.1234679789
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.2716499036
Short name T273
Test name
Test status
Simulation time 3727205562 ps
CPU time 16.89 seconds
Started Jul 04 04:52:13 PM PDT 24
Finished Jul 04 04:52:31 PM PDT 24
Peak memory 229156 kb
Host smart-a3ef5936-08dd-4cb2-8475-18e0246c5a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716499036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.2716499036
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.196292771
Short name T190
Test name
Test status
Simulation time 39913292 ps
CPU time 0.86 seconds
Started Jul 04 04:52:10 PM PDT 24
Finished Jul 04 04:52:11 PM PDT 24
Peak memory 222060 kb
Host smart-89edf97a-675e-41e7-a070-031341878146
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196292771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.196292771
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.1987438015
Short name T1248
Test name
Test status
Simulation time 1963967532 ps
CPU time 4.95 seconds
Started Jul 04 04:52:08 PM PDT 24
Finished Jul 04 04:52:14 PM PDT 24
Peak memory 212884 kb
Host smart-aa76549d-12e2-4134-b799-ecdfe344b1d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987438015 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1987438015
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.957916434
Short name T951
Test name
Test status
Simulation time 150347883 ps
CPU time 0.99 seconds
Started Jul 04 04:52:11 PM PDT 24
Finished Jul 04 04:52:13 PM PDT 24
Peak memory 204508 kb
Host smart-c7f5af5b-bd3f-4df9-b308-ff99592907d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957916434 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_acq.957916434
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.2838557645
Short name T1218
Test name
Test status
Simulation time 410292555 ps
CPU time 1.44 seconds
Started Jul 04 04:52:08 PM PDT 24
Finished Jul 04 04:52:10 PM PDT 24
Peak memory 204752 kb
Host smart-664a3fa8-3099-4ceb-8956-1f78f82a1724
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838557645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.2838557645
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.1473059621
Short name T1317
Test name
Test status
Simulation time 1833215815 ps
CPU time 2.25 seconds
Started Jul 04 04:52:11 PM PDT 24
Finished Jul 04 04:52:14 PM PDT 24
Peak memory 204632 kb
Host smart-7f2a084a-ed01-4185-8b7a-31a654b68c40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473059621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.1473059621
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.1338382899
Short name T300
Test name
Test status
Simulation time 515889040 ps
CPU time 1.15 seconds
Started Jul 04 04:52:10 PM PDT 24
Finished Jul 04 04:52:11 PM PDT 24
Peak memory 204496 kb
Host smart-4330d5bd-aac4-4b56-be50-98d61f230568
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338382899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.1338382899
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.197757687
Short name T1442
Test name
Test status
Simulation time 1953958222 ps
CPU time 2.18 seconds
Started Jul 04 04:52:06 PM PDT 24
Finished Jul 04 04:52:08 PM PDT 24
Peak memory 204716 kb
Host smart-423a53a5-ddec-4453-80ce-db7c7cda873f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197757687 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.197757687
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2859606087
Short name T1214
Test name
Test status
Simulation time 5209428862 ps
CPU time 7.26 seconds
Started Jul 04 04:52:08 PM PDT 24
Finished Jul 04 04:52:16 PM PDT 24
Peak memory 213040 kb
Host smart-f150277c-ae00-4cdc-9c6a-55defdec8fdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859606087 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2859606087
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.3446946381
Short name T552
Test name
Test status
Simulation time 24196904268 ps
CPU time 174.88 seconds
Started Jul 04 04:52:08 PM PDT 24
Finished Jul 04 04:55:03 PM PDT 24
Peak memory 3044320 kb
Host smart-12a7f17a-3cc4-4774-8067-270c563ce278
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446946381 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3446946381
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.574018580
Short name T1467
Test name
Test status
Simulation time 2100768945 ps
CPU time 38.54 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:52:47 PM PDT 24
Peak memory 204712 kb
Host smart-0e9e2ca4-fcb7-4720-b8c9-35493767d316
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574018580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_targ
et_smoke.574018580
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.2391074393
Short name T169
Test name
Test status
Simulation time 828025162 ps
CPU time 12.44 seconds
Started Jul 04 04:52:13 PM PDT 24
Finished Jul 04 04:52:26 PM PDT 24
Peak memory 216672 kb
Host smart-718cf429-d719-47c8-a623-5b1e7c28cfbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391074393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.2391074393
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.3562791930
Short name T707
Test name
Test status
Simulation time 22460359794 ps
CPU time 13.01 seconds
Started Jul 04 04:52:06 PM PDT 24
Finished Jul 04 04:52:20 PM PDT 24
Peak memory 204736 kb
Host smart-3357879d-bdd7-4350-9e2d-f63e21458cf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562791930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.3562791930
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.716749496
Short name T213
Test name
Test status
Simulation time 29841976719 ps
CPU time 211 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:55:38 PM PDT 24
Peak memory 1937772 kb
Host smart-dfaf899a-ace5-405e-9096-d9c0f3cf0140
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716749496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_ta
rget_stretch.716749496
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.3262579072
Short name T1130
Test name
Test status
Simulation time 5610626324 ps
CPU time 7.81 seconds
Started Jul 04 04:52:07 PM PDT 24
Finished Jul 04 04:52:16 PM PDT 24
Peak memory 221080 kb
Host smart-046d42fd-590b-47c3-aca3-3c063734522d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262579072 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.3262579072
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.2753509959
Short name T545
Test name
Test status
Simulation time 450938599 ps
CPU time 6.27 seconds
Started Jul 04 04:52:09 PM PDT 24
Finished Jul 04 04:52:15 PM PDT 24
Peak memory 204640 kb
Host smart-a80036fa-2e0b-4e0b-b016-cb0e3e7002ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753509959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.2753509959
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.390375229
Short name T1368
Test name
Test status
Simulation time 27278536 ps
CPU time 0.63 seconds
Started Jul 04 04:54:40 PM PDT 24
Finished Jul 04 04:54:41 PM PDT 24
Peak memory 204356 kb
Host smart-d62c7ff9-1924-4dda-b3df-60a9d895d341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390375229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.390375229
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.2288477895
Short name T986
Test name
Test status
Simulation time 418345630 ps
CPU time 2.4 seconds
Started Jul 04 04:54:34 PM PDT 24
Finished Jul 04 04:54:37 PM PDT 24
Peak memory 213020 kb
Host smart-e5cc5715-6e0e-4215-a530-9487ad9ea777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288477895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.2288477895
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1843969816
Short name T416
Test name
Test status
Simulation time 729133883 ps
CPU time 13.38 seconds
Started Jul 04 04:54:33 PM PDT 24
Finished Jul 04 04:54:47 PM PDT 24
Peak memory 242960 kb
Host smart-eb39d8a2-216c-4be6-9991-15de300af3a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843969816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1843969816
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.941066991
Short name T156
Test name
Test status
Simulation time 2401622751 ps
CPU time 75.98 seconds
Started Jul 04 04:54:35 PM PDT 24
Finished Jul 04 04:55:51 PM PDT 24
Peak memory 634336 kb
Host smart-d45fc0bf-26f4-4779-a9e6-1b303c967eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941066991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.941066991
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.62845053
Short name T349
Test name
Test status
Simulation time 2805123396 ps
CPU time 89.36 seconds
Started Jul 04 04:54:29 PM PDT 24
Finished Jul 04 04:55:58 PM PDT 24
Peak memory 884940 kb
Host smart-de58e53c-02ec-458e-8b83-38fe6f9294fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62845053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.62845053
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.1388961299
Short name T477
Test name
Test status
Simulation time 1856618286 ps
CPU time 11.29 seconds
Started Jul 04 04:54:34 PM PDT 24
Finished Jul 04 04:54:46 PM PDT 24
Peak memory 239804 kb
Host smart-52d55312-5134-42c1-ab42-b67445db9dc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388961299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.1388961299
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.125107963
Short name T997
Test name
Test status
Simulation time 4175152965 ps
CPU time 292.86 seconds
Started Jul 04 04:54:32 PM PDT 24
Finished Jul 04 04:59:25 PM PDT 24
Peak memory 1225856 kb
Host smart-1f46268a-3d2f-4655-982a-0abe8a20d41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125107963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.125107963
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.3902572000
Short name T737
Test name
Test status
Simulation time 3769267006 ps
CPU time 11.42 seconds
Started Jul 04 04:54:34 PM PDT 24
Finished Jul 04 04:54:45 PM PDT 24
Peak memory 204748 kb
Host smart-2b7fd7a4-5c15-4789-9331-b7b27927eab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902572000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.3902572000
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3024076941
Short name T538
Test name
Test status
Simulation time 6669518722 ps
CPU time 74.31 seconds
Started Jul 04 04:54:32 PM PDT 24
Finished Jul 04 04:55:47 PM PDT 24
Peak memory 296792 kb
Host smart-ff41c1af-39cc-4d7f-9900-30df9747981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024076941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3024076941
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.2883085164
Short name T1303
Test name
Test status
Simulation time 20860809 ps
CPU time 0.64 seconds
Started Jul 04 04:54:33 PM PDT 24
Finished Jul 04 04:54:34 PM PDT 24
Peak memory 204392 kb
Host smart-e5740bf3-801d-402e-9b22-79391106de80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883085164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.2883085164
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.1908769892
Short name T715
Test name
Test status
Simulation time 5769569050 ps
CPU time 44.86 seconds
Started Jul 04 04:54:36 PM PDT 24
Finished Jul 04 04:55:22 PM PDT 24
Peak memory 205712 kb
Host smart-f6fadf45-f1aa-48c1-93f2-628a9b995e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908769892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.1908769892
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.3254193285
Short name T161
Test name
Test status
Simulation time 24262149245 ps
CPU time 1290.26 seconds
Started Jul 04 04:54:36 PM PDT 24
Finished Jul 04 05:16:07 PM PDT 24
Peak memory 905664 kb
Host smart-1ac6d7d8-9f9d-4688-ac8b-64c2b9e6025d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254193285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.3254193285
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.2513508635
Short name T472
Test name
Test status
Simulation time 6877961374 ps
CPU time 23.79 seconds
Started Jul 04 04:54:30 PM PDT 24
Finished Jul 04 04:54:55 PM PDT 24
Peak memory 293988 kb
Host smart-295f41fc-90cc-42c9-abcd-1a76c8330151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513508635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.2513508635
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.1892445415
Short name T264
Test name
Test status
Simulation time 23893399253 ps
CPU time 492.86 seconds
Started Jul 04 04:54:33 PM PDT 24
Finished Jul 04 05:02:46 PM PDT 24
Peak memory 1514096 kb
Host smart-620e08d6-7db3-4e76-8962-8045e4d46ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892445415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.1892445415
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.13241730
Short name T1350
Test name
Test status
Simulation time 701802783 ps
CPU time 32.46 seconds
Started Jul 04 04:54:36 PM PDT 24
Finished Jul 04 04:55:09 PM PDT 24
Peak memory 212888 kb
Host smart-2aa671c8-7ed3-4ecd-844f-f243bd8635b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13241730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.13241730
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3068007441
Short name T1103
Test name
Test status
Simulation time 422700917 ps
CPU time 2.88 seconds
Started Jul 04 04:54:37 PM PDT 24
Finished Jul 04 04:54:40 PM PDT 24
Peak memory 204728 kb
Host smart-ea23b109-bdf8-4426-b020-ae15cbf821be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068007441 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3068007441
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.409352945
Short name T854
Test name
Test status
Simulation time 245177779 ps
CPU time 1.59 seconds
Started Jul 04 04:54:34 PM PDT 24
Finished Jul 04 04:54:35 PM PDT 24
Peak memory 204708 kb
Host smart-cc15652b-690f-46fa-830f-d29f2aab5eda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409352945 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.409352945
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.1791766347
Short name T284
Test name
Test status
Simulation time 552992854 ps
CPU time 1.27 seconds
Started Jul 04 04:54:35 PM PDT 24
Finished Jul 04 04:54:37 PM PDT 24
Peak memory 204852 kb
Host smart-6e9c5dfb-99c5-42f5-906f-730477f20d9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791766347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.1791766347
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.2719898038
Short name T1322
Test name
Test status
Simulation time 489633457 ps
CPU time 2.5 seconds
Started Jul 04 04:54:36 PM PDT 24
Finished Jul 04 04:54:39 PM PDT 24
Peak memory 204632 kb
Host smart-bcf646a1-816c-4516-8102-23a0960b6016
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719898038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.2719898038
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.695601080
Short name T1280
Test name
Test status
Simulation time 237598807 ps
CPU time 1.12 seconds
Started Jul 04 04:54:33 PM PDT 24
Finished Jul 04 04:54:34 PM PDT 24
Peak memory 204564 kb
Host smart-08829cc9-621c-4be0-97dd-4428009ad2d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695601080 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.695601080
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.1591566299
Short name T128
Test name
Test status
Simulation time 662516511 ps
CPU time 3.6 seconds
Started Jul 04 04:54:36 PM PDT 24
Finished Jul 04 04:54:40 PM PDT 24
Peak memory 204700 kb
Host smart-ed9fe22c-da89-4fe6-b448-826cf76102ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591566299 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.1591566299
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.3825759564
Short name T984
Test name
Test status
Simulation time 4190424185 ps
CPU time 5.81 seconds
Started Jul 04 04:54:33 PM PDT 24
Finished Jul 04 04:54:40 PM PDT 24
Peak memory 218680 kb
Host smart-4bfbacf5-eff6-4347-acdc-c613de7600d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825759564 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.3825759564
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.4291869353
Short name T1148
Test name
Test status
Simulation time 20348837671 ps
CPU time 48.37 seconds
Started Jul 04 04:54:35 PM PDT 24
Finished Jul 04 04:55:23 PM PDT 24
Peak memory 1188924 kb
Host smart-7e1992b0-e343-4758-a1e2-23deecb7fdf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291869353 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.4291869353
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.1621310538
Short name T709
Test name
Test status
Simulation time 854135449 ps
CPU time 12.89 seconds
Started Jul 04 04:54:37 PM PDT 24
Finished Jul 04 04:54:50 PM PDT 24
Peak memory 204728 kb
Host smart-7276d9db-4325-4b6c-b0ce-57e77d39feff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621310538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.1621310538
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2547964492
Short name T91
Test name
Test status
Simulation time 6430091440 ps
CPU time 25.15 seconds
Started Jul 04 04:54:35 PM PDT 24
Finished Jul 04 04:55:01 PM PDT 24
Peak memory 223448 kb
Host smart-bc98388f-b6f1-47fa-8e6d-d9830567f1d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547964492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2547964492
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.979305638
Short name T996
Test name
Test status
Simulation time 56825634825 ps
CPU time 1412.44 seconds
Started Jul 04 04:54:36 PM PDT 24
Finished Jul 04 05:18:09 PM PDT 24
Peak memory 9023972 kb
Host smart-a9f22265-953d-4646-b643-9bda060119be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979305638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_wr.979305638
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.1737560732
Short name T889
Test name
Test status
Simulation time 1220145924 ps
CPU time 7.15 seconds
Started Jul 04 04:54:35 PM PDT 24
Finished Jul 04 04:54:43 PM PDT 24
Peak memory 220948 kb
Host smart-630be8be-2060-4131-9b86-65d7081e5689
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737560732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.1737560732
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.3067044826
Short name T1233
Test name
Test status
Simulation time 671239660 ps
CPU time 8 seconds
Started Jul 04 04:54:35 PM PDT 24
Finished Jul 04 04:54:43 PM PDT 24
Peak memory 204664 kb
Host smart-02d17450-8f2a-4d3b-b2dd-83d86fed902d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067044826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.3067044826
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3734068665
Short name T937
Test name
Test status
Simulation time 33847694 ps
CPU time 0.65 seconds
Started Jul 04 04:54:48 PM PDT 24
Finished Jul 04 04:54:49 PM PDT 24
Peak memory 204400 kb
Host smart-d42fec70-cf75-4749-a0f7-4fa7758229c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734068665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3734068665
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.3723168624
Short name T521
Test name
Test status
Simulation time 67828406 ps
CPU time 1.21 seconds
Started Jul 04 04:54:43 PM PDT 24
Finished Jul 04 04:54:44 PM PDT 24
Peak memory 204812 kb
Host smart-3f678180-2f30-4245-8b54-ca0d066633f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723168624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.3723168624
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.3577270765
Short name T893
Test name
Test status
Simulation time 9138686740 ps
CPU time 26.11 seconds
Started Jul 04 04:54:42 PM PDT 24
Finished Jul 04 04:55:08 PM PDT 24
Peak memory 310988 kb
Host smart-71b8cc10-167d-4254-b497-bb741e19a318
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577270765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.3577270765
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.1872850926
Short name T639
Test name
Test status
Simulation time 11261861918 ps
CPU time 81.44 seconds
Started Jul 04 04:54:42 PM PDT 24
Finished Jul 04 04:56:04 PM PDT 24
Peak memory 712976 kb
Host smart-f408af8c-c9c5-4c88-b9aa-c3e67ac3f648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872850926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1872850926
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.2148647837
Short name T1382
Test name
Test status
Simulation time 1432070911 ps
CPU time 45.42 seconds
Started Jul 04 04:54:43 PM PDT 24
Finished Jul 04 04:55:29 PM PDT 24
Peak memory 544436 kb
Host smart-01db8cbe-8c42-4873-aa9e-952dde1750df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148647837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2148647837
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.319702643
Short name T923
Test name
Test status
Simulation time 252969365 ps
CPU time 0.81 seconds
Started Jul 04 04:54:41 PM PDT 24
Finished Jul 04 04:54:42 PM PDT 24
Peak memory 204356 kb
Host smart-4e772506-b32c-4f57-a39e-b804b435a733
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319702643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fm
t.319702643
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3786864473
Short name T1048
Test name
Test status
Simulation time 217024779 ps
CPU time 4.97 seconds
Started Jul 04 04:54:42 PM PDT 24
Finished Jul 04 04:54:47 PM PDT 24
Peak memory 204676 kb
Host smart-fbfcf591-6a9a-4350-bffd-293a99bfc852
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786864473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3786864473
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.101614310
Short name T1281
Test name
Test status
Simulation time 3021050660 ps
CPU time 65.18 seconds
Started Jul 04 04:54:42 PM PDT 24
Finished Jul 04 04:55:48 PM PDT 24
Peak memory 887812 kb
Host smart-1feb0303-0d1d-4a1c-a69c-15402c262187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101614310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.101614310
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.1850407842
Short name T648
Test name
Test status
Simulation time 3197423692 ps
CPU time 31.28 seconds
Started Jul 04 04:54:50 PM PDT 24
Finished Jul 04 04:55:21 PM PDT 24
Peak memory 204736 kb
Host smart-7bfa1bfa-40ca-48a4-bb25-084de80ce481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850407842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.1850407842
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.716755485
Short name T1278
Test name
Test status
Simulation time 9196733559 ps
CPU time 40.84 seconds
Started Jul 04 04:54:49 PM PDT 24
Finished Jul 04 04:55:30 PM PDT 24
Peak memory 342672 kb
Host smart-ad6714d2-78e4-4001-8d47-8e800da205c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716755485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.716755485
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.1364736297
Short name T380
Test name
Test status
Simulation time 26880392 ps
CPU time 0.68 seconds
Started Jul 04 04:54:43 PM PDT 24
Finished Jul 04 04:54:44 PM PDT 24
Peak memory 204416 kb
Host smart-2e2cab5b-9919-4020-935a-2fecc9909ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364736297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1364736297
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.747664266
Short name T63
Test name
Test status
Simulation time 7942450755 ps
CPU time 12.77 seconds
Started Jul 04 04:54:41 PM PDT 24
Finished Jul 04 04:54:54 PM PDT 24
Peak memory 204852 kb
Host smart-91df10d9-b67f-44b5-99b9-9b5e5c3f2870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747664266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.747664266
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.1603245057
Short name T794
Test name
Test status
Simulation time 219970412 ps
CPU time 10.29 seconds
Started Jul 04 04:54:41 PM PDT 24
Finished Jul 04 04:54:52 PM PDT 24
Peak memory 242208 kb
Host smart-56799f2d-14d5-4ed0-b95d-6da6e2c4b51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603245057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.1603245057
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.2510079223
Short name T797
Test name
Test status
Simulation time 5587000560 ps
CPU time 24.5 seconds
Started Jul 04 04:54:44 PM PDT 24
Finished Jul 04 04:55:09 PM PDT 24
Peak memory 311556 kb
Host smart-0400225b-d022-43b0-87ae-4dde5be240be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510079223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.2510079223
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.3848890349
Short name T995
Test name
Test status
Simulation time 1870955009 ps
CPU time 31.16 seconds
Started Jul 04 04:54:41 PM PDT 24
Finished Jul 04 04:55:12 PM PDT 24
Peak memory 212912 kb
Host smart-feadb4c5-d0a4-4fc8-b871-105a1cdcdaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848890349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.3848890349
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.1814544541
Short name T360
Test name
Test status
Simulation time 618975399 ps
CPU time 3.71 seconds
Started Jul 04 04:54:48 PM PDT 24
Finished Jul 04 04:54:52 PM PDT 24
Peak memory 212924 kb
Host smart-064d2688-52ff-4592-b3e3-fbbf8323d445
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814544541 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.1814544541
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.3487952195
Short name T1336
Test name
Test status
Simulation time 481551364 ps
CPU time 1.08 seconds
Started Jul 04 04:54:41 PM PDT 24
Finished Jul 04 04:54:42 PM PDT 24
Peak memory 204704 kb
Host smart-839a80b2-b291-4830-bbc0-2f6a615a4a64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487952195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.3487952195
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3831690906
Short name T1270
Test name
Test status
Simulation time 480978309 ps
CPU time 1.08 seconds
Started Jul 04 04:54:49 PM PDT 24
Finished Jul 04 04:54:50 PM PDT 24
Peak memory 204592 kb
Host smart-f6a3d2ae-896d-450e-bd0e-da061a65f45c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831690906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3831690906
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.4230071580
Short name T410
Test name
Test status
Simulation time 428836244 ps
CPU time 1.4 seconds
Started Jul 04 04:54:50 PM PDT 24
Finished Jul 04 04:54:52 PM PDT 24
Peak memory 204488 kb
Host smart-f84ce0e4-805b-4b7f-9403-87e518105e81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230071580 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.4230071580
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.1202519494
Short name T322
Test name
Test status
Simulation time 423346302 ps
CPU time 1.18 seconds
Started Jul 04 04:54:57 PM PDT 24
Finished Jul 04 04:54:58 PM PDT 24
Peak memory 204500 kb
Host smart-8092e808-2bc3-4e89-8306-ce2a394c286e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202519494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.1202519494
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.4226914286
Short name T27
Test name
Test status
Simulation time 653503196 ps
CPU time 2.78 seconds
Started Jul 04 04:54:48 PM PDT 24
Finished Jul 04 04:54:51 PM PDT 24
Peak memory 204708 kb
Host smart-7aa4e543-e95b-4458-899b-99e50f55fa9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226914286 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.4226914286
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3170738364
Short name T1124
Test name
Test status
Simulation time 3808942035 ps
CPU time 4.49 seconds
Started Jul 04 04:54:41 PM PDT 24
Finished Jul 04 04:54:46 PM PDT 24
Peak memory 212900 kb
Host smart-fc3f6c0e-960a-4412-b0e1-04b4917b3afa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170738364 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3170738364
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.3024405081
Short name T1133
Test name
Test status
Simulation time 26143679789 ps
CPU time 552.66 seconds
Started Jul 04 04:54:42 PM PDT 24
Finished Jul 04 05:03:55 PM PDT 24
Peak memory 6198144 kb
Host smart-7147f394-bbd9-45d5-a456-899aa0041d80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024405081 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.3024405081
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.3050819790
Short name T1018
Test name
Test status
Simulation time 3932983666 ps
CPU time 33.99 seconds
Started Jul 04 04:54:42 PM PDT 24
Finished Jul 04 04:55:17 PM PDT 24
Peak memory 204764 kb
Host smart-f0cec131-2e51-445c-82ea-ebe5f6ef9e60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050819790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.3050819790
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.4290383580
Short name T1171
Test name
Test status
Simulation time 923812004 ps
CPU time 40.75 seconds
Started Jul 04 04:54:42 PM PDT 24
Finished Jul 04 04:55:23 PM PDT 24
Peak memory 204692 kb
Host smart-5394a470-9a80-4666-9483-6657a50d9c2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290383580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.4290383580
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.3819316125
Short name T461
Test name
Test status
Simulation time 40444173412 ps
CPU time 189.47 seconds
Started Jul 04 04:54:44 PM PDT 24
Finished Jul 04 04:57:54 PM PDT 24
Peak memory 2579620 kb
Host smart-c55ac84f-4ae1-4fab-9b2a-51e0acadc1d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819316125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.3819316125
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.1114858368
Short name T1287
Test name
Test status
Simulation time 18197508614 ps
CPU time 2423.35 seconds
Started Jul 04 04:54:40 PM PDT 24
Finished Jul 04 05:35:04 PM PDT 24
Peak memory 4217520 kb
Host smart-a537574a-1930-43b8-a791-fc465c3b1cf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114858368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.1114858368
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2873271392
Short name T696
Test name
Test status
Simulation time 1343622551 ps
CPU time 7.03 seconds
Started Jul 04 04:54:43 PM PDT 24
Finished Jul 04 04:54:50 PM PDT 24
Peak memory 211664 kb
Host smart-5a7c81bf-7896-4c43-b789-824335a31e02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873271392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2873271392
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.2481838867
Short name T374
Test name
Test status
Simulation time 216718591 ps
CPU time 3.7 seconds
Started Jul 04 04:54:47 PM PDT 24
Finished Jul 04 04:54:50 PM PDT 24
Peak memory 204784 kb
Host smart-0a53a0ff-19de-4b5e-bc2a-fc6b92b70958
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481838867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.2481838867
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3089615996
Short name T1511
Test name
Test status
Simulation time 51852243 ps
CPU time 0.65 seconds
Started Jul 04 04:54:53 PM PDT 24
Finished Jul 04 04:54:54 PM PDT 24
Peak memory 204376 kb
Host smart-5f4d6693-78a3-49c9-a17f-25315baab038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089615996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3089615996
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.1492214572
Short name T39
Test name
Test status
Simulation time 495618260 ps
CPU time 2.95 seconds
Started Jul 04 04:54:57 PM PDT 24
Finished Jul 04 04:55:00 PM PDT 24
Peak memory 215408 kb
Host smart-235e0250-9023-4d5d-9dd9-a1494023005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492214572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.1492214572
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1006949870
Short name T483
Test name
Test status
Simulation time 312204304 ps
CPU time 7.19 seconds
Started Jul 04 04:54:48 PM PDT 24
Finished Jul 04 04:54:56 PM PDT 24
Peak memory 269224 kb
Host smart-cc4c4c37-ec83-41e3-857d-992654444d4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006949870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1006949870
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3609633268
Short name T1131
Test name
Test status
Simulation time 2361895888 ps
CPU time 68.43 seconds
Started Jul 04 04:54:57 PM PDT 24
Finished Jul 04 04:56:06 PM PDT 24
Peak memory 725788 kb
Host smart-9bd45a24-8fcc-45e4-9869-c2c8459206a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609633268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3609633268
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2359216307
Short name T1425
Test name
Test status
Simulation time 7170446454 ps
CPU time 121.39 seconds
Started Jul 04 04:54:49 PM PDT 24
Finished Jul 04 04:56:50 PM PDT 24
Peak memory 632744 kb
Host smart-3bd7e796-32ca-4aba-815b-cd48fe6dc8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359216307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2359216307
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.397466532
Short name T1101
Test name
Test status
Simulation time 519123003 ps
CPU time 1.1 seconds
Started Jul 04 04:54:49 PM PDT 24
Finished Jul 04 04:54:50 PM PDT 24
Peak memory 204440 kb
Host smart-d9ff45a5-0608-485e-9a9f-e148fdc9cf46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397466532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fm
t.397466532
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.24622113
Short name T1335
Test name
Test status
Simulation time 880195919 ps
CPU time 3.33 seconds
Started Jul 04 04:54:47 PM PDT 24
Finished Jul 04 04:54:51 PM PDT 24
Peak memory 204716 kb
Host smart-3cbe9af6-abba-401f-8fc4-7480c91ad616
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24622113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.24622113
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.4100903000
Short name T1439
Test name
Test status
Simulation time 4692688689 ps
CPU time 308.07 seconds
Started Jul 04 04:54:49 PM PDT 24
Finished Jul 04 04:59:57 PM PDT 24
Peak memory 1329452 kb
Host smart-e0c0d3d8-40ec-4e19-b224-d0dbc8956d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100903000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.4100903000
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.2655818213
Short name T45
Test name
Test status
Simulation time 1141010465 ps
CPU time 21.7 seconds
Started Jul 04 04:54:57 PM PDT 24
Finished Jul 04 04:55:19 PM PDT 24
Peak memory 204744 kb
Host smart-44b330fb-9cd7-495d-942e-73fa9a1969dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655818213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.2655818213
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.3059939057
Short name T691
Test name
Test status
Simulation time 14146577066 ps
CPU time 95.58 seconds
Started Jul 04 04:54:57 PM PDT 24
Finished Jul 04 04:56:33 PM PDT 24
Peak memory 352248 kb
Host smart-8d0cc79e-1483-49d6-80d8-6d229bb83c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059939057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3059939057
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.3857344814
Short name T396
Test name
Test status
Simulation time 89743555 ps
CPU time 0.64 seconds
Started Jul 04 04:54:57 PM PDT 24
Finished Jul 04 04:54:58 PM PDT 24
Peak memory 204408 kb
Host smart-ae33d1e6-f2df-46fc-998e-5a778d768ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857344814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.3857344814
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.2230323881
Short name T1378
Test name
Test status
Simulation time 27632131799 ps
CPU time 182.91 seconds
Started Jul 04 04:54:47 PM PDT 24
Finished Jul 04 04:57:50 PM PDT 24
Peak memory 213056 kb
Host smart-3200579d-3520-4d05-8e15-455f6341e8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230323881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2230323881
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.3988940378
Short name T484
Test name
Test status
Simulation time 6599361951 ps
CPU time 68.35 seconds
Started Jul 04 04:54:49 PM PDT 24
Finished Jul 04 04:55:58 PM PDT 24
Peak memory 506948 kb
Host smart-e87f320a-d80c-4d03-9704-eca49614aaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988940378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.3988940378
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.1923286362
Short name T384
Test name
Test status
Simulation time 4001056496 ps
CPU time 35.93 seconds
Started Jul 04 04:54:48 PM PDT 24
Finished Jul 04 04:55:25 PM PDT 24
Peak memory 279376 kb
Host smart-c72fcaec-ae4a-47cf-bee7-e2aa1eead1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923286362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1923286362
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.1772940827
Short name T47
Test name
Test status
Simulation time 13940864327 ps
CPU time 817.86 seconds
Started Jul 04 04:54:53 PM PDT 24
Finished Jul 04 05:08:31 PM PDT 24
Peak memory 3008364 kb
Host smart-93adf2b8-009c-422c-a691-8a61797acf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772940827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.1772940827
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.32743932
Short name T495
Test name
Test status
Simulation time 713379115 ps
CPU time 10.98 seconds
Started Jul 04 04:54:47 PM PDT 24
Finished Jul 04 04:54:58 PM PDT 24
Peak memory 221100 kb
Host smart-b3584921-595a-422b-896f-e833ec3a1837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32743932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.32743932
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.597089088
Short name T401
Test name
Test status
Simulation time 742031320 ps
CPU time 4.02 seconds
Started Jul 04 04:54:55 PM PDT 24
Finished Jul 04 04:54:59 PM PDT 24
Peak memory 212828 kb
Host smart-3bdf103f-95e6-4064-a39b-5d713b5f492d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597089088 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.597089088
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.939795951
Short name T1310
Test name
Test status
Simulation time 264624479 ps
CPU time 1.12 seconds
Started Jul 04 04:54:57 PM PDT 24
Finished Jul 04 04:54:58 PM PDT 24
Peak memory 212716 kb
Host smart-2c5747ba-aca6-40ed-bff7-33f90d8e173b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939795951 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_acq.939795951
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.57786742
Short name T553
Test name
Test status
Simulation time 797444920 ps
CPU time 2.24 seconds
Started Jul 04 04:54:55 PM PDT 24
Finished Jul 04 04:54:57 PM PDT 24
Peak memory 204668 kb
Host smart-c5cce862-c738-47ac-b592-f6fb7040fe48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57786742 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.57786742
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.1525412781
Short name T136
Test name
Test status
Simulation time 125600756 ps
CPU time 1.19 seconds
Started Jul 04 04:54:55 PM PDT 24
Finished Jul 04 04:54:56 PM PDT 24
Peak memory 204524 kb
Host smart-ff971f7a-4a83-47ae-aea5-d54d0f9d3148
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525412781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.1525412781
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.2577898206
Short name T1402
Test name
Test status
Simulation time 1477027116 ps
CPU time 4.23 seconds
Started Jul 04 04:54:57 PM PDT 24
Finished Jul 04 04:55:02 PM PDT 24
Peak memory 204692 kb
Host smart-2b29b969-2083-45fb-acea-3a33efe0aa2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577898206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.2577898206
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.1776011443
Short name T1219
Test name
Test status
Simulation time 4170918351 ps
CPU time 6.5 seconds
Started Jul 04 04:54:55 PM PDT 24
Finished Jul 04 04:55:02 PM PDT 24
Peak memory 216768 kb
Host smart-b666e63f-8093-4cbb-a407-f8a34a1ca63b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776011443 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.1776011443
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.17594856
Short name T1422
Test name
Test status
Simulation time 17698916276 ps
CPU time 94.34 seconds
Started Jul 04 04:54:56 PM PDT 24
Finished Jul 04 04:56:31 PM PDT 24
Peak memory 1300680 kb
Host smart-aba6eecc-1823-4b6d-ba92-e088a54e479b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17594856 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.17594856
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.1146749979
Short name T1315
Test name
Test status
Simulation time 1017290487 ps
CPU time 39.16 seconds
Started Jul 04 04:54:56 PM PDT 24
Finished Jul 04 04:55:36 PM PDT 24
Peak memory 204620 kb
Host smart-6713f4e1-9117-41c9-8282-20a2340068b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146749979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.1146749979
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1693364929
Short name T1021
Test name
Test status
Simulation time 1749520270 ps
CPU time 19.54 seconds
Started Jul 04 04:54:56 PM PDT 24
Finished Jul 04 04:55:15 PM PDT 24
Peak memory 204720 kb
Host smart-dcf1f548-a032-4808-a2f2-6f1cdc88b838
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693364929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1693364929
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.3505822654
Short name T1485
Test name
Test status
Simulation time 7274486863 ps
CPU time 14.04 seconds
Started Jul 04 04:54:56 PM PDT 24
Finished Jul 04 04:55:10 PM PDT 24
Peak memory 204516 kb
Host smart-cd37f126-1973-47a2-8277-2a065a335208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505822654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.3505822654
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.627344516
Short name T372
Test name
Test status
Simulation time 1504252945 ps
CPU time 7.46 seconds
Started Jul 04 04:54:56 PM PDT 24
Finished Jul 04 04:55:04 PM PDT 24
Peak memory 220992 kb
Host smart-9f809074-0de7-4f1c-a49a-97f7fc38401e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627344516 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.627344516
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.3605387535
Short name T17
Test name
Test status
Simulation time 167697470 ps
CPU time 3.57 seconds
Started Jul 04 04:54:57 PM PDT 24
Finished Jul 04 04:55:01 PM PDT 24
Peak memory 204740 kb
Host smart-94b28338-1ef3-4fe9-bd20-22ad2a83421e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605387535 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.3605387535
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2633779479
Short name T482
Test name
Test status
Simulation time 28984955 ps
CPU time 0.63 seconds
Started Jul 04 04:55:04 PM PDT 24
Finished Jul 04 04:55:04 PM PDT 24
Peak memory 204324 kb
Host smart-149923a2-4014-4eb3-9ff4-9e5aca23e254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633779479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2633779479
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.4038570559
Short name T1460
Test name
Test status
Simulation time 116127072 ps
CPU time 3.83 seconds
Started Jul 04 04:54:57 PM PDT 24
Finished Jul 04 04:55:01 PM PDT 24
Peak memory 221008 kb
Host smart-318529b7-c281-43ab-9b95-7f6de3742847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038570559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.4038570559
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.849068781
Short name T293
Test name
Test status
Simulation time 741351639 ps
CPU time 6.63 seconds
Started Jul 04 04:54:57 PM PDT 24
Finished Jul 04 04:55:04 PM PDT 24
Peak memory 278096 kb
Host smart-733fd15a-2c3d-4678-9dce-57f369ad0c15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849068781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.849068781
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.3172880626
Short name T88
Test name
Test status
Simulation time 4442495154 ps
CPU time 73.68 seconds
Started Jul 04 04:54:55 PM PDT 24
Finished Jul 04 04:56:09 PM PDT 24
Peak memory 678392 kb
Host smart-bda61853-0c4b-41da-a704-c10df2e8a206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172880626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.3172880626
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.337425394
Short name T784
Test name
Test status
Simulation time 23692843763 ps
CPU time 147.5 seconds
Started Jul 04 04:54:55 PM PDT 24
Finished Jul 04 04:57:22 PM PDT 24
Peak memory 615392 kb
Host smart-6636ba0b-5bde-4f0d-a203-63d4bab04ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337425394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.337425394
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.1847301881
Short name T433
Test name
Test status
Simulation time 365524302 ps
CPU time 0.81 seconds
Started Jul 04 04:54:56 PM PDT 24
Finished Jul 04 04:54:57 PM PDT 24
Peak memory 204332 kb
Host smart-822aba6d-ad52-401f-a302-a83fa5d7ba96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847301881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.1847301881
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.483897660
Short name T1202
Test name
Test status
Simulation time 115766013 ps
CPU time 2.99 seconds
Started Jul 04 04:55:00 PM PDT 24
Finished Jul 04 04:55:03 PM PDT 24
Peak memory 204740 kb
Host smart-17dc4c56-1863-4a1c-a3bf-18d7ffa2611e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483897660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.
483897660
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.1727184744
Short name T114
Test name
Test status
Simulation time 7827424272 ps
CPU time 158.74 seconds
Started Jul 04 04:54:55 PM PDT 24
Finished Jul 04 04:57:34 PM PDT 24
Peak memory 1560376 kb
Host smart-9270a460-28f3-49e9-9769-31486062e4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727184744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1727184744
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.617266603
Short name T1495
Test name
Test status
Simulation time 731668202 ps
CPU time 28.12 seconds
Started Jul 04 04:55:02 PM PDT 24
Finished Jul 04 04:55:31 PM PDT 24
Peak memory 204676 kb
Host smart-886596ff-4971-42cd-8332-8865702b83e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617266603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.617266603
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.2911590771
Short name T99
Test name
Test status
Simulation time 197261472 ps
CPU time 0.65 seconds
Started Jul 04 04:54:58 PM PDT 24
Finished Jul 04 04:54:59 PM PDT 24
Peak memory 204500 kb
Host smart-050cd510-6cac-43ed-be81-2b2969072e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911590771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.2911590771
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3018780762
Short name T64
Test name
Test status
Simulation time 2000160717 ps
CPU time 91.11 seconds
Started Jul 04 04:54:55 PM PDT 24
Finished Jul 04 04:56:26 PM PDT 24
Peak memory 386296 kb
Host smart-a09abe0e-4d3b-482c-9f5b-8fbe52e7744d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018780762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3018780762
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.1833601042
Short name T1334
Test name
Test status
Simulation time 279538028 ps
CPU time 2.52 seconds
Started Jul 04 04:54:56 PM PDT 24
Finished Jul 04 04:54:59 PM PDT 24
Peak memory 205224 kb
Host smart-7d8ddd5e-f86e-4c62-8d05-88eca922fb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833601042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.1833601042
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.1907438103
Short name T968
Test name
Test status
Simulation time 1782621216 ps
CPU time 35.49 seconds
Started Jul 04 04:54:57 PM PDT 24
Finished Jul 04 04:55:33 PM PDT 24
Peak memory 405140 kb
Host smart-0ac3535d-9b9c-4d0b-875a-0980b50f5a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907438103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1907438103
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.1350494193
Short name T1023
Test name
Test status
Simulation time 20398622028 ps
CPU time 1129.27 seconds
Started Jul 04 04:55:03 PM PDT 24
Finished Jul 04 05:13:53 PM PDT 24
Peak memory 3713532 kb
Host smart-8d8d540f-f9a0-4588-9fc3-ef4a7531a8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350494193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1350494193
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.1070899442
Short name T862
Test name
Test status
Simulation time 476922157 ps
CPU time 8.98 seconds
Started Jul 04 04:54:56 PM PDT 24
Finished Jul 04 04:55:05 PM PDT 24
Peak memory 220896 kb
Host smart-f981ef53-7769-4813-9828-8559471def72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070899442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.1070899442
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.3771430390
Short name T1488
Test name
Test status
Simulation time 1489384499 ps
CPU time 2.37 seconds
Started Jul 04 04:55:02 PM PDT 24
Finished Jul 04 04:55:05 PM PDT 24
Peak memory 204728 kb
Host smart-c2d8f698-e2fd-4e14-b610-7e3feca6b255
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771430390 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.3771430390
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.1981562342
Short name T1351
Test name
Test status
Simulation time 179330307 ps
CPU time 1.23 seconds
Started Jul 04 04:55:01 PM PDT 24
Finished Jul 04 04:55:02 PM PDT 24
Peak memory 205616 kb
Host smart-9b4985dd-461d-4845-8b69-a73de57f0b5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981562342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.1981562342
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3399119595
Short name T421
Test name
Test status
Simulation time 456453088 ps
CPU time 1.05 seconds
Started Jul 04 04:55:02 PM PDT 24
Finished Jul 04 04:55:03 PM PDT 24
Peak memory 212800 kb
Host smart-5f9bdd73-ac0d-419f-95a8-77f9ab8b325b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399119595 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3399119595
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.734647606
Short name T710
Test name
Test status
Simulation time 447180086 ps
CPU time 2.51 seconds
Started Jul 04 04:55:03 PM PDT 24
Finished Jul 04 04:55:06 PM PDT 24
Peak memory 204660 kb
Host smart-dcc40012-fca8-41a2-8e35-68ede0c0fd48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734647606 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.734647606
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.993745801
Short name T475
Test name
Test status
Simulation time 313840533 ps
CPU time 0.99 seconds
Started Jul 04 04:55:02 PM PDT 24
Finished Jul 04 04:55:04 PM PDT 24
Peak memory 204496 kb
Host smart-046e1cb4-f85f-43fc-9ec1-08373c6f9e1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993745801 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.993745801
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.387858610
Short name T1348
Test name
Test status
Simulation time 15235980865 ps
CPU time 6.36 seconds
Started Jul 04 04:55:03 PM PDT 24
Finished Jul 04 04:55:09 PM PDT 24
Peak memory 213536 kb
Host smart-63b61ecb-a9e6-4c1d-877c-321f0fa37d66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387858610 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.387858610
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.1056419849
Short name T1201
Test name
Test status
Simulation time 1328324342 ps
CPU time 17.77 seconds
Started Jul 04 04:55:04 PM PDT 24
Finished Jul 04 04:55:22 PM PDT 24
Peak memory 204700 kb
Host smart-b718b106-4b70-4f7f-9e22-df45e957b661
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056419849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.1056419849
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.1550397626
Short name T295
Test name
Test status
Simulation time 593078776 ps
CPU time 12.03 seconds
Started Jul 04 04:55:03 PM PDT 24
Finished Jul 04 04:55:15 PM PDT 24
Peak memory 204676 kb
Host smart-189aa7b9-5026-4ab5-acce-a1f54e76f7f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550397626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.1550397626
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.339387934
Short name T1211
Test name
Test status
Simulation time 33141476684 ps
CPU time 41.86 seconds
Started Jul 04 04:55:05 PM PDT 24
Finished Jul 04 04:55:47 PM PDT 24
Peak memory 845080 kb
Host smart-ce6985cd-2ecd-4c4f-882f-7a3648c7d3f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339387934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c
_target_stress_wr.339387934
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.1089051653
Short name T1457
Test name
Test status
Simulation time 27434442861 ps
CPU time 92.18 seconds
Started Jul 04 04:55:03 PM PDT 24
Finished Jul 04 04:56:36 PM PDT 24
Peak memory 889932 kb
Host smart-0ed52c93-ab84-4f0c-b58f-0e354dc50d3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089051653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.1089051653
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3873414925
Short name T78
Test name
Test status
Simulation time 2447773223 ps
CPU time 7.04 seconds
Started Jul 04 04:55:02 PM PDT 24
Finished Jul 04 04:55:09 PM PDT 24
Peak memory 218616 kb
Host smart-90411e3a-7fef-4aa6-ae11-95e106dab3cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873414925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3873414925
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.1782047620
Short name T1451
Test name
Test status
Simulation time 38144660 ps
CPU time 0.63 seconds
Started Jul 04 04:55:13 PM PDT 24
Finished Jul 04 04:55:15 PM PDT 24
Peak memory 204300 kb
Host smart-839ecfb4-03cb-4cf7-a830-62cbf382cbc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782047620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1782047620
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2250829857
Short name T364
Test name
Test status
Simulation time 447732318 ps
CPU time 1.7 seconds
Started Jul 04 04:55:07 PM PDT 24
Finished Jul 04 04:55:09 PM PDT 24
Peak memory 212940 kb
Host smart-c08f335f-5223-4d31-913b-f9eef988e455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250829857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2250829857
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.1782768176
Short name T398
Test name
Test status
Simulation time 1596188801 ps
CPU time 13.46 seconds
Started Jul 04 04:55:01 PM PDT 24
Finished Jul 04 04:55:15 PM PDT 24
Peak memory 260288 kb
Host smart-a673b3a4-ea28-42bc-8f51-d01457cce653
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782768176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.1782768176
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2105984233
Short name T1107
Test name
Test status
Simulation time 10641804536 ps
CPU time 65.92 seconds
Started Jul 04 04:55:01 PM PDT 24
Finished Jul 04 04:56:07 PM PDT 24
Peak memory 640608 kb
Host smart-54531826-dd1b-41eb-b22d-d7174975a867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105984233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2105984233
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2621804199
Short name T1377
Test name
Test status
Simulation time 6721526045 ps
CPU time 50.95 seconds
Started Jul 04 04:55:04 PM PDT 24
Finished Jul 04 04:55:55 PM PDT 24
Peak memory 574364 kb
Host smart-0bbeec4b-d63f-4429-b2eb-f6974c9fd620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621804199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2621804199
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.2884371142
Short name T1015
Test name
Test status
Simulation time 848899046 ps
CPU time 1.1 seconds
Started Jul 04 04:55:04 PM PDT 24
Finished Jul 04 04:55:05 PM PDT 24
Peak memory 204344 kb
Host smart-4b116ef0-67d4-4313-90b2-40e68f4b2de5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884371142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.2884371142
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.802713545
Short name T1504
Test name
Test status
Simulation time 843262033 ps
CPU time 4.27 seconds
Started Jul 04 04:55:03 PM PDT 24
Finished Jul 04 04:55:08 PM PDT 24
Peak memory 204684 kb
Host smart-92f41412-4910-426c-a816-924f3b9570b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802713545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.
802713545
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1212975653
Short name T1164
Test name
Test status
Simulation time 11287967419 ps
CPU time 183.85 seconds
Started Jul 04 04:55:05 PM PDT 24
Finished Jul 04 04:58:09 PM PDT 24
Peak memory 1585452 kb
Host smart-9e7fa3ed-bc6c-4da0-b619-cded1653fba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212975653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1212975653
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1361768943
Short name T411
Test name
Test status
Simulation time 429455676 ps
CPU time 3.49 seconds
Started Jul 04 04:55:09 PM PDT 24
Finished Jul 04 04:55:12 PM PDT 24
Peak memory 204712 kb
Host smart-030c1509-8374-4bc1-bb92-62b79d078a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361768943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1361768943
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.143177834
Short name T1274
Test name
Test status
Simulation time 1956030554 ps
CPU time 85.52 seconds
Started Jul 04 04:55:21 PM PDT 24
Finished Jul 04 04:56:47 PM PDT 24
Peak memory 366128 kb
Host smart-8cbc01c8-1775-4dca-9514-30404fbaaff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143177834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.143177834
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.3395528417
Short name T1250
Test name
Test status
Simulation time 33085109 ps
CPU time 0.63 seconds
Started Jul 04 04:55:01 PM PDT 24
Finished Jul 04 04:55:02 PM PDT 24
Peak memory 204360 kb
Host smart-e06471fd-a0f4-4ad5-8c1e-a3646aacf70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395528417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3395528417
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2848213513
Short name T1064
Test name
Test status
Simulation time 25407081731 ps
CPU time 1090.6 seconds
Started Jul 04 04:55:06 PM PDT 24
Finished Jul 04 05:13:17 PM PDT 24
Peak memory 2044240 kb
Host smart-e676aeff-1be5-439d-9774-358b41be3db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848213513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2848213513
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.409759938
Short name T454
Test name
Test status
Simulation time 111369051 ps
CPU time 1.2 seconds
Started Jul 04 04:55:04 PM PDT 24
Finished Jul 04 04:55:05 PM PDT 24
Peak memory 223424 kb
Host smart-6e97fa21-878f-4e6b-a44f-0dfeb7bcace8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409759938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.409759938
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.1342066377
Short name T1235
Test name
Test status
Simulation time 10416656860 ps
CPU time 26.13 seconds
Started Jul 04 04:55:02 PM PDT 24
Finished Jul 04 04:55:28 PM PDT 24
Peak memory 310072 kb
Host smart-6b91f9fd-9904-4fc6-bb62-74a26a202b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342066377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.1342066377
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.2439871666
Short name T972
Test name
Test status
Simulation time 18717707447 ps
CPU time 1362.28 seconds
Started Jul 04 04:55:10 PM PDT 24
Finished Jul 04 05:17:52 PM PDT 24
Peak memory 4753908 kb
Host smart-a9d954f0-6c8e-4086-a782-9be46d385630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439871666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.2439871666
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.706101237
Short name T265
Test name
Test status
Simulation time 758159292 ps
CPU time 31.73 seconds
Started Jul 04 04:55:03 PM PDT 24
Finished Jul 04 04:55:35 PM PDT 24
Peak memory 212808 kb
Host smart-c949b7e1-8699-4f00-9adc-de66d630a871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706101237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.706101237
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.3904367697
Short name T1138
Test name
Test status
Simulation time 552691357 ps
CPU time 3.03 seconds
Started Jul 04 04:55:14 PM PDT 24
Finished Jul 04 04:55:17 PM PDT 24
Peak memory 204780 kb
Host smart-c35f183e-a811-4eae-abc9-6ec6a23d733c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904367697 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3904367697
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3261647091
Short name T440
Test name
Test status
Simulation time 713906391 ps
CPU time 1.39 seconds
Started Jul 04 04:55:12 PM PDT 24
Finished Jul 04 04:55:14 PM PDT 24
Peak memory 204712 kb
Host smart-aa446765-8f71-4b12-ae09-fc9ff408cc88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261647091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.3261647091
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.1468497193
Short name T458
Test name
Test status
Simulation time 431284528 ps
CPU time 1.06 seconds
Started Jul 04 04:55:10 PM PDT 24
Finished Jul 04 04:55:12 PM PDT 24
Peak memory 204472 kb
Host smart-4462abc0-35c4-4e28-99a0-b4295c52814e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468497193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.1468497193
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.3358331578
Short name T913
Test name
Test status
Simulation time 2727051554 ps
CPU time 2.04 seconds
Started Jul 04 04:55:10 PM PDT 24
Finished Jul 04 04:55:12 PM PDT 24
Peak memory 204776 kb
Host smart-40b936c7-22d5-4700-95c5-d91abecd657d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358331578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.3358331578
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.3980697703
Short name T620
Test name
Test status
Simulation time 190202902 ps
CPU time 1.37 seconds
Started Jul 04 04:55:10 PM PDT 24
Finished Jul 04 04:55:12 PM PDT 24
Peak memory 204512 kb
Host smart-ccacc0cb-1b81-4ec6-8f51-c2ca7cee58cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980697703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.3980697703
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2755173632
Short name T966
Test name
Test status
Simulation time 4867766193 ps
CPU time 5.96 seconds
Started Jul 04 04:55:10 PM PDT 24
Finished Jul 04 04:55:16 PM PDT 24
Peak memory 213024 kb
Host smart-90a4b794-7bc7-4218-85ba-870ddd8557eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755173632 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2755173632
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.1039052721
Short name T647
Test name
Test status
Simulation time 28192060413 ps
CPU time 64.97 seconds
Started Jul 04 04:55:09 PM PDT 24
Finished Jul 04 04:56:14 PM PDT 24
Peak memory 1339240 kb
Host smart-fd87d8e8-188d-4065-b6c5-64b005b1f182
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039052721 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.1039052721
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.3944027718
Short name T940
Test name
Test status
Simulation time 3120954868 ps
CPU time 9.52 seconds
Started Jul 04 04:55:10 PM PDT 24
Finished Jul 04 04:55:19 PM PDT 24
Peak memory 204756 kb
Host smart-0b06c752-ca34-4825-b6ab-eb9e3f465324
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944027718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.3944027718
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.701825328
Short name T952
Test name
Test status
Simulation time 1382714223 ps
CPU time 27.6 seconds
Started Jul 04 04:55:10 PM PDT 24
Finished Jul 04 04:55:38 PM PDT 24
Peak memory 226068 kb
Host smart-05d65529-8f04-4c6a-8fd5-40d8beedc336
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701825328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.701825328
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.1913461260
Short name T1098
Test name
Test status
Simulation time 40449463864 ps
CPU time 91.09 seconds
Started Jul 04 04:55:11 PM PDT 24
Finished Jul 04 04:56:43 PM PDT 24
Peak memory 1515812 kb
Host smart-1fde3d0b-875c-4c44-a48f-4bc6f4272089
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913461260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.1913461260
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1189443599
Short name T1395
Test name
Test status
Simulation time 31090639703 ps
CPU time 1608.45 seconds
Started Jul 04 04:55:08 PM PDT 24
Finished Jul 04 05:21:57 PM PDT 24
Peak memory 7368272 kb
Host smart-a89ea482-641f-4739-ad5d-55e09f699b2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189443599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1189443599
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.3050485603
Short name T831
Test name
Test status
Simulation time 1364493481 ps
CPU time 7.07 seconds
Started Jul 04 04:55:10 PM PDT 24
Finished Jul 04 04:55:17 PM PDT 24
Peak memory 212944 kb
Host smart-7e7792b1-ae6b-4316-9cc9-4cb0e51b3c4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050485603 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.3050485603
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.2494479079
Short name T1282
Test name
Test status
Simulation time 116356027 ps
CPU time 1.65 seconds
Started Jul 04 04:55:11 PM PDT 24
Finished Jul 04 04:55:13 PM PDT 24
Peak memory 204732 kb
Host smart-33e3a55a-3b00-4ef3-8857-66155841cd81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494479079 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.2494479079
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.177883801
Short name T1234
Test name
Test status
Simulation time 16196227 ps
CPU time 0.63 seconds
Started Jul 04 04:55:21 PM PDT 24
Finished Jul 04 04:55:22 PM PDT 24
Peak memory 204300 kb
Host smart-da8f9415-bf9f-423f-a97d-dfa0a8e303c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177883801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.177883801
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3761852382
Short name T645
Test name
Test status
Simulation time 583778408 ps
CPU time 2.24 seconds
Started Jul 04 04:55:12 PM PDT 24
Finished Jul 04 04:55:14 PM PDT 24
Peak memory 212988 kb
Host smart-8baac96c-9b73-4d02-94b6-33a05938696e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761852382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3761852382
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.3971322546
Short name T1231
Test name
Test status
Simulation time 984576165 ps
CPU time 5.98 seconds
Started Jul 04 04:55:12 PM PDT 24
Finished Jul 04 04:55:18 PM PDT 24
Peak memory 258096 kb
Host smart-bb9f8f78-4127-4cac-9a14-4051f68a6e76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971322546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.3971322546
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.2574211279
Short name T524
Test name
Test status
Simulation time 3530044751 ps
CPU time 48.24 seconds
Started Jul 04 04:55:13 PM PDT 24
Finished Jul 04 04:56:02 PM PDT 24
Peak memory 626752 kb
Host smart-590e37da-e670-46eb-bd7b-97d65bfd2ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574211279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2574211279
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.1848542655
Short name T679
Test name
Test status
Simulation time 11430621332 ps
CPU time 155.74 seconds
Started Jul 04 04:55:09 PM PDT 24
Finished Jul 04 04:57:45 PM PDT 24
Peak memory 717752 kb
Host smart-e138be3b-2718-459d-b7f0-bf57692259c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848542655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1848542655
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.736917453
Short name T1259
Test name
Test status
Simulation time 316350893 ps
CPU time 0.91 seconds
Started Jul 04 04:55:13 PM PDT 24
Finished Jul 04 04:55:15 PM PDT 24
Peak memory 204400 kb
Host smart-9cb4866a-c6d6-4cca-9dc9-1118c56beff0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736917453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fm
t.736917453
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.4057145351
Short name T424
Test name
Test status
Simulation time 283524512 ps
CPU time 9.38 seconds
Started Jul 04 04:55:12 PM PDT 24
Finished Jul 04 04:55:21 PM PDT 24
Peak memory 231724 kb
Host smart-771fd54e-66b3-405d-8408-04cdc8e288cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057145351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.4057145351
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.1149023294
Short name T310
Test name
Test status
Simulation time 5421922378 ps
CPU time 143.62 seconds
Started Jul 04 04:55:14 PM PDT 24
Finished Jul 04 04:57:38 PM PDT 24
Peak memory 1357040 kb
Host smart-fd91156f-55b7-417f-9408-dc58d7077419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149023294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1149023294
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.3722411086
Short name T68
Test name
Test status
Simulation time 3553882429 ps
CPU time 5.55 seconds
Started Jul 04 04:55:21 PM PDT 24
Finished Jul 04 04:55:27 PM PDT 24
Peak memory 204804 kb
Host smart-9ab2274b-c67d-46fc-a8a4-31d9a8bc234b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722411086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.3722411086
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.713657262
Short name T1404
Test name
Test status
Simulation time 1916677876 ps
CPU time 31.86 seconds
Started Jul 04 04:55:19 PM PDT 24
Finished Jul 04 04:55:51 PM PDT 24
Peak memory 354696 kb
Host smart-ec619d14-8a90-46a8-b20c-56d1e5878586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713657262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.713657262
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.3528358355
Short name T1160
Test name
Test status
Simulation time 87001139 ps
CPU time 0.69 seconds
Started Jul 04 04:55:10 PM PDT 24
Finished Jul 04 04:55:11 PM PDT 24
Peak memory 204332 kb
Host smart-b7a94763-3519-41cc-9cf2-f0433664c1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528358355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.3528358355
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.374448952
Short name T1412
Test name
Test status
Simulation time 11017271247 ps
CPU time 22 seconds
Started Jul 04 04:55:11 PM PDT 24
Finished Jul 04 04:55:34 PM PDT 24
Peak memory 222224 kb
Host smart-fcede948-53f5-4a3e-ab95-90d9e48de82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374448952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.374448952
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.1475599627
Short name T917
Test name
Test status
Simulation time 332922500 ps
CPU time 2.19 seconds
Started Jul 04 04:55:09 PM PDT 24
Finished Jul 04 04:55:11 PM PDT 24
Peak memory 204620 kb
Host smart-37d50919-31af-4226-a381-0de660ab0e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475599627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.1475599627
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.2098683592
Short name T389
Test name
Test status
Simulation time 3764722883 ps
CPU time 16.08 seconds
Started Jul 04 04:55:14 PM PDT 24
Finished Jul 04 04:55:31 PM PDT 24
Peak memory 305232 kb
Host smart-f1410b2c-094a-4a55-b29e-75c5b57eacf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098683592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2098683592
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.2797521750
Short name T279
Test name
Test status
Simulation time 12131327084 ps
CPU time 1001.32 seconds
Started Jul 04 04:55:13 PM PDT 24
Finished Jul 04 05:11:55 PM PDT 24
Peak memory 1724488 kb
Host smart-2185620d-eef4-4c7c-afd4-bc5ba4dae703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797521750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2797521750
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.381520755
Short name T716
Test name
Test status
Simulation time 774317301 ps
CPU time 12.57 seconds
Started Jul 04 04:55:14 PM PDT 24
Finished Jul 04 04:55:27 PM PDT 24
Peak memory 219600 kb
Host smart-2b32a90b-a18d-4f1f-b338-bee827de66fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381520755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.381520755
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.2736621384
Short name T1325
Test name
Test status
Simulation time 790630264 ps
CPU time 4.52 seconds
Started Jul 04 04:55:26 PM PDT 24
Finished Jul 04 04:55:30 PM PDT 24
Peak memory 212916 kb
Host smart-85301d8b-4a56-490a-a945-0ab2ae2ec359
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736621384 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.2736621384
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.3321277628
Short name T1156
Test name
Test status
Simulation time 1206169236 ps
CPU time 1.25 seconds
Started Jul 04 04:55:15 PM PDT 24
Finished Jul 04 04:55:17 PM PDT 24
Peak memory 204656 kb
Host smart-b890346a-4061-4756-aa01-3a2e4956163d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321277628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.3321277628
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1104195171
Short name T1453
Test name
Test status
Simulation time 1409137920 ps
CPU time 1.3 seconds
Started Jul 04 04:55:24 PM PDT 24
Finished Jul 04 04:55:26 PM PDT 24
Peak memory 204680 kb
Host smart-6d1bba0c-9f8b-4793-ba49-b47e3eac2532
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104195171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1104195171
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.3117320901
Short name T1198
Test name
Test status
Simulation time 1350794539 ps
CPU time 2.13 seconds
Started Jul 04 04:55:21 PM PDT 24
Finished Jul 04 04:55:24 PM PDT 24
Peak memory 204696 kb
Host smart-385d4b18-d025-4272-a82e-6c948578a01f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117320901 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.3117320901
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.2903537489
Short name T1261
Test name
Test status
Simulation time 1032031402 ps
CPU time 1.38 seconds
Started Jul 04 04:55:16 PM PDT 24
Finished Jul 04 04:55:17 PM PDT 24
Peak memory 204476 kb
Host smart-41056836-c79f-4f8f-aaac-0ee32ed65b00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903537489 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.2903537489
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.2444966400
Short name T1162
Test name
Test status
Simulation time 4212030985 ps
CPU time 5.66 seconds
Started Jul 04 04:55:15 PM PDT 24
Finished Jul 04 04:55:21 PM PDT 24
Peak memory 218808 kb
Host smart-dbadda24-3745-407e-9e11-f81c6f6d03e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444966400 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.2444966400
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.109820323
Short name T532
Test name
Test status
Simulation time 8323722579 ps
CPU time 10.97 seconds
Started Jul 04 04:55:16 PM PDT 24
Finished Jul 04 04:55:27 PM PDT 24
Peak memory 234256 kb
Host smart-d3305a0e-1e1a-477b-845d-bbf61bb5d27a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109820323 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.109820323
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.4021590908
Short name T1435
Test name
Test status
Simulation time 775988508 ps
CPU time 13.45 seconds
Started Jul 04 04:55:18 PM PDT 24
Finished Jul 04 04:55:31 PM PDT 24
Peak memory 204700 kb
Host smart-d46a96fb-628b-431f-9897-c1264b518b79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021590908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.4021590908
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1625401525
Short name T435
Test name
Test status
Simulation time 5028764783 ps
CPU time 21.05 seconds
Started Jul 04 04:55:17 PM PDT 24
Finished Jul 04 04:55:38 PM PDT 24
Peak memory 216484 kb
Host smart-5b0406c5-f953-405f-808c-5c36c4f4aa67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625401525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1625401525
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.4082302465
Short name T1223
Test name
Test status
Simulation time 42675756271 ps
CPU time 675.75 seconds
Started Jul 04 04:55:23 PM PDT 24
Finished Jul 04 05:06:39 PM PDT 24
Peak memory 5458140 kb
Host smart-4a17cfdb-aae0-43df-a701-9f662fc6bb30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082302465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.4082302465
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.1496456036
Short name T721
Test name
Test status
Simulation time 44398168283 ps
CPU time 2169.01 seconds
Started Jul 04 04:55:18 PM PDT 24
Finished Jul 04 05:31:27 PM PDT 24
Peak memory 4339460 kb
Host smart-6f5af024-3e6b-4b93-a533-bcb943d005f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496456036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.1496456036
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.4106152184
Short name T302
Test name
Test status
Simulation time 3034132689 ps
CPU time 7.7 seconds
Started Jul 04 04:55:14 PM PDT 24
Finished Jul 04 04:55:22 PM PDT 24
Peak memory 218256 kb
Host smart-a0c5ffec-fd11-4f1b-ac2a-75832f1526d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106152184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.4106152184
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.4032299342
Short name T1109
Test name
Test status
Simulation time 171234877 ps
CPU time 3.31 seconds
Started Jul 04 04:55:15 PM PDT 24
Finished Jul 04 04:55:19 PM PDT 24
Peak memory 205096 kb
Host smart-b4ffc2ea-9596-4700-88c5-58bb76470b04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032299342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.4032299342
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.2106895443
Short name T449
Test name
Test status
Simulation time 18016098 ps
CPU time 0.65 seconds
Started Jul 04 04:55:33 PM PDT 24
Finished Jul 04 04:55:34 PM PDT 24
Peak memory 204356 kb
Host smart-0644e68a-98a3-4bd2-b775-725fda94582d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106895443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2106895443
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.2374396260
Short name T912
Test name
Test status
Simulation time 1293784533 ps
CPU time 3.49 seconds
Started Jul 04 04:55:24 PM PDT 24
Finished Jul 04 04:55:27 PM PDT 24
Peak memory 212940 kb
Host smart-d4966c31-b784-4830-926a-084d8c780067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374396260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.2374396260
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2287442026
Short name T1397
Test name
Test status
Simulation time 459925985 ps
CPU time 9.4 seconds
Started Jul 04 04:55:23 PM PDT 24
Finished Jul 04 04:55:32 PM PDT 24
Peak memory 304720 kb
Host smart-7bccb329-c0a5-4030-9970-79a2ebca2034
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287442026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2287442026
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.1467004121
Short name T564
Test name
Test status
Simulation time 2869709624 ps
CPU time 136.49 seconds
Started Jul 04 04:55:24 PM PDT 24
Finished Jul 04 04:57:41 PM PDT 24
Peak memory 649164 kb
Host smart-1b7012bf-0e75-49df-98d4-27e93cfb4498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467004121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1467004121
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.981693958
Short name T849
Test name
Test status
Simulation time 2075707055 ps
CPU time 122.56 seconds
Started Jul 04 04:55:27 PM PDT 24
Finished Jul 04 04:57:30 PM PDT 24
Peak memory 614048 kb
Host smart-4478b7a7-6a2f-423e-9096-fc24696fa173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981693958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.981693958
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2921938060
Short name T1391
Test name
Test status
Simulation time 637044253 ps
CPU time 0.97 seconds
Started Jul 04 04:55:24 PM PDT 24
Finished Jul 04 04:55:25 PM PDT 24
Peak memory 204364 kb
Host smart-a4dddd61-4d41-4e27-a629-f2c5baac17aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921938060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2921938060
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.121550606
Short name T489
Test name
Test status
Simulation time 436040651 ps
CPU time 3.15 seconds
Started Jul 04 04:55:26 PM PDT 24
Finished Jul 04 04:55:29 PM PDT 24
Peak memory 204748 kb
Host smart-cdc2bf3b-ff4c-4cfc-a421-bea843a1a66f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121550606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.
121550606
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.342050588
Short name T363
Test name
Test status
Simulation time 14131407446 ps
CPU time 104.81 seconds
Started Jul 04 04:55:16 PM PDT 24
Finished Jul 04 04:57:01 PM PDT 24
Peak memory 1123436 kb
Host smart-ef0a3454-9879-4132-b462-de234d3bc076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342050588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.342050588
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.3371346486
Short name T275
Test name
Test status
Simulation time 2163111920 ps
CPU time 23.84 seconds
Started Jul 04 04:55:33 PM PDT 24
Finished Jul 04 04:55:57 PM PDT 24
Peak memory 204804 kb
Host smart-39d81f39-e6f8-4d0e-8cb9-815e58bfe34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371346486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.3371346486
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.3070967510
Short name T1286
Test name
Test status
Simulation time 1229056200 ps
CPU time 52.19 seconds
Started Jul 04 04:55:31 PM PDT 24
Finished Jul 04 04:56:23 PM PDT 24
Peak memory 298692 kb
Host smart-e4b35890-856e-4d1e-8624-f17ba2ee31a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070967510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.3070967510
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.1894890962
Short name T595
Test name
Test status
Simulation time 66948895 ps
CPU time 0.65 seconds
Started Jul 04 04:55:14 PM PDT 24
Finished Jul 04 04:55:15 PM PDT 24
Peak memory 204472 kb
Host smart-89dd2b03-0172-4462-971b-fb8332f8b9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894890962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.1894890962
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.150857372
Short name T1329
Test name
Test status
Simulation time 12716086522 ps
CPU time 227.07 seconds
Started Jul 04 04:55:25 PM PDT 24
Finished Jul 04 04:59:12 PM PDT 24
Peak memory 969440 kb
Host smart-2e7a9ad8-352b-4d6a-a9da-9c20f9f49882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150857372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.150857372
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.430665991
Short name T434
Test name
Test status
Simulation time 232475758 ps
CPU time 1.88 seconds
Started Jul 04 04:55:21 PM PDT 24
Finished Jul 04 04:55:23 PM PDT 24
Peak memory 212736 kb
Host smart-4a9897bf-81ca-400b-99da-9217567dfd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430665991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.430665991
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1621074320
Short name T993
Test name
Test status
Simulation time 1828635126 ps
CPU time 87.01 seconds
Started Jul 04 04:55:22 PM PDT 24
Finished Jul 04 04:56:50 PM PDT 24
Peak memory 358408 kb
Host smart-3b719b33-82fa-43f9-89ad-e6310badbffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621074320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1621074320
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.2761612524
Short name T555
Test name
Test status
Simulation time 709234640 ps
CPU time 10.73 seconds
Started Jul 04 04:55:22 PM PDT 24
Finished Jul 04 04:55:33 PM PDT 24
Peak memory 213332 kb
Host smart-8c235a9e-2ac0-4bcb-a67e-3e3ce432f80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761612524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.2761612524
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.1586651279
Short name T588
Test name
Test status
Simulation time 1670181824 ps
CPU time 4.15 seconds
Started Jul 04 04:55:30 PM PDT 24
Finished Jul 04 04:55:34 PM PDT 24
Peak memory 212876 kb
Host smart-76e4ac05-9116-4629-9647-44437f277133
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586651279 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.1586651279
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3655711067
Short name T356
Test name
Test status
Simulation time 1143958895 ps
CPU time 1.32 seconds
Started Jul 04 04:55:27 PM PDT 24
Finished Jul 04 04:55:28 PM PDT 24
Peak memory 204600 kb
Host smart-56cdf540-2c28-4aa6-94fe-44e245218676
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655711067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3655711067
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.2689599741
Short name T730
Test name
Test status
Simulation time 438940052 ps
CPU time 0.74 seconds
Started Jul 04 04:55:26 PM PDT 24
Finished Jul 04 04:55:26 PM PDT 24
Peak memory 204516 kb
Host smart-a535d79f-c68b-4aaf-b72f-7dc7b8da5219
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689599741 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.2689599741
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.378479134
Short name T724
Test name
Test status
Simulation time 217837930 ps
CPU time 1.13 seconds
Started Jul 04 04:55:31 PM PDT 24
Finished Jul 04 04:55:32 PM PDT 24
Peak memory 204512 kb
Host smart-4d199a89-0c2e-4532-ae2c-9df34b89f0d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378479134 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.378479134
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.3368426078
Short name T1112
Test name
Test status
Simulation time 1966602568 ps
CPU time 2.22 seconds
Started Jul 04 04:55:36 PM PDT 24
Finished Jul 04 04:55:39 PM PDT 24
Peak memory 204728 kb
Host smart-e15b3bd4-3a34-4a5f-bd8f-0fee7bc17475
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368426078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.3368426078
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.2165827472
Short name T24
Test name
Test status
Simulation time 3343185243 ps
CPU time 4.91 seconds
Started Jul 04 04:55:23 PM PDT 24
Finished Jul 04 04:55:28 PM PDT 24
Peak memory 212976 kb
Host smart-ab2cef4e-cef9-4ce8-bebe-a6fd1cdbd03c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165827472 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.2165827472
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.3101783794
Short name T817
Test name
Test status
Simulation time 3034859103 ps
CPU time 2.36 seconds
Started Jul 04 04:55:24 PM PDT 24
Finished Jul 04 04:55:27 PM PDT 24
Peak memory 204716 kb
Host smart-dca7482a-cd51-4e0a-9c91-06f39fa10a5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101783794 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.3101783794
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.1925157791
Short name T485
Test name
Test status
Simulation time 11877576906 ps
CPU time 31.89 seconds
Started Jul 04 04:55:21 PM PDT 24
Finished Jul 04 04:55:53 PM PDT 24
Peak memory 204872 kb
Host smart-b3487a07-ac7d-4889-87bc-20483e07d948
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925157791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.1925157791
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1255314943
Short name T585
Test name
Test status
Simulation time 38253341316 ps
CPU time 67.47 seconds
Started Jul 04 04:55:25 PM PDT 24
Finished Jul 04 04:56:32 PM PDT 24
Peak memory 1116432 kb
Host smart-8222ddde-c70f-4e90-96c1-ba6cfe94077b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255314943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1255314943
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3177585544
Short name T1190
Test name
Test status
Simulation time 27195350873 ps
CPU time 288.76 seconds
Started Jul 04 04:55:25 PM PDT 24
Finished Jul 04 05:00:14 PM PDT 24
Peak memory 1154224 kb
Host smart-4df667c1-ed40-4e76-82a5-4a988266432e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177585544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3177585544
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.1527400642
Short name T991
Test name
Test status
Simulation time 1285845314 ps
CPU time 7.24 seconds
Started Jul 04 04:55:22 PM PDT 24
Finished Jul 04 04:55:30 PM PDT 24
Peak memory 220980 kb
Host smart-378c33aa-fa31-4482-a1d0-1f14f9b33f0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527400642 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.1527400642
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.223085596
Short name T18
Test name
Test status
Simulation time 118853096 ps
CPU time 2.57 seconds
Started Jul 04 04:55:30 PM PDT 24
Finished Jul 04 04:55:33 PM PDT 24
Peak memory 204712 kb
Host smart-fef8cd6f-3cea-41cf-ac15-135672b3b8de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223085596 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.223085596
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.4061086675
Short name T333
Test name
Test status
Simulation time 31931002 ps
CPU time 0.63 seconds
Started Jul 04 04:55:36 PM PDT 24
Finished Jul 04 04:55:37 PM PDT 24
Peak memory 204348 kb
Host smart-6dacb20c-128e-4b1c-8106-d0d7ea9f3327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061086675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.4061086675
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2512604658
Short name T1017
Test name
Test status
Simulation time 464225765 ps
CPU time 4 seconds
Started Jul 04 04:55:31 PM PDT 24
Finished Jul 04 04:55:36 PM PDT 24
Peak memory 220896 kb
Host smart-978f3df8-90bf-40b8-a10c-4fd4e25da0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512604658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2512604658
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.202386063
Short name T898
Test name
Test status
Simulation time 494870309 ps
CPU time 13.02 seconds
Started Jul 04 04:55:35 PM PDT 24
Finished Jul 04 04:55:48 PM PDT 24
Peak memory 253784 kb
Host smart-48d02c9d-38bf-4115-8882-ea1422d82298
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202386063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empt
y.202386063
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.1892479989
Short name T788
Test name
Test status
Simulation time 1771647288 ps
CPU time 63.47 seconds
Started Jul 04 04:55:30 PM PDT 24
Finished Jul 04 04:56:34 PM PDT 24
Peak memory 646668 kb
Host smart-ff78fdf9-90d6-4313-9461-724526da5971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892479989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1892479989
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.373110279
Short name T821
Test name
Test status
Simulation time 9802313931 ps
CPU time 173.32 seconds
Started Jul 04 04:55:34 PM PDT 24
Finished Jul 04 04:58:27 PM PDT 24
Peak memory 761900 kb
Host smart-84bda734-bb4d-4bbe-b631-2c3a7d4277d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373110279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.373110279
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.3921978273
Short name T1459
Test name
Test status
Simulation time 1339352889 ps
CPU time 1.02 seconds
Started Jul 04 04:55:31 PM PDT 24
Finished Jul 04 04:55:32 PM PDT 24
Peak memory 204356 kb
Host smart-0a9d5fd1-2dfd-4352-91cb-e42a8c6e8b77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921978273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.3921978273
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3838410857
Short name T408
Test name
Test status
Simulation time 168691287 ps
CPU time 3.6 seconds
Started Jul 04 04:55:33 PM PDT 24
Finished Jul 04 04:55:37 PM PDT 24
Peak memory 204708 kb
Host smart-5bbfeebe-3b31-4f74-89fb-d59421a61d8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838410857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3838410857
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3879397482
Short name T1200
Test name
Test status
Simulation time 3661039856 ps
CPU time 91.06 seconds
Started Jul 04 04:55:32 PM PDT 24
Finished Jul 04 04:57:03 PM PDT 24
Peak memory 1109672 kb
Host smart-41d5ceee-504c-414a-ad01-e587fda838a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879397482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3879397482
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.1241221816
Short name T1165
Test name
Test status
Simulation time 208006257 ps
CPU time 3.54 seconds
Started Jul 04 04:55:40 PM PDT 24
Finished Jul 04 04:55:44 PM PDT 24
Peak memory 204732 kb
Host smart-2b2c0495-e21e-4cfe-bd7e-77df6170a7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241221816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.1241221816
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.1158202735
Short name T624
Test name
Test status
Simulation time 2718591128 ps
CPU time 18.34 seconds
Started Jul 04 04:55:38 PM PDT 24
Finished Jul 04 04:55:57 PM PDT 24
Peak memory 333744 kb
Host smart-ab980fd5-86b2-459a-a737-7e149ea6c994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158202735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.1158202735
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.1432328014
Short name T694
Test name
Test status
Simulation time 95980519 ps
CPU time 0.64 seconds
Started Jul 04 04:55:35 PM PDT 24
Finished Jul 04 04:55:35 PM PDT 24
Peak memory 204400 kb
Host smart-bd5ac292-7c18-429d-b9f5-12aa90c62c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432328014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1432328014
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.894889918
Short name T1008
Test name
Test status
Simulation time 25812238908 ps
CPU time 82.3 seconds
Started Jul 04 04:55:30 PM PDT 24
Finished Jul 04 04:56:52 PM PDT 24
Peak memory 204840 kb
Host smart-8f247154-d090-49a4-bcda-c2182e9fdb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894889918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.894889918
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.3168495216
Short name T1441
Test name
Test status
Simulation time 246675493 ps
CPU time 1.73 seconds
Started Jul 04 04:55:36 PM PDT 24
Finished Jul 04 04:55:38 PM PDT 24
Peak memory 212864 kb
Host smart-3ee1c164-f06d-49d0-a065-705529c3346b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168495216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.3168495216
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.1083152535
Short name T390
Test name
Test status
Simulation time 4766411343 ps
CPU time 23.58 seconds
Started Jul 04 04:55:32 PM PDT 24
Finished Jul 04 04:55:56 PM PDT 24
Peak memory 362420 kb
Host smart-4d3f9336-623b-4a93-b9ac-9ba374abed17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083152535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.1083152535
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.178926430
Short name T116
Test name
Test status
Simulation time 53384883844 ps
CPU time 434.35 seconds
Started Jul 04 04:55:39 PM PDT 24
Finished Jul 04 05:02:54 PM PDT 24
Peak memory 2282032 kb
Host smart-0dcd561b-1a50-4950-9a87-77b585294176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178926430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.178926430
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.4052641195
Short name T1501
Test name
Test status
Simulation time 845263225 ps
CPU time 39.35 seconds
Started Jul 04 04:55:36 PM PDT 24
Finished Jul 04 04:56:16 PM PDT 24
Peak memory 212816 kb
Host smart-667dda26-bdfd-44ee-8037-0888a94b770a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052641195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.4052641195
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.300052175
Short name T820
Test name
Test status
Simulation time 4918407150 ps
CPU time 2.8 seconds
Started Jul 04 04:55:41 PM PDT 24
Finished Jul 04 04:55:44 PM PDT 24
Peak memory 204796 kb
Host smart-1bd9ce56-2904-4806-8c9e-a76a6f901574
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300052175 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.300052175
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.880805496
Short name T1003
Test name
Test status
Simulation time 402228466 ps
CPU time 1.39 seconds
Started Jul 04 04:55:41 PM PDT 24
Finished Jul 04 04:55:42 PM PDT 24
Peak memory 204352 kb
Host smart-01a7652c-10b3-4c0c-bbd5-3e1f7b9858a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880805496 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_fifo_reset_tx.880805496
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.2775684058
Short name T129
Test name
Test status
Simulation time 684475210 ps
CPU time 2.11 seconds
Started Jul 04 04:55:39 PM PDT 24
Finished Jul 04 04:55:42 PM PDT 24
Peak memory 204740 kb
Host smart-e27114cc-722d-4c8e-8a91-7daae1817d8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775684058 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.2775684058
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.2779049859
Short name T1337
Test name
Test status
Simulation time 463170177 ps
CPU time 1.22 seconds
Started Jul 04 04:55:37 PM PDT 24
Finished Jul 04 04:55:39 PM PDT 24
Peak memory 204492 kb
Host smart-7e4d7180-82c7-43ce-9bd8-9cca3490614b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779049859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.2779049859
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.2413967336
Short name T1301
Test name
Test status
Simulation time 1368128298 ps
CPU time 4.19 seconds
Started Jul 04 04:55:38 PM PDT 24
Finished Jul 04 04:55:43 PM PDT 24
Peak memory 204656 kb
Host smart-6bae210c-4de3-4825-aec2-044b5e44bd0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413967336 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.2413967336
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2176560633
Short name T1209
Test name
Test status
Simulation time 4542732404 ps
CPU time 6.03 seconds
Started Jul 04 04:55:38 PM PDT 24
Finished Jul 04 04:55:44 PM PDT 24
Peak memory 213028 kb
Host smart-8c81ec04-75e5-4e94-8664-83ec016033c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176560633 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2176560633
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.2063229843
Short name T903
Test name
Test status
Simulation time 10282845237 ps
CPU time 8.35 seconds
Started Jul 04 04:55:36 PM PDT 24
Finished Jul 04 04:55:45 PM PDT 24
Peak memory 237236 kb
Host smart-583e2fbb-4518-4e0c-8aaa-c2f369024d6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063229843 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.2063229843
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.2935656663
Short name T668
Test name
Test status
Simulation time 3990042649 ps
CPU time 26.94 seconds
Started Jul 04 04:55:36 PM PDT 24
Finished Jul 04 04:56:03 PM PDT 24
Peak memory 204760 kb
Host smart-39960116-3ee7-4d86-8c70-4ebe8a95d520
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935656663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.2935656663
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.2762032653
Short name T402
Test name
Test status
Simulation time 1326851489 ps
CPU time 26.81 seconds
Started Jul 04 04:55:41 PM PDT 24
Finished Jul 04 04:56:08 PM PDT 24
Peak memory 222204 kb
Host smart-c9d0b4d1-757f-44f8-8f42-c475c103d90a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762032653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.2762032653
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.3584618869
Short name T584
Test name
Test status
Simulation time 15219667294 ps
CPU time 9.17 seconds
Started Jul 04 04:55:38 PM PDT 24
Finished Jul 04 04:55:47 PM PDT 24
Peak memory 204776 kb
Host smart-489ef9e0-bd26-45b0-8ca8-0d56f9dd6bf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584618869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.3584618869
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.3948144990
Short name T630
Test name
Test status
Simulation time 20688548701 ps
CPU time 921.86 seconds
Started Jul 04 04:55:40 PM PDT 24
Finished Jul 04 05:11:02 PM PDT 24
Peak memory 2485096 kb
Host smart-34d7bfa8-648f-4641-ad46-a6b5ae1e6255
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948144990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.3948144990
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3361177260
Short name T900
Test name
Test status
Simulation time 5759494293 ps
CPU time 7.94 seconds
Started Jul 04 04:55:39 PM PDT 24
Finished Jul 04 04:55:47 PM PDT 24
Peak memory 217592 kb
Host smart-42127b8b-fa6f-4256-9d13-c4f5868583ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361177260 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3361177260
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.3216580118
Short name T373
Test name
Test status
Simulation time 110592029 ps
CPU time 2.44 seconds
Started Jul 04 04:55:36 PM PDT 24
Finished Jul 04 04:55:40 PM PDT 24
Peak memory 204740 kb
Host smart-8a3282a7-d7cf-41e9-a111-bc988964c5cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216580118 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.3216580118
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.465489124
Short name T1450
Test name
Test status
Simulation time 112937288 ps
CPU time 0.66 seconds
Started Jul 04 04:55:44 PM PDT 24
Finished Jul 04 04:55:45 PM PDT 24
Peak memory 204320 kb
Host smart-9e42c08c-e2c1-4057-8f3e-e764ec336ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465489124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.465489124
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.3166310477
Short name T629
Test name
Test status
Simulation time 335581012 ps
CPU time 1.26 seconds
Started Jul 04 04:55:43 PM PDT 24
Finished Jul 04 04:55:45 PM PDT 24
Peak memory 212988 kb
Host smart-63ad007b-e2b5-4d4e-94f9-515f780811c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166310477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3166310477
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2797801496
Short name T826
Test name
Test status
Simulation time 725821905 ps
CPU time 8.43 seconds
Started Jul 04 04:55:38 PM PDT 24
Finished Jul 04 04:55:47 PM PDT 24
Peak memory 282712 kb
Host smart-110c05ff-01c8-4591-8963-61fef3cbf533
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797801496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2797801496
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3435643809
Short name T318
Test name
Test status
Simulation time 2139358305 ps
CPU time 65.15 seconds
Started Jul 04 04:55:38 PM PDT 24
Finished Jul 04 04:56:44 PM PDT 24
Peak memory 709376 kb
Host smart-af49ada4-5bc4-4e4f-9dc6-e0d50efd1c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435643809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3435643809
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.175281090
Short name T503
Test name
Test status
Simulation time 8488870439 ps
CPU time 77.47 seconds
Started Jul 04 04:55:38 PM PDT 24
Finished Jul 04 04:56:56 PM PDT 24
Peak memory 734520 kb
Host smart-70352375-f275-4311-a5c2-244cb72683d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175281090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.175281090
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.790358794
Short name T60
Test name
Test status
Simulation time 194789941 ps
CPU time 0.95 seconds
Started Jul 04 04:55:37 PM PDT 24
Finished Jul 04 04:55:38 PM PDT 24
Peak memory 204440 kb
Host smart-9c77d3ca-56a3-4194-ac5f-60405982a000
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790358794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fm
t.790358794
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.2858038280
Short name T888
Test name
Test status
Simulation time 619446648 ps
CPU time 5.14 seconds
Started Jul 04 04:55:38 PM PDT 24
Finished Jul 04 04:55:44 PM PDT 24
Peak memory 233216 kb
Host smart-2f3dc1e0-c0fc-4c9e-8212-687a710350c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858038280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.2858038280
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.2306477454
Short name T1285
Test name
Test status
Simulation time 18891699390 ps
CPU time 193.48 seconds
Started Jul 04 04:55:37 PM PDT 24
Finished Jul 04 04:58:52 PM PDT 24
Peak memory 929184 kb
Host smart-53127b00-513e-4efc-bf7b-c174a2c7f31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306477454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2306477454
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.4046571309
Short name T1423
Test name
Test status
Simulation time 932042595 ps
CPU time 9.3 seconds
Started Jul 04 04:55:41 PM PDT 24
Finished Jul 04 04:55:51 PM PDT 24
Peak memory 204632 kb
Host smart-aa08e16c-a298-42bd-bdf4-6de10104433f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046571309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.4046571309
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.1406647593
Short name T596
Test name
Test status
Simulation time 1636139282 ps
CPU time 23.46 seconds
Started Jul 04 04:55:44 PM PDT 24
Finished Jul 04 04:56:07 PM PDT 24
Peak memory 285948 kb
Host smart-e8cad1b9-e96e-4fd1-9914-cebf9f192118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406647593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.1406647593
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.3354716349
Short name T148
Test name
Test status
Simulation time 28677222 ps
CPU time 0.7 seconds
Started Jul 04 04:55:38 PM PDT 24
Finished Jul 04 04:55:39 PM PDT 24
Peak memory 204388 kb
Host smart-b7ffbe0e-8742-4c54-992e-75d31466d761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354716349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.3354716349
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.280878470
Short name T558
Test name
Test status
Simulation time 29600417991 ps
CPU time 280.52 seconds
Started Jul 04 04:55:36 PM PDT 24
Finished Jul 04 05:00:17 PM PDT 24
Peak memory 204868 kb
Host smart-52e26cf3-f5b3-471a-948a-432f0ace2d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280878470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.280878470
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.973869774
Short name T847
Test name
Test status
Simulation time 5880723997 ps
CPU time 86.58 seconds
Started Jul 04 04:55:37 PM PDT 24
Finished Jul 04 04:57:04 PM PDT 24
Peak memory 563060 kb
Host smart-492d16e1-391a-4a84-a8d7-b05912bade6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973869774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.973869774
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.2842876322
Short name T1342
Test name
Test status
Simulation time 3131457443 ps
CPU time 78.48 seconds
Started Jul 04 04:55:39 PM PDT 24
Finished Jul 04 04:56:58 PM PDT 24
Peak memory 353560 kb
Host smart-aac5e3e0-c1fe-4d8e-81d6-01c1074ea029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842876322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.2842876322
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.2782437147
Short name T277
Test name
Test status
Simulation time 51318195018 ps
CPU time 358.91 seconds
Started Jul 04 04:55:44 PM PDT 24
Finished Jul 04 05:01:44 PM PDT 24
Peak memory 1699812 kb
Host smart-20142848-fab2-4156-809f-4b7b1e1a3600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782437147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.2782437147
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.1721231874
Short name T445
Test name
Test status
Simulation time 2955204992 ps
CPU time 11.91 seconds
Started Jul 04 04:55:42 PM PDT 24
Finished Jul 04 04:55:55 PM PDT 24
Peak memory 221132 kb
Host smart-1755cbc1-8a73-4215-98ed-18a4162779cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721231874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.1721231874
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.828405023
Short name T471
Test name
Test status
Simulation time 3904535654 ps
CPU time 4.67 seconds
Started Jul 04 04:55:42 PM PDT 24
Finished Jul 04 04:55:47 PM PDT 24
Peak memory 213188 kb
Host smart-8c01687d-7d48-44e9-90e3-9aada3e062a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828405023 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.828405023
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.1762000240
Short name T341
Test name
Test status
Simulation time 672935479 ps
CPU time 1.13 seconds
Started Jul 04 04:55:45 PM PDT 24
Finished Jul 04 04:55:46 PM PDT 24
Peak memory 212844 kb
Host smart-e5e0f597-099c-445b-83f2-575c506baa22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762000240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.1762000240
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.3218368713
Short name T258
Test name
Test status
Simulation time 836233561 ps
CPU time 1.58 seconds
Started Jul 04 04:55:43 PM PDT 24
Finished Jul 04 04:55:45 PM PDT 24
Peak memory 209308 kb
Host smart-97346586-5d15-4e60-8e82-7c24250f6766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218368713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.3218368713
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.99904606
Short name T1452
Test name
Test status
Simulation time 161222568 ps
CPU time 1.32 seconds
Started Jul 04 04:55:44 PM PDT 24
Finished Jul 04 04:55:46 PM PDT 24
Peak memory 204440 kb
Host smart-f387610b-d655-49c0-b572-ec34ea65f707
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99904606 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.99904606
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.532930513
Short name T887
Test name
Test status
Simulation time 140984788 ps
CPU time 1.29 seconds
Started Jul 04 04:55:45 PM PDT 24
Finished Jul 04 04:55:47 PM PDT 24
Peak memory 204472 kb
Host smart-2644ea64-5a6f-4305-96ac-a4f108a426b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532930513 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.532930513
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.3331458978
Short name T1128
Test name
Test status
Simulation time 301449992 ps
CPU time 3.08 seconds
Started Jul 04 04:55:44 PM PDT 24
Finished Jul 04 04:55:47 PM PDT 24
Peak memory 204700 kb
Host smart-c11ef1af-c1b5-45b7-bbe9-8346e9530227
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331458978 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.3331458978
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.849151573
Short name T853
Test name
Test status
Simulation time 3753318324 ps
CPU time 4.51 seconds
Started Jul 04 04:55:43 PM PDT 24
Finished Jul 04 04:55:47 PM PDT 24
Peak memory 204656 kb
Host smart-e2d7a22e-65be-4efa-bb32-8ffcb30a2878
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849151573 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.849151573
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1625697902
Short name T590
Test name
Test status
Simulation time 18953453236 ps
CPU time 112.69 seconds
Started Jul 04 04:55:44 PM PDT 24
Finished Jul 04 04:57:38 PM PDT 24
Peak memory 1552436 kb
Host smart-2fdb0fa9-b811-435a-82cc-dee422532571
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625697902 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1625697902
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1721099043
Short name T1343
Test name
Test status
Simulation time 6687214013 ps
CPU time 12.43 seconds
Started Jul 04 04:55:42 PM PDT 24
Finished Jul 04 04:55:55 PM PDT 24
Peak memory 204916 kb
Host smart-e1428755-e61d-4fc9-b0e7-80c0bf10051d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721099043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1721099043
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3228275948
Short name T527
Test name
Test status
Simulation time 1890685695 ps
CPU time 8 seconds
Started Jul 04 04:55:42 PM PDT 24
Finished Jul 04 04:55:51 PM PDT 24
Peak memory 204712 kb
Host smart-ed2f56c6-56e6-4e70-91d1-a73f9df24f8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228275948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3228275948
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.4044458630
Short name T359
Test name
Test status
Simulation time 41448074099 ps
CPU time 649.53 seconds
Started Jul 04 04:55:43 PM PDT 24
Finished Jul 04 05:06:33 PM PDT 24
Peak memory 5389884 kb
Host smart-201bb58e-f83f-45b6-89e6-e1e585a5bc3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044458630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.4044458630
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.4252610941
Short name T1279
Test name
Test status
Simulation time 5123835765 ps
CPU time 32.75 seconds
Started Jul 04 04:55:43 PM PDT 24
Finished Jul 04 04:56:16 PM PDT 24
Peak memory 664688 kb
Host smart-8787ac07-92bc-4479-95b7-24683950a7dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252610941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.4252610941
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.2095128278
Short name T813
Test name
Test status
Simulation time 5151312633 ps
CPU time 6.74 seconds
Started Jul 04 04:55:43 PM PDT 24
Finished Jul 04 04:55:50 PM PDT 24
Peak memory 213088 kb
Host smart-ffcc0895-9630-4e80-a2fe-f832176a4cd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095128278 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.2095128278
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.1774546409
Short name T1330
Test name
Test status
Simulation time 118022620 ps
CPU time 2.65 seconds
Started Jul 04 04:55:42 PM PDT 24
Finished Jul 04 04:55:45 PM PDT 24
Peak memory 204732 kb
Host smart-eb1da441-f088-4c4a-b3fa-2eded593d568
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774546409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.1774546409
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.2198830619
Short name T328
Test name
Test status
Simulation time 26870573 ps
CPU time 0.65 seconds
Started Jul 04 04:55:53 PM PDT 24
Finished Jul 04 04:55:54 PM PDT 24
Peak memory 204356 kb
Host smart-861bc7e7-7dab-41f9-b5a3-8b5c418322ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198830619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.2198830619
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.435415930
Short name T1497
Test name
Test status
Simulation time 525994704 ps
CPU time 1.44 seconds
Started Jul 04 04:55:52 PM PDT 24
Finished Jul 04 04:55:54 PM PDT 24
Peak memory 213008 kb
Host smart-4a902268-61a8-4788-b56e-bdd0954f596f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435415930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.435415930
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2073939312
Short name T723
Test name
Test status
Simulation time 867422974 ps
CPU time 9.99 seconds
Started Jul 04 04:55:51 PM PDT 24
Finished Jul 04 04:56:01 PM PDT 24
Peak memory 299336 kb
Host smart-2d461b48-3ab9-4cb3-99e3-891d1044a0eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073939312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2073939312
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.1080961286
Short name T266
Test name
Test status
Simulation time 3902109442 ps
CPU time 110.12 seconds
Started Jul 04 04:55:52 PM PDT 24
Finished Jul 04 04:57:42 PM PDT 24
Peak memory 417528 kb
Host smart-b75dcf8c-e565-412f-8a1f-ea3533286509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080961286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.1080961286
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.725704519
Short name T1102
Test name
Test status
Simulation time 3856792736 ps
CPU time 66.18 seconds
Started Jul 04 04:55:42 PM PDT 24
Finished Jul 04 04:56:48 PM PDT 24
Peak memory 675840 kb
Host smart-c6e839f9-fee1-4d2d-aad8-bc0ece8a92ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725704519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.725704519
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1138699257
Short name T1193
Test name
Test status
Simulation time 737165533 ps
CPU time 1.12 seconds
Started Jul 04 04:55:43 PM PDT 24
Finished Jul 04 04:55:45 PM PDT 24
Peak memory 204580 kb
Host smart-7dc365c5-7f1d-4260-9daa-c4a4e49573b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138699257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1138699257
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2682630332
Short name T556
Test name
Test status
Simulation time 507206987 ps
CPU time 6.65 seconds
Started Jul 04 04:55:51 PM PDT 24
Finished Jul 04 04:55:57 PM PDT 24
Peak memory 204716 kb
Host smart-e740ad42-9edb-4b56-a9fd-888c23fa3e62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682630332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2682630332
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.3777562184
Short name T274
Test name
Test status
Simulation time 4440489261 ps
CPU time 134.84 seconds
Started Jul 04 04:55:42 PM PDT 24
Finished Jul 04 04:57:57 PM PDT 24
Peak memory 1235708 kb
Host smart-586cabc3-e992-4c12-94b6-9cc448dd2f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777562184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.3777562184
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.3185172867
Short name T496
Test name
Test status
Simulation time 1349865404 ps
CPU time 5.77 seconds
Started Jul 04 04:55:51 PM PDT 24
Finished Jul 04 04:55:57 PM PDT 24
Peak memory 204676 kb
Host smart-4f334a44-b0e7-4538-8012-5dd507a68f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185172867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.3185172867
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.1634153877
Short name T35
Test name
Test status
Simulation time 973386362 ps
CPU time 17.05 seconds
Started Jul 04 04:55:50 PM PDT 24
Finished Jul 04 04:56:07 PM PDT 24
Peak memory 306756 kb
Host smart-b67d0dce-d467-4ed6-8a8d-798e6b60fb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634153877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.1634153877
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.3122270152
Short name T80
Test name
Test status
Simulation time 45509348 ps
CPU time 0.69 seconds
Started Jul 04 04:55:42 PM PDT 24
Finished Jul 04 04:55:43 PM PDT 24
Peak memory 204796 kb
Host smart-b9779d41-0668-41d3-b08d-277859414408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122270152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3122270152
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.271735921
Short name T354
Test name
Test status
Simulation time 6986187196 ps
CPU time 69.95 seconds
Started Jul 04 04:55:51 PM PDT 24
Finished Jul 04 04:57:01 PM PDT 24
Peak memory 235704 kb
Host smart-3ad60cf0-9a5e-460c-8f9f-778c40a8c69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271735921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.271735921
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.2349307904
Short name T437
Test name
Test status
Simulation time 795336041 ps
CPU time 9.66 seconds
Started Jul 04 04:55:49 PM PDT 24
Finished Jul 04 04:55:59 PM PDT 24
Peak memory 278312 kb
Host smart-9c487dce-9a12-44e4-b183-59e9596bd0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349307904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.2349307904
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2265782657
Short name T701
Test name
Test status
Simulation time 1524099462 ps
CPU time 21.14 seconds
Started Jul 04 04:55:45 PM PDT 24
Finished Jul 04 04:56:07 PM PDT 24
Peak memory 301940 kb
Host smart-8dc57dfd-2e6b-4ef4-9e8d-6d18ca6f067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265782657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2265782657
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.513400444
Short name T1461
Test name
Test status
Simulation time 20995038530 ps
CPU time 1261.29 seconds
Started Jul 04 04:55:52 PM PDT 24
Finished Jul 04 05:16:54 PM PDT 24
Peak memory 3896664 kb
Host smart-9d9500b9-395f-4d48-9aae-00b936fbb30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513400444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.513400444
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.3754431578
Short name T1061
Test name
Test status
Simulation time 674115376 ps
CPU time 12.37 seconds
Started Jul 04 04:55:51 PM PDT 24
Finished Jul 04 04:56:04 PM PDT 24
Peak memory 221016 kb
Host smart-c9ff856c-7d4a-4971-8e10-c58f4d55e70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754431578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.3754431578
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.3301522102
Short name T1420
Test name
Test status
Simulation time 1670974059 ps
CPU time 2.59 seconds
Started Jul 04 04:55:50 PM PDT 24
Finished Jul 04 04:55:53 PM PDT 24
Peak memory 204720 kb
Host smart-d996ee93-1ba4-4d5e-a7ca-fa30bd3e0fb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301522102 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3301522102
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.511276394
Short name T311
Test name
Test status
Simulation time 641097249 ps
CPU time 1.19 seconds
Started Jul 04 04:55:53 PM PDT 24
Finished Jul 04 04:55:54 PM PDT 24
Peak memory 204836 kb
Host smart-db0e3423-315a-46d8-b803-f01081d2ccd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511276394 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_fifo_reset_tx.511276394
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.3234255427
Short name T289
Test name
Test status
Simulation time 337835379 ps
CPU time 1.23 seconds
Started Jul 04 04:55:51 PM PDT 24
Finished Jul 04 04:55:53 PM PDT 24
Peak memory 204476 kb
Host smart-56107528-c5fb-4fb0-ab23-464b0abd462c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234255427 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.3234255427
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.4173316819
Short name T837
Test name
Test status
Simulation time 109245458 ps
CPU time 1.13 seconds
Started Jul 04 04:55:50 PM PDT 24
Finished Jul 04 04:55:52 PM PDT 24
Peak memory 204568 kb
Host smart-369ca05d-222c-4301-9ff0-99b87208804e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173316819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.4173316819
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.999272128
Short name T1147
Test name
Test status
Simulation time 2251680184 ps
CPU time 6.78 seconds
Started Jul 04 04:55:51 PM PDT 24
Finished Jul 04 04:55:58 PM PDT 24
Peak memory 221088 kb
Host smart-ac885e41-3d8d-4694-ab77-0658c72de89d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999272128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_intr_smoke.999272128
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.1605281739
Short name T999
Test name
Test status
Simulation time 28734893310 ps
CPU time 65.84 seconds
Started Jul 04 04:55:52 PM PDT 24
Finished Jul 04 04:56:58 PM PDT 24
Peak memory 1455260 kb
Host smart-7dbb7cd6-5fd6-4214-8d79-d7c95e39a5d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605281739 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.1605281739
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2362167892
Short name T93
Test name
Test status
Simulation time 902353963 ps
CPU time 33.96 seconds
Started Jul 04 04:55:53 PM PDT 24
Finished Jul 04 04:56:27 PM PDT 24
Peak memory 204708 kb
Host smart-b7b39a54-80b0-4783-8a64-d2719fdd5ddc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362167892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2362167892
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.1250860740
Short name T1075
Test name
Test status
Simulation time 7632601935 ps
CPU time 16.98 seconds
Started Jul 04 04:55:53 PM PDT 24
Finished Jul 04 04:56:10 PM PDT 24
Peak memory 214780 kb
Host smart-97104ee8-9c0d-41ca-a14c-6debd5754703
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250860740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.1250860740
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2355883888
Short name T142
Test name
Test status
Simulation time 22755706188 ps
CPU time 53.67 seconds
Started Jul 04 04:55:51 PM PDT 24
Finished Jul 04 04:56:45 PM PDT 24
Peak memory 715940 kb
Host smart-ff51628c-dbd7-4c6e-96b7-19f2de15578a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355883888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2355883888
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.604735232
Short name T515
Test name
Test status
Simulation time 1052774980 ps
CPU time 6.66 seconds
Started Jul 04 04:55:53 PM PDT 24
Finished Jul 04 04:56:00 PM PDT 24
Peak memory 213024 kb
Host smart-63249f8a-0eec-4836-899a-0c3c5990975c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604735232 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_timeout.604735232
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.1186869133
Short name T1116
Test name
Test status
Simulation time 247348863 ps
CPU time 4.22 seconds
Started Jul 04 04:55:51 PM PDT 24
Finished Jul 04 04:55:55 PM PDT 24
Peak memory 204696 kb
Host smart-8e4711f3-6562-4707-842b-541ef8bff4b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186869133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.1186869133
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.1469260067
Short name T1105
Test name
Test status
Simulation time 19862924 ps
CPU time 0.66 seconds
Started Jul 04 04:52:16 PM PDT 24
Finished Jul 04 04:52:17 PM PDT 24
Peak memory 204348 kb
Host smart-dc6f6559-7bba-4008-8ecb-2c7b1fa439d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469260067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1469260067
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.2182502878
Short name T1117
Test name
Test status
Simulation time 179036995 ps
CPU time 1.86 seconds
Started Jul 04 04:52:15 PM PDT 24
Finished Jul 04 04:52:17 PM PDT 24
Peak memory 216696 kb
Host smart-ee68168c-266d-45b8-8a38-dafb3909892b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182502878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.2182502878
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2414396134
Short name T1515
Test name
Test status
Simulation time 329849283 ps
CPU time 7.32 seconds
Started Jul 04 04:52:15 PM PDT 24
Finished Jul 04 04:52:22 PM PDT 24
Peak memory 270860 kb
Host smart-283b34d3-738a-4927-9c88-7846268a05fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414396134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2414396134
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3219869853
Short name T994
Test name
Test status
Simulation time 6357181105 ps
CPU time 43.16 seconds
Started Jul 04 04:52:15 PM PDT 24
Finished Jul 04 04:52:59 PM PDT 24
Peak memory 539128 kb
Host smart-71629b07-5dbf-4848-a1d5-268c7c3dbdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219869853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3219869853
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.1756587050
Short name T100
Test name
Test status
Simulation time 1844601452 ps
CPU time 122.13 seconds
Started Jul 04 04:52:20 PM PDT 24
Finished Jul 04 04:54:22 PM PDT 24
Peak memory 610708 kb
Host smart-d6a43c32-09af-4ff0-a41c-b12cf2c2f7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756587050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1756587050
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.4053721343
Short name T1244
Test name
Test status
Simulation time 339692418 ps
CPU time 1.39 seconds
Started Jul 04 04:52:18 PM PDT 24
Finished Jul 04 04:52:20 PM PDT 24
Peak memory 204460 kb
Host smart-dd91d91e-a4d6-48be-a82a-15c6a3b5ff7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053721343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.4053721343
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.1087984630
Short name T235
Test name
Test status
Simulation time 156211523 ps
CPU time 3.41 seconds
Started Jul 04 04:52:17 PM PDT 24
Finished Jul 04 04:52:21 PM PDT 24
Peak memory 204704 kb
Host smart-ff12dcfc-dab8-4675-981d-c70071609274
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087984630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
1087984630
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1777742582
Short name T890
Test name
Test status
Simulation time 17494446937 ps
CPU time 113.16 seconds
Started Jul 04 04:52:08 PM PDT 24
Finished Jul 04 04:54:02 PM PDT 24
Peak memory 1295356 kb
Host smart-bdf7b5ae-bbc1-412c-be62-a21475c559dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777742582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1777742582
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.613956594
Short name T792
Test name
Test status
Simulation time 2475641818 ps
CPU time 11.77 seconds
Started Jul 04 04:52:15 PM PDT 24
Finished Jul 04 04:52:27 PM PDT 24
Peak memory 204816 kb
Host smart-7d7e2feb-d00d-44f2-b2ab-f981c792ba67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613956594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.613956594
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.2946080340
Short name T1084
Test name
Test status
Simulation time 1787598084 ps
CPU time 87.09 seconds
Started Jul 04 04:52:16 PM PDT 24
Finished Jul 04 04:53:43 PM PDT 24
Peak memory 348672 kb
Host smart-0a324e82-773c-430d-82ec-1531b2d8d162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946080340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.2946080340
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.2141965335
Short name T149
Test name
Test status
Simulation time 29020212 ps
CPU time 0.74 seconds
Started Jul 04 04:52:08 PM PDT 24
Finished Jul 04 04:52:09 PM PDT 24
Peak memory 204412 kb
Host smart-3f0d8579-8376-44b0-b34c-299481157200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141965335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.2141965335
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.684318843
Short name T1194
Test name
Test status
Simulation time 8962147436 ps
CPU time 97.48 seconds
Started Jul 04 04:52:15 PM PDT 24
Finished Jul 04 04:53:53 PM PDT 24
Peak memory 204932 kb
Host smart-39b524e9-ead6-40fe-a29a-e199d569b612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684318843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.684318843
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.4285879562
Short name T899
Test name
Test status
Simulation time 50283554 ps
CPU time 2.8 seconds
Started Jul 04 04:52:14 PM PDT 24
Finished Jul 04 04:52:17 PM PDT 24
Peak memory 215480 kb
Host smart-f869e179-9d0c-4ed8-998a-3879538a66e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285879562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.4285879562
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.2025366854
Short name T770
Test name
Test status
Simulation time 4024485250 ps
CPU time 22.84 seconds
Started Jul 04 04:52:09 PM PDT 24
Finished Jul 04 04:52:32 PM PDT 24
Peak memory 313760 kb
Host smart-1471f8df-6273-4e66-8d9c-b43bd39fc1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025366854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2025366854
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.4021049145
Short name T1340
Test name
Test status
Simulation time 48350001180 ps
CPU time 683.35 seconds
Started Jul 04 04:52:16 PM PDT 24
Finished Jul 04 05:03:40 PM PDT 24
Peak memory 2092088 kb
Host smart-ed0f7789-1900-4451-8a38-a7a2b4473374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021049145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.4021049145
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.3307438507
Short name T575
Test name
Test status
Simulation time 587617532 ps
CPU time 25.88 seconds
Started Jul 04 04:52:16 PM PDT 24
Finished Jul 04 04:52:43 PM PDT 24
Peak memory 212848 kb
Host smart-fd084140-0dc4-4167-b502-390256cda2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307438507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3307438507
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.1842237597
Short name T187
Test name
Test status
Simulation time 998990014 ps
CPU time 1.21 seconds
Started Jul 04 04:52:15 PM PDT 24
Finished Jul 04 04:52:17 PM PDT 24
Peak memory 222068 kb
Host smart-112dd525-d1b4-4134-8fd8-b45397766b7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842237597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1842237597
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.1084190048
Short name T1430
Test name
Test status
Simulation time 565003829 ps
CPU time 1.9 seconds
Started Jul 04 04:52:18 PM PDT 24
Finished Jul 04 04:52:20 PM PDT 24
Peak memory 204760 kb
Host smart-bf22403f-2ef5-41d9-9430-e5f45b2ae73b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084190048 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1084190048
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3944919000
Short name T1077
Test name
Test status
Simulation time 570555198 ps
CPU time 1.26 seconds
Started Jul 04 04:52:15 PM PDT 24
Finished Jul 04 04:52:17 PM PDT 24
Peak memory 204736 kb
Host smart-7f29228c-72fc-48e4-8aae-387c2cad7128
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944919000 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3944919000
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1327519983
Short name T980
Test name
Test status
Simulation time 537467596 ps
CPU time 0.89 seconds
Started Jul 04 04:52:15 PM PDT 24
Finished Jul 04 04:52:16 PM PDT 24
Peak memory 204512 kb
Host smart-5fa136ec-6117-43f4-b639-e1ee7e0bc2bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327519983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1327519983
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.1339307005
Short name T948
Test name
Test status
Simulation time 527753820 ps
CPU time 2.52 seconds
Started Jul 04 04:52:16 PM PDT 24
Finished Jul 04 04:52:19 PM PDT 24
Peak memory 204688 kb
Host smart-ab8ff58d-4d87-4f2a-ace7-c2ff881a2130
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339307005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.1339307005
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.345541762
Short name T1516
Test name
Test status
Simulation time 53348486 ps
CPU time 0.82 seconds
Started Jul 04 04:52:16 PM PDT 24
Finished Jul 04 04:52:17 PM PDT 24
Peak memory 204500 kb
Host smart-be2408ef-a62c-4763-90fd-c2ef0f872768
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345541762 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.345541762
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3029858561
Short name T618
Test name
Test status
Simulation time 4184100981 ps
CPU time 5.59 seconds
Started Jul 04 04:52:14 PM PDT 24
Finished Jul 04 04:52:20 PM PDT 24
Peak memory 213008 kb
Host smart-5ed9523a-2ced-4136-a40c-a443e984fce8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029858561 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3029858561
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3306073618
Short name T779
Test name
Test status
Simulation time 17554226317 ps
CPU time 281.97 seconds
Started Jul 04 04:52:16 PM PDT 24
Finished Jul 04 04:56:59 PM PDT 24
Peak memory 3896904 kb
Host smart-c433a8d1-f352-4b72-9eb2-2e14179387d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306073618 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3306073618
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.1413741999
Short name T1470
Test name
Test status
Simulation time 24779026001 ps
CPU time 20.71 seconds
Started Jul 04 04:52:16 PM PDT 24
Finished Jul 04 04:52:37 PM PDT 24
Peak memory 204740 kb
Host smart-737785f6-8572-4fc9-a02c-c735bdf8e3d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413741999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.1413741999
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.4081390213
Short name T465
Test name
Test status
Simulation time 967446295 ps
CPU time 17.76 seconds
Started Jul 04 04:52:14 PM PDT 24
Finished Jul 04 04:52:32 PM PDT 24
Peak memory 211492 kb
Host smart-46c274d4-2b84-46ca-b7e8-bf0d2d9040df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081390213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.4081390213
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.4056729541
Short name T463
Test name
Test status
Simulation time 33609590782 ps
CPU time 295.36 seconds
Started Jul 04 04:52:15 PM PDT 24
Finished Jul 04 04:57:10 PM PDT 24
Peak memory 3421316 kb
Host smart-dfd5a7b9-de89-4736-aca9-b7e4c4de11f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056729541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.4056729541
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.819319497
Short name T29
Test name
Test status
Simulation time 18212588906 ps
CPU time 83.43 seconds
Started Jul 04 04:52:13 PM PDT 24
Finished Jul 04 04:53:37 PM PDT 24
Peak memory 497088 kb
Host smart-67aaa126-4106-4f22-960c-4c36b107a416
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819319497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stretch.819319497
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.1126127418
Short name T1056
Test name
Test status
Simulation time 1068276824 ps
CPU time 7.16 seconds
Started Jul 04 04:52:13 PM PDT 24
Finished Jul 04 04:52:20 PM PDT 24
Peak memory 218932 kb
Host smart-8de0524e-88cb-477d-bf5d-020cd0508860
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126127418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.1126127418
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.4165037167
Short name T567
Test name
Test status
Simulation time 161317734 ps
CPU time 2.68 seconds
Started Jul 04 04:52:15 PM PDT 24
Finished Jul 04 04:52:19 PM PDT 24
Peak memory 204804 kb
Host smart-460318d5-3dfe-47bf-b9f9-033becb4d5c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165037167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.4165037167
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.449024462
Short name T340
Test name
Test status
Simulation time 26408510 ps
CPU time 0.63 seconds
Started Jul 04 04:56:05 PM PDT 24
Finished Jul 04 04:56:06 PM PDT 24
Peak memory 204356 kb
Host smart-8dc3c434-c160-4796-8384-b2eaa4af7291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449024462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.449024462
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.148356241
Short name T1119
Test name
Test status
Simulation time 1488094996 ps
CPU time 8.02 seconds
Started Jul 04 04:55:58 PM PDT 24
Finished Jul 04 04:56:06 PM PDT 24
Peak memory 266040 kb
Host smart-8bceb224-0a81-4e64-81b1-8c1d7e1ddf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148356241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.148356241
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.3916990685
Short name T1393
Test name
Test status
Simulation time 373848279 ps
CPU time 19.07 seconds
Started Jul 04 04:55:59 PM PDT 24
Finished Jul 04 04:56:18 PM PDT 24
Peak memory 281864 kb
Host smart-0b81cece-133d-4408-a522-ccf89366586f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916990685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.3916990685
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.1079890435
Short name T89
Test name
Test status
Simulation time 1854220242 ps
CPU time 61.94 seconds
Started Jul 04 04:56:00 PM PDT 24
Finished Jul 04 04:57:02 PM PDT 24
Peak memory 593956 kb
Host smart-e606b66d-22b9-4fa7-814b-866622e83dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079890435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.1079890435
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.3517063556
Short name T528
Test name
Test status
Simulation time 7346410887 ps
CPU time 125.32 seconds
Started Jul 04 04:55:58 PM PDT 24
Finished Jul 04 04:58:04 PM PDT 24
Peak memory 643128 kb
Host smart-9e5e7e68-ac20-4abd-ba51-97a663af6dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517063556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3517063556
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.881833264
Short name T1111
Test name
Test status
Simulation time 464770762 ps
CPU time 0.96 seconds
Started Jul 04 04:55:58 PM PDT 24
Finished Jul 04 04:55:59 PM PDT 24
Peak memory 204396 kb
Host smart-1ecd3904-04be-48e1-a8ab-d151a0b0f7a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881833264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fm
t.881833264
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.1629876039
Short name T869
Test name
Test status
Simulation time 296825585 ps
CPU time 8.66 seconds
Started Jul 04 04:55:58 PM PDT 24
Finished Jul 04 04:56:06 PM PDT 24
Peak memory 229296 kb
Host smart-8c0a66d2-c76d-4bd9-a478-0ad7fe809644
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629876039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.1629876039
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.1658617583
Short name T488
Test name
Test status
Simulation time 13231285457 ps
CPU time 82.95 seconds
Started Jul 04 04:55:56 PM PDT 24
Finished Jul 04 04:57:20 PM PDT 24
Peak memory 963752 kb
Host smart-4001d91b-ca9c-460a-aa92-67a09b0d06af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658617583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1658617583
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.1237974795
Short name T254
Test name
Test status
Simulation time 485790880 ps
CPU time 4 seconds
Started Jul 04 04:55:57 PM PDT 24
Finished Jul 04 04:56:01 PM PDT 24
Peak memory 204732 kb
Host smart-d03c7780-b207-44df-9775-c0a6743c1449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237974795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.1237974795
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.2708679303
Short name T631
Test name
Test status
Simulation time 5789863698 ps
CPU time 27.28 seconds
Started Jul 04 04:55:59 PM PDT 24
Finished Jul 04 04:56:26 PM PDT 24
Peak memory 300684 kb
Host smart-97eaf966-2ef7-4334-b1fb-41c91f7996a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708679303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.2708679303
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.1192386735
Short name T1263
Test name
Test status
Simulation time 46260910 ps
CPU time 0.67 seconds
Started Jul 04 04:55:53 PM PDT 24
Finished Jul 04 04:55:54 PM PDT 24
Peak memory 204412 kb
Host smart-f7063cd5-1512-4a68-83d2-ab96dfe5431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192386735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.1192386735
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.1801984938
Short name T37
Test name
Test status
Simulation time 26022789620 ps
CPU time 74.92 seconds
Started Jul 04 04:55:57 PM PDT 24
Finished Jul 04 04:57:12 PM PDT 24
Peak memory 212976 kb
Host smart-5070c14b-0300-4ec0-af22-5e18d4a481d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801984938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.1801984938
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.1756015726
Short name T551
Test name
Test status
Simulation time 699468942 ps
CPU time 13.84 seconds
Started Jul 04 04:55:59 PM PDT 24
Finished Jul 04 04:56:13 PM PDT 24
Peak memory 307592 kb
Host smart-206fb739-1f9f-4c17-848e-f121bf999d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756015726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.1756015726
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2345797965
Short name T305
Test name
Test status
Simulation time 2811682909 ps
CPU time 59.45 seconds
Started Jul 04 04:55:53 PM PDT 24
Finished Jul 04 04:56:53 PM PDT 24
Peak memory 269848 kb
Host smart-ef32a4d7-9371-4014-9266-30b3d8359b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345797965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2345797965
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.1989437512
Short name T543
Test name
Test status
Simulation time 3653109855 ps
CPU time 42.61 seconds
Started Jul 04 04:56:08 PM PDT 24
Finished Jul 04 04:56:51 PM PDT 24
Peak memory 213020 kb
Host smart-dd134d8c-6357-4d48-8cbf-c958a439dbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989437512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1989437512
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3628874677
Short name T345
Test name
Test status
Simulation time 1136412919 ps
CPU time 5.85 seconds
Started Jul 04 04:55:57 PM PDT 24
Finished Jul 04 04:56:03 PM PDT 24
Peak memory 214080 kb
Host smart-f5627202-8886-4c2a-8533-0b713b1dccc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628874677 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3628874677
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2925985432
Short name T838
Test name
Test status
Simulation time 302195394 ps
CPU time 0.88 seconds
Started Jul 04 04:56:00 PM PDT 24
Finished Jul 04 04:56:01 PM PDT 24
Peak memory 204472 kb
Host smart-e4283450-a37a-483c-9e56-d5d103311565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925985432 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2925985432
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.507401662
Short name T969
Test name
Test status
Simulation time 1047638120 ps
CPU time 0.93 seconds
Started Jul 04 04:56:08 PM PDT 24
Finished Jul 04 04:56:09 PM PDT 24
Peak memory 204464 kb
Host smart-a53fb9c9-2d01-49fb-9981-06e3e8dfff24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507401662 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.507401662
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.4161714441
Short name T828
Test name
Test status
Simulation time 612471788 ps
CPU time 3.12 seconds
Started Jul 04 04:55:59 PM PDT 24
Finished Jul 04 04:56:02 PM PDT 24
Peak memory 204680 kb
Host smart-18f66bcd-a2b4-4214-bb77-2ecb39076cbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161714441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.4161714441
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.3934391328
Short name T357
Test name
Test status
Simulation time 83931800 ps
CPU time 1.03 seconds
Started Jul 04 04:56:04 PM PDT 24
Finished Jul 04 04:56:05 PM PDT 24
Peak memory 204416 kb
Host smart-fc8df4b9-936c-4717-8a65-08ad7f95585e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934391328 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.3934391328
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.3299141777
Short name T1123
Test name
Test status
Simulation time 12326055216 ps
CPU time 4.93 seconds
Started Jul 04 04:55:57 PM PDT 24
Finished Jul 04 04:56:03 PM PDT 24
Peak memory 205588 kb
Host smart-c6b697a9-917f-456f-8112-f33d003f21de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299141777 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.3299141777
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.1201798459
Short name T839
Test name
Test status
Simulation time 20223427108 ps
CPU time 66.6 seconds
Started Jul 04 04:56:00 PM PDT 24
Finished Jul 04 04:57:07 PM PDT 24
Peak memory 977044 kb
Host smart-90b40520-f9d9-4488-99f4-c1549211301a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201798459 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.1201798459
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.3887025814
Short name T157
Test name
Test status
Simulation time 2365795315 ps
CPU time 22.47 seconds
Started Jul 04 04:56:03 PM PDT 24
Finished Jul 04 04:56:25 PM PDT 24
Peak memory 204776 kb
Host smart-b3a57aab-c27f-4f9b-8d7b-3035d4546698
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887025814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.3887025814
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.1617612362
Short name T297
Test name
Test status
Simulation time 758380937 ps
CPU time 29.37 seconds
Started Jul 04 04:55:57 PM PDT 24
Finished Jul 04 04:56:27 PM PDT 24
Peak memory 204740 kb
Host smart-a5b76292-b90b-48e0-b5fe-0b733b499297
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617612362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.1617612362
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.1777348529
Short name T1498
Test name
Test status
Simulation time 20271935650 ps
CPU time 21.1 seconds
Started Jul 04 04:55:56 PM PDT 24
Finished Jul 04 04:56:18 PM PDT 24
Peak memory 204792 kb
Host smart-0f109062-b063-4fa8-85d9-0c6d04ce354e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777348529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.1777348529
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.2830167448
Short name T1227
Test name
Test status
Simulation time 35900625268 ps
CPU time 258.81 seconds
Started Jul 04 04:56:00 PM PDT 24
Finished Jul 04 05:00:19 PM PDT 24
Peak memory 1982388 kb
Host smart-07f3bdfb-5be5-4a41-a699-691f2b2628df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830167448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.2830167448
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.2568471137
Short name T1183
Test name
Test status
Simulation time 13270670388 ps
CPU time 6.38 seconds
Started Jul 04 04:55:59 PM PDT 24
Finished Jul 04 04:56:05 PM PDT 24
Peak memory 213808 kb
Host smart-e1256e51-524f-4155-9762-4b6294e3fde7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568471137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.2568471137
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.1127912408
Short name T430
Test name
Test status
Simulation time 219161452 ps
CPU time 3.23 seconds
Started Jul 04 04:56:04 PM PDT 24
Finished Jul 04 04:56:07 PM PDT 24
Peak memory 204664 kb
Host smart-5663006a-52e3-432e-a40e-f0ef4ac5e294
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127912408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.1127912408
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.1619750038
Short name T464
Test name
Test status
Simulation time 17757275 ps
CPU time 0.64 seconds
Started Jul 04 04:56:11 PM PDT 24
Finished Jul 04 04:56:12 PM PDT 24
Peak memory 204284 kb
Host smart-9a252247-4b44-4962-b296-158292b4339b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619750038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1619750038
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3263696477
Short name T1078
Test name
Test status
Simulation time 115164248 ps
CPU time 1.6 seconds
Started Jul 04 04:56:06 PM PDT 24
Finished Jul 04 04:56:08 PM PDT 24
Peak memory 213076 kb
Host smart-ee3a8f29-7b4c-4d81-b0f2-4b8f43317353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263696477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3263696477
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.1192122704
Short name T589
Test name
Test status
Simulation time 329939708 ps
CPU time 17.31 seconds
Started Jul 04 04:56:05 PM PDT 24
Finished Jul 04 04:56:23 PM PDT 24
Peak memory 273660 kb
Host smart-5597c8fa-fedb-40c2-850f-34190f950f55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192122704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.1192122704
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.3542508498
Short name T1028
Test name
Test status
Simulation time 3830769239 ps
CPU time 50.37 seconds
Started Jul 04 04:56:03 PM PDT 24
Finished Jul 04 04:56:53 PM PDT 24
Peak memory 589164 kb
Host smart-cee5a166-c306-4afb-af67-aa7a01a3380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542508498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.3542508498
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.714242067
Short name T1494
Test name
Test status
Simulation time 1572435811 ps
CPU time 108.21 seconds
Started Jul 04 04:56:07 PM PDT 24
Finished Jul 04 04:57:55 PM PDT 24
Peak memory 595804 kb
Host smart-af8b93c8-d2dc-49bc-8a6a-39d63c5855e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714242067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.714242067
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3574353282
Short name T932
Test name
Test status
Simulation time 152552367 ps
CPU time 0.99 seconds
Started Jul 04 04:56:07 PM PDT 24
Finished Jul 04 04:56:08 PM PDT 24
Peak memory 204356 kb
Host smart-69eac4ff-f123-4446-9a79-2dd3fa617ecd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574353282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3574353282
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.550254525
Short name T998
Test name
Test status
Simulation time 222353779 ps
CPU time 12.01 seconds
Started Jul 04 04:56:03 PM PDT 24
Finished Jul 04 04:56:15 PM PDT 24
Peak memory 246024 kb
Host smart-ceec061f-1e18-41b7-bbc6-9fc2dea99316
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550254525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
550254525
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.3137999943
Short name T699
Test name
Test status
Simulation time 946367718 ps
CPU time 6.2 seconds
Started Jul 04 04:56:13 PM PDT 24
Finished Jul 04 04:56:19 PM PDT 24
Peak memory 204760 kb
Host smart-b175c807-4881-4d33-b066-848ba6f7826c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137999943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.3137999943
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.2438186522
Short name T961
Test name
Test status
Simulation time 1541151149 ps
CPU time 66.22 seconds
Started Jul 04 04:56:13 PM PDT 24
Finished Jul 04 04:57:19 PM PDT 24
Peak memory 277840 kb
Host smart-5a4bb178-3545-4651-802e-53a3ff28877f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438186522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.2438186522
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.1030320032
Short name T1462
Test name
Test status
Simulation time 28613072 ps
CPU time 0.73 seconds
Started Jul 04 04:56:03 PM PDT 24
Finished Jul 04 04:56:04 PM PDT 24
Peak memory 204396 kb
Host smart-e0106ced-07a7-4738-8be0-46a2522c8bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030320032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1030320032
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.1808416085
Short name T614
Test name
Test status
Simulation time 3130090962 ps
CPU time 11.21 seconds
Started Jul 04 04:56:04 PM PDT 24
Finished Jul 04 04:56:16 PM PDT 24
Peak memory 226040 kb
Host smart-26ca9f62-9f60-4f4d-9009-6764a2dc5d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808416085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.1808416085
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.3368864633
Short name T692
Test name
Test status
Simulation time 1922544735 ps
CPU time 25.75 seconds
Started Jul 04 04:56:05 PM PDT 24
Finished Jul 04 04:56:31 PM PDT 24
Peak memory 250748 kb
Host smart-39ef56b5-a175-466f-902d-1f960aea3001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368864633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.3368864633
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.3682063615
Short name T881
Test name
Test status
Simulation time 2426853278 ps
CPU time 23.03 seconds
Started Jul 04 04:56:04 PM PDT 24
Finished Jul 04 04:56:27 PM PDT 24
Peak memory 340284 kb
Host smart-9fab1ae6-6a5c-4b49-af64-08a8d881b244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682063615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3682063615
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.1315135109
Short name T38
Test name
Test status
Simulation time 20509785537 ps
CPU time 551.5 seconds
Started Jul 04 04:56:05 PM PDT 24
Finished Jul 04 05:05:16 PM PDT 24
Peak memory 1768712 kb
Host smart-fdd1f3ae-795c-4186-82dc-91709731ad14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315135109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.1315135109
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.1549353145
Short name T576
Test name
Test status
Simulation time 826126569 ps
CPU time 16.05 seconds
Started Jul 04 04:56:04 PM PDT 24
Finished Jul 04 04:56:21 PM PDT 24
Peak memory 221088 kb
Host smart-41d99a78-b44b-47da-9fd6-70b498066f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549353145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1549353145
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.4085891589
Short name T1180
Test name
Test status
Simulation time 1422276696 ps
CPU time 2.19 seconds
Started Jul 04 04:56:11 PM PDT 24
Finished Jul 04 04:56:13 PM PDT 24
Peak memory 204772 kb
Host smart-2a012071-7473-467c-aebb-ce4b865eb3d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085891589 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.4085891589
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.2860330222
Short name T1070
Test name
Test status
Simulation time 999644743 ps
CPU time 0.86 seconds
Started Jul 04 04:56:13 PM PDT 24
Finished Jul 04 04:56:14 PM PDT 24
Peak memory 204504 kb
Host smart-e03a45c0-4d55-4dd0-b6a4-f79215f59900
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860330222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.2860330222
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.1966546189
Short name T933
Test name
Test status
Simulation time 465029191 ps
CPU time 1.56 seconds
Started Jul 04 04:56:11 PM PDT 24
Finished Jul 04 04:56:13 PM PDT 24
Peak memory 204652 kb
Host smart-1e60bbd9-ec9d-4ba0-9135-d1be4205da79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966546189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.1966546189
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.155625182
Short name T640
Test name
Test status
Simulation time 1019866609 ps
CPU time 2.74 seconds
Started Jul 04 04:56:12 PM PDT 24
Finished Jul 04 04:56:15 PM PDT 24
Peak memory 204692 kb
Host smart-537e6fc3-71f7-4913-875c-fc937eea0f7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155625182 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.155625182
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.2525885182
Short name T771
Test name
Test status
Simulation time 587270106 ps
CPU time 1.12 seconds
Started Jul 04 04:56:12 PM PDT 24
Finished Jul 04 04:56:13 PM PDT 24
Peak memory 204512 kb
Host smart-1b4e97a5-ccf2-43f9-bad3-71e3910f8598
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525885182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.2525885182
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.2658822755
Short name T420
Test name
Test status
Simulation time 823237232 ps
CPU time 4.89 seconds
Started Jul 04 04:56:07 PM PDT 24
Finished Jul 04 04:56:12 PM PDT 24
Peak memory 212920 kb
Host smart-68cdd904-03e1-4ab3-adfd-bc6288fd97ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658822755 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.2658822755
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.636470896
Short name T698
Test name
Test status
Simulation time 8459342330 ps
CPU time 43.38 seconds
Started Jul 04 04:56:04 PM PDT 24
Finished Jul 04 04:56:48 PM PDT 24
Peak memory 1147636 kb
Host smart-9462b7d5-4685-4ee5-8600-710d0f4a2346
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636470896 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.636470896
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.1677802643
Short name T1065
Test name
Test status
Simulation time 990884363 ps
CPU time 12.73 seconds
Started Jul 04 04:56:04 PM PDT 24
Finished Jul 04 04:56:17 PM PDT 24
Peak memory 204644 kb
Host smart-269015d9-5527-4b98-93d0-46d6bbddb5d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677802643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.1677802643
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1418785266
Short name T938
Test name
Test status
Simulation time 2008268584 ps
CPU time 21.48 seconds
Started Jul 04 04:56:03 PM PDT 24
Finished Jul 04 04:56:25 PM PDT 24
Peak memory 204728 kb
Host smart-573a2bf6-8b61-437c-8cb1-922e30b4817a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418785266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1418785266
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2455382683
Short name T16
Test name
Test status
Simulation time 63764360216 ps
CPU time 2018.43 seconds
Started Jul 04 04:56:04 PM PDT 24
Finished Jul 04 05:29:43 PM PDT 24
Peak memory 11209140 kb
Host smart-e079f2b7-220a-49e5-8a74-623088c31025
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455382683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2455382683
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.947727506
Short name T1009
Test name
Test status
Simulation time 5861589059 ps
CPU time 416.11 seconds
Started Jul 04 04:56:04 PM PDT 24
Finished Jul 04 05:03:01 PM PDT 24
Peak memory 1509200 kb
Host smart-842076b5-1896-40c1-83fe-a006af92cf51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947727506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_t
arget_stretch.947727506
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.2499451068
Short name T883
Test name
Test status
Simulation time 2749109075 ps
CPU time 6.79 seconds
Started Jul 04 04:56:04 PM PDT 24
Finished Jul 04 04:56:11 PM PDT 24
Peak memory 204888 kb
Host smart-08bc10b8-f0e1-4f59-9462-6aaaeba9f9a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499451068 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.2499451068
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.168209936
Short name T1359
Test name
Test status
Simulation time 505529866 ps
CPU time 6.99 seconds
Started Jul 04 04:56:13 PM PDT 24
Finished Jul 04 04:56:20 PM PDT 24
Peak memory 204740 kb
Host smart-0560ca95-6386-4536-a4e7-bae183337cc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168209936 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.168209936
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3826222712
Short name T1254
Test name
Test status
Simulation time 20843630 ps
CPU time 0.63 seconds
Started Jul 04 04:56:18 PM PDT 24
Finished Jul 04 04:56:18 PM PDT 24
Peak memory 204432 kb
Host smart-46684d04-213d-4428-a912-8ad33b69d078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826222712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3826222712
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1139278105
Short name T1002
Test name
Test status
Simulation time 335121387 ps
CPU time 4.89 seconds
Started Jul 04 04:56:11 PM PDT 24
Finished Jul 04 04:56:16 PM PDT 24
Peak memory 249584 kb
Host smart-ce19e1ad-2f6d-4e6c-816c-546e3cdb5bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139278105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1139278105
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.3866118769
Short name T1247
Test name
Test status
Simulation time 887233175 ps
CPU time 5.66 seconds
Started Jul 04 04:56:11 PM PDT 24
Finished Jul 04 04:56:17 PM PDT 24
Peak memory 268608 kb
Host smart-f6513bab-f6cf-4e69-9b5f-735bed164c92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866118769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.3866118769
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2415273385
Short name T1224
Test name
Test status
Simulation time 2408223732 ps
CPU time 67.84 seconds
Started Jul 04 04:56:13 PM PDT 24
Finished Jul 04 04:57:21 PM PDT 24
Peak memory 653792 kb
Host smart-2d3556d0-539c-4eaa-b7b5-d92f2e2a3623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415273385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2415273385
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.1870599088
Short name T830
Test name
Test status
Simulation time 4403417425 ps
CPU time 56.67 seconds
Started Jul 04 04:56:10 PM PDT 24
Finished Jul 04 04:57:07 PM PDT 24
Peak memory 675480 kb
Host smart-a3fdcab1-48d0-4d5b-8381-cf5fa95f4e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870599088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1870599088
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.4068856278
Short name T1418
Test name
Test status
Simulation time 442640226 ps
CPU time 0.98 seconds
Started Jul 04 04:56:12 PM PDT 24
Finished Jul 04 04:56:14 PM PDT 24
Peak memory 204348 kb
Host smart-78402279-f727-4520-a51f-822ba006bf8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068856278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.4068856278
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.944793561
Short name T990
Test name
Test status
Simulation time 2162801040 ps
CPU time 2.94 seconds
Started Jul 04 04:56:13 PM PDT 24
Finished Jul 04 04:56:16 PM PDT 24
Peak memory 204712 kb
Host smart-c716b579-8020-4de6-85b4-0c3008f84d22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944793561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.
944793561
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.1342017536
Short name T269
Test name
Test status
Simulation time 19181913916 ps
CPU time 310.05 seconds
Started Jul 04 04:56:12 PM PDT 24
Finished Jul 04 05:01:22 PM PDT 24
Peak memory 1161772 kb
Host smart-7d570cdb-a7ee-4d79-93e9-46041afc0484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342017536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.1342017536
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.3609613529
Short name T1239
Test name
Test status
Simulation time 557323148 ps
CPU time 22.14 seconds
Started Jul 04 04:56:29 PM PDT 24
Finished Jul 04 04:56:51 PM PDT 24
Peak memory 204692 kb
Host smart-b64b6227-cd69-4fcc-add1-4e6792917db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609613529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.3609613529
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.2425534205
Short name T70
Test name
Test status
Simulation time 1874253598 ps
CPU time 71.63 seconds
Started Jul 04 04:56:28 PM PDT 24
Finished Jul 04 04:57:40 PM PDT 24
Peak memory 326452 kb
Host smart-e48ba526-85ea-4d6e-996a-8a0895c60029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425534205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.2425534205
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.398079683
Short name T9
Test name
Test status
Simulation time 19815903 ps
CPU time 0.7 seconds
Started Jul 04 04:56:12 PM PDT 24
Finished Jul 04 04:56:13 PM PDT 24
Peak memory 204372 kb
Host smart-4cb1a5c0-ef97-4220-8a2f-6cbacd3495c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398079683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.398079683
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.2702478936
Short name T1406
Test name
Test status
Simulation time 7254706585 ps
CPU time 201.27 seconds
Started Jul 04 04:56:12 PM PDT 24
Finished Jul 04 04:59:33 PM PDT 24
Peak memory 904360 kb
Host smart-d0bd1383-fb6b-4869-9fd5-2217845f633e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702478936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.2702478936
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.1272001430
Short name T756
Test name
Test status
Simulation time 270057431 ps
CPU time 1.59 seconds
Started Jul 04 04:56:12 PM PDT 24
Finished Jul 04 04:56:14 PM PDT 24
Peak memory 204668 kb
Host smart-73bf1304-f3c1-4198-af70-bd58a087d806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272001430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.1272001430
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.2739925429
Short name T601
Test name
Test status
Simulation time 1706455394 ps
CPU time 33.21 seconds
Started Jul 04 04:56:11 PM PDT 24
Finished Jul 04 04:56:45 PM PDT 24
Peak memory 348224 kb
Host smart-645bdd0b-397e-4466-8935-dbf11810b9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739925429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2739925429
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.3359605205
Short name T703
Test name
Test status
Simulation time 1356630762 ps
CPU time 31.24 seconds
Started Jul 04 04:56:14 PM PDT 24
Finished Jul 04 04:56:45 PM PDT 24
Peak memory 212928 kb
Host smart-e8d5b22c-e2ee-42ed-ac1f-76bcd155b14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359605205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.3359605205
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.1115401952
Short name T963
Test name
Test status
Simulation time 808030674 ps
CPU time 4.16 seconds
Started Jul 04 04:56:19 PM PDT 24
Finished Jul 04 04:56:23 PM PDT 24
Peak memory 212888 kb
Host smart-5918c3b6-4a7e-43ec-b602-73595606ed0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115401952 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.1115401952
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.3095173532
Short name T613
Test name
Test status
Simulation time 315851717 ps
CPU time 0.91 seconds
Started Jul 04 04:56:18 PM PDT 24
Finished Jul 04 04:56:19 PM PDT 24
Peak memory 212704 kb
Host smart-d601a64e-7dba-4b96-95bc-492f775adeda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095173532 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.3095173532
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.3355451688
Short name T1226
Test name
Test status
Simulation time 249150766 ps
CPU time 0.81 seconds
Started Jul 04 04:56:17 PM PDT 24
Finished Jul 04 04:56:18 PM PDT 24
Peak memory 204520 kb
Host smart-109e7758-b936-4155-9bd2-a6f4c9cbef58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355451688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.3355451688
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.1078069700
Short name T1229
Test name
Test status
Simulation time 1328092263 ps
CPU time 2.12 seconds
Started Jul 04 04:56:29 PM PDT 24
Finished Jul 04 04:56:31 PM PDT 24
Peak memory 204648 kb
Host smart-2452cb7a-0d4e-406a-85e6-688fa7094010
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078069700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.1078069700
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.2786634604
Short name T774
Test name
Test status
Simulation time 198079863 ps
CPU time 0.87 seconds
Started Jul 04 04:56:20 PM PDT 24
Finished Jul 04 04:56:21 PM PDT 24
Peak memory 204592 kb
Host smart-b780d820-fff1-4267-8cd4-827736e9c346
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786634604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.2786634604
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3603467738
Short name T1369
Test name
Test status
Simulation time 232313750 ps
CPU time 1.92 seconds
Started Jul 04 04:56:29 PM PDT 24
Finished Jul 04 04:56:31 PM PDT 24
Peak memory 204712 kb
Host smart-1fb8764e-d01d-4fae-ae87-6d1d13c15208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603467738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3603467738
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.35923881
Short name T646
Test name
Test status
Simulation time 1886046229 ps
CPU time 9.65 seconds
Started Jul 04 04:56:17 PM PDT 24
Finished Jul 04 04:56:27 PM PDT 24
Peak memory 220968 kb
Host smart-e08f15da-cabf-4e19-a366-136e46aa5f40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35923881 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.35923881
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.2256727987
Short name T1277
Test name
Test status
Simulation time 8532553265 ps
CPU time 18.16 seconds
Started Jul 04 04:56:17 PM PDT 24
Finished Jul 04 04:56:35 PM PDT 24
Peak memory 626220 kb
Host smart-8635e206-4e57-4be4-bb52-66556334819c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256727987 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.2256727987
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.876858953
Short name T388
Test name
Test status
Simulation time 970748489 ps
CPU time 16.17 seconds
Started Jul 04 04:56:17 PM PDT 24
Finished Jul 04 04:56:33 PM PDT 24
Peak memory 204708 kb
Host smart-c8493b02-80aa-472d-9772-f4343e9b3807
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876858953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_tar
get_smoke.876858953
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.2358635850
Short name T954
Test name
Test status
Simulation time 4522940234 ps
CPU time 15.55 seconds
Started Jul 04 04:56:17 PM PDT 24
Finished Jul 04 04:56:33 PM PDT 24
Peak memory 218372 kb
Host smart-cd99f358-be02-4b44-b4c4-8da99b5a0a03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358635850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.2358635850
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.3534523397
Short name T260
Test name
Test status
Simulation time 30070334471 ps
CPU time 40.45 seconds
Started Jul 04 04:56:28 PM PDT 24
Finished Jul 04 04:57:09 PM PDT 24
Peak memory 789200 kb
Host smart-1eaddb08-3dba-4949-a4ca-dece4135ea94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534523397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.3534523397
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1083008276
Short name T172
Test name
Test status
Simulation time 8918625043 ps
CPU time 631.14 seconds
Started Jul 04 04:56:19 PM PDT 24
Finished Jul 04 05:06:50 PM PDT 24
Peak memory 1941708 kb
Host smart-4eb812f4-598b-420b-92c2-b728bc6ad7e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083008276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1083008276
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.3061480555
Short name T822
Test name
Test status
Simulation time 7550947660 ps
CPU time 7.61 seconds
Started Jul 04 04:56:22 PM PDT 24
Finished Jul 04 04:56:29 PM PDT 24
Peak memory 221156 kb
Host smart-e2017957-4b03-4abf-92d0-31a46a16af66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061480555 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.3061480555
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.2768240841
Short name T1468
Test name
Test status
Simulation time 130460790 ps
CPU time 2.7 seconds
Started Jul 04 04:56:17 PM PDT 24
Finished Jul 04 04:56:20 PM PDT 24
Peak memory 204708 kb
Host smart-51d30ca7-8c8c-4b0a-9e7c-8b7b0e9bde33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768240841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.2768240841
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3174480286
Short name T184
Test name
Test status
Simulation time 15682674 ps
CPU time 0.65 seconds
Started Jul 04 04:56:26 PM PDT 24
Finished Jul 04 04:56:27 PM PDT 24
Peak memory 204432 kb
Host smart-376218b9-698d-4812-a6ff-22f66112b761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174480286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3174480286
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.600806777
Short name T1370
Test name
Test status
Simulation time 215794822 ps
CPU time 1.74 seconds
Started Jul 04 04:56:25 PM PDT 24
Finished Jul 04 04:56:27 PM PDT 24
Peak memory 213012 kb
Host smart-58b480f5-ba6a-4361-a6e9-07371bbf64af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600806777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.600806777
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.2401044187
Short name T856
Test name
Test status
Simulation time 589449472 ps
CPU time 5.36 seconds
Started Jul 04 04:56:18 PM PDT 24
Finished Jul 04 04:56:23 PM PDT 24
Peak memory 262752 kb
Host smart-e839dc7d-638c-4d77-91ba-3d4a23cebd3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401044187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.2401044187
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.396310915
Short name T84
Test name
Test status
Simulation time 2295333953 ps
CPU time 160.43 seconds
Started Jul 04 04:56:21 PM PDT 24
Finished Jul 04 04:59:02 PM PDT 24
Peak memory 773640 kb
Host smart-36ac7284-83ed-48f6-94ef-24654ed3d1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396310915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.396310915
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.506780096
Short name T867
Test name
Test status
Simulation time 4532881095 ps
CPU time 45.61 seconds
Started Jul 04 04:56:19 PM PDT 24
Finished Jul 04 04:57:05 PM PDT 24
Peak memory 521468 kb
Host smart-b944329e-a3d6-4524-a639-b18940d42342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506780096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.506780096
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.2751490123
Short name T501
Test name
Test status
Simulation time 120710574 ps
CPU time 0.82 seconds
Started Jul 04 04:56:17 PM PDT 24
Finished Jul 04 04:56:18 PM PDT 24
Peak memory 204432 kb
Host smart-60fd61d9-af2a-415f-a46f-b8e0571b5f96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751490123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.2751490123
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.1251646408
Short name T171
Test name
Test status
Simulation time 462242432 ps
CPU time 2.84 seconds
Started Jul 04 04:56:29 PM PDT 24
Finished Jul 04 04:56:32 PM PDT 24
Peak memory 204664 kb
Host smart-aae78ab1-a1b3-45a1-9768-217efc561444
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251646408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.1251646408
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.4291137026
Short name T649
Test name
Test status
Simulation time 15759847912 ps
CPU time 264.17 seconds
Started Jul 04 04:56:18 PM PDT 24
Finished Jul 04 05:00:42 PM PDT 24
Peak memory 1148244 kb
Host smart-3ab78ac4-5946-4341-97e8-afa327cf0017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291137026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.4291137026
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.1300610086
Short name T140
Test name
Test status
Simulation time 1019685107 ps
CPU time 6.4 seconds
Started Jul 04 04:56:25 PM PDT 24
Finished Jul 04 04:56:32 PM PDT 24
Peak memory 204796 kb
Host smart-3b7d1246-8513-4887-8554-ed989e87b463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300610086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.1300610086
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.324192576
Short name T506
Test name
Test status
Simulation time 6252401595 ps
CPU time 66.3 seconds
Started Jul 04 04:56:25 PM PDT 24
Finished Jul 04 04:57:32 PM PDT 24
Peak memory 334332 kb
Host smart-1a9a468d-cfc0-4919-9874-8828a2a6a512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324192576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.324192576
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.2185369533
Short name T1471
Test name
Test status
Simulation time 40156235 ps
CPU time 0.66 seconds
Started Jul 04 04:56:19 PM PDT 24
Finished Jul 04 04:56:20 PM PDT 24
Peak memory 204384 kb
Host smart-984005a5-345c-415c-a305-bcb176e0d944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185369533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2185369533
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3461519277
Short name T65
Test name
Test status
Simulation time 7553071735 ps
CPU time 301.09 seconds
Started Jul 04 04:56:24 PM PDT 24
Finished Jul 04 05:01:25 PM PDT 24
Peak memory 213048 kb
Host smart-c0042b95-2c0a-490b-92af-bb049d9ed737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461519277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3461519277
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.529059030
Short name T561
Test name
Test status
Simulation time 102829785 ps
CPU time 1.57 seconds
Started Jul 04 04:56:28 PM PDT 24
Finished Jul 04 04:56:30 PM PDT 24
Peak memory 222500 kb
Host smart-08a1f138-2bdd-4046-ac3d-baf3cdf64d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529059030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.529059030
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3582198781
Short name T1088
Test name
Test status
Simulation time 2124035697 ps
CPU time 35.7 seconds
Started Jul 04 04:56:19 PM PDT 24
Finished Jul 04 04:56:54 PM PDT 24
Peak memory 365864 kb
Host smart-2bcf8c4a-1ec7-4b8e-a60a-98b3df1c6964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582198781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3582198781
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.1375556415
Short name T1051
Test name
Test status
Simulation time 15260060202 ps
CPU time 621.12 seconds
Started Jul 04 04:56:26 PM PDT 24
Finished Jul 04 05:06:47 PM PDT 24
Peak memory 1754268 kb
Host smart-81ff1d67-bad5-4e59-82e0-0ef365417824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375556415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.1375556415
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.140848414
Short name T276
Test name
Test status
Simulation time 3398775861 ps
CPU time 10.38 seconds
Started Jul 04 04:56:23 PM PDT 24
Finished Jul 04 04:56:33 PM PDT 24
Peak memory 212880 kb
Host smart-835c0782-79f2-4109-a08e-71916b3c8304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140848414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.140848414
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.1494326193
Short name T167
Test name
Test status
Simulation time 1014172789 ps
CPU time 5.23 seconds
Started Jul 04 04:56:25 PM PDT 24
Finished Jul 04 04:56:31 PM PDT 24
Peak memory 212908 kb
Host smart-86bc6033-704d-436f-8b22-a78bfffcd9f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494326193 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.1494326193
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2491962206
Short name T1481
Test name
Test status
Simulation time 391450066 ps
CPU time 0.85 seconds
Started Jul 04 04:56:26 PM PDT 24
Finished Jul 04 04:56:27 PM PDT 24
Peak memory 212716 kb
Host smart-c454fdcb-c038-4cc6-8e8e-454dec8da0ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491962206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2491962206
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.1412928809
Short name T376
Test name
Test status
Simulation time 459500954 ps
CPU time 1.07 seconds
Started Jul 04 04:56:28 PM PDT 24
Finished Jul 04 04:56:29 PM PDT 24
Peak memory 204452 kb
Host smart-e0d09fe2-a7e1-4720-8913-4ade37163cfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412928809 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.1412928809
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.3703382344
Short name T164
Test name
Test status
Simulation time 475389839 ps
CPU time 2.81 seconds
Started Jul 04 04:56:26 PM PDT 24
Finished Jul 04 04:56:29 PM PDT 24
Peak memory 204700 kb
Host smart-ddd888ea-4cb7-492c-99ce-367f020fc69c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703382344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.3703382344
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.2612565107
Short name T943
Test name
Test status
Simulation time 510636913 ps
CPU time 1.18 seconds
Started Jul 04 04:56:27 PM PDT 24
Finished Jul 04 04:56:28 PM PDT 24
Peak memory 204476 kb
Host smart-e8efba67-c2ed-43c0-8e82-166e7da38766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612565107 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.2612565107
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3743986046
Short name T98
Test name
Test status
Simulation time 778180969 ps
CPU time 3.06 seconds
Started Jul 04 04:56:25 PM PDT 24
Finished Jul 04 04:56:28 PM PDT 24
Peak memory 204692 kb
Host smart-614e71dc-f7fe-484c-ba90-bd4482f77e81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743986046 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3743986046
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.4046625536
Short name T1283
Test name
Test status
Simulation time 1756689865 ps
CPU time 4.26 seconds
Started Jul 04 04:56:25 PM PDT 24
Finished Jul 04 04:56:29 PM PDT 24
Peak memory 205096 kb
Host smart-0ff31c00-d4b6-43fb-a2e8-153f314e4672
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046625536 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.4046625536
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.952418916
Short name T740
Test name
Test status
Simulation time 20260685359 ps
CPU time 49.46 seconds
Started Jul 04 04:56:25 PM PDT 24
Finished Jul 04 04:57:15 PM PDT 24
Peak memory 1163512 kb
Host smart-09009932-c6ca-4879-ac69-37c8f0dee371
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952418916 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.952418916
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.746133335
Short name T492
Test name
Test status
Simulation time 2585490241 ps
CPU time 7.94 seconds
Started Jul 04 04:56:25 PM PDT 24
Finished Jul 04 04:56:33 PM PDT 24
Peak memory 204692 kb
Host smart-6503527b-b187-4d1f-bffa-76d8f473c6bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746133335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_tar
get_smoke.746133335
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.1097685859
Short name T244
Test name
Test status
Simulation time 3474147091 ps
CPU time 31.99 seconds
Started Jul 04 04:56:28 PM PDT 24
Finished Jul 04 04:57:00 PM PDT 24
Peak memory 226684 kb
Host smart-ea1f7b1b-f93c-483e-bdc7-d9dc0684327f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097685859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.1097685859
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.1732045368
Short name T1069
Test name
Test status
Simulation time 69523039781 ps
CPU time 1940.04 seconds
Started Jul 04 04:56:27 PM PDT 24
Finished Jul 04 05:28:47 PM PDT 24
Peak memory 9941120 kb
Host smart-24a9ef6a-c814-47e6-9eaa-ae7611552010
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732045368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.1732045368
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1831076628
Short name T361
Test name
Test status
Simulation time 38626554813 ps
CPU time 3160.01 seconds
Started Jul 04 04:56:26 PM PDT 24
Finished Jul 04 05:49:07 PM PDT 24
Peak memory 9177040 kb
Host smart-68dbf00f-5a6f-4e5b-a3cf-f8c701dc610a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831076628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1831076628
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1793373162
Short name T1163
Test name
Test status
Simulation time 1147176337 ps
CPU time 6.95 seconds
Started Jul 04 04:56:25 PM PDT 24
Finished Jul 04 04:56:32 PM PDT 24
Peak memory 216420 kb
Host smart-4b99e651-6aea-4d94-a757-e87ba7f9822b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793373162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1793373162
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.1868424899
Short name T377
Test name
Test status
Simulation time 292515294 ps
CPU time 4.05 seconds
Started Jul 04 04:56:25 PM PDT 24
Finished Jul 04 04:56:30 PM PDT 24
Peak memory 204716 kb
Host smart-19dcdaa8-1e39-4110-ab77-1afd85d2fb83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868424899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.1868424899
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.2715393105
Short name T1090
Test name
Test status
Simulation time 17199903 ps
CPU time 0.62 seconds
Started Jul 04 04:56:32 PM PDT 24
Finished Jul 04 04:56:33 PM PDT 24
Peak memory 204352 kb
Host smart-5578c628-40b9-4274-871e-e98463d17550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715393105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2715393105
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3627282610
Short name T422
Test name
Test status
Simulation time 307533661 ps
CPU time 1.7 seconds
Started Jul 04 04:56:33 PM PDT 24
Finished Jul 04 04:56:35 PM PDT 24
Peak memory 221128 kb
Host smart-e5e5555b-17c5-4d32-9eb2-d8e80d07cae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627282610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3627282610
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3126840939
Short name T861
Test name
Test status
Simulation time 466232443 ps
CPU time 9.26 seconds
Started Jul 04 04:56:25 PM PDT 24
Finished Jul 04 04:56:34 PM PDT 24
Peak memory 283344 kb
Host smart-c089e969-fac7-411c-81a7-07267728b230
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126840939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3126840939
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.4120763872
Short name T444
Test name
Test status
Simulation time 11066693347 ps
CPU time 86.72 seconds
Started Jul 04 04:56:26 PM PDT 24
Finished Jul 04 04:57:53 PM PDT 24
Peak memory 840572 kb
Host smart-c3242a77-9c8d-4365-9fb0-9bf7880b92e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120763872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.4120763872
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.3550788498
Short name T1268
Test name
Test status
Simulation time 22959561188 ps
CPU time 180.03 seconds
Started Jul 04 04:56:26 PM PDT 24
Finished Jul 04 04:59:26 PM PDT 24
Peak memory 749304 kb
Host smart-9d001c6f-2006-466b-90ed-8279d43a1021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550788498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3550788498
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.264418006
Short name T443
Test name
Test status
Simulation time 463842651 ps
CPU time 1.04 seconds
Started Jul 04 04:56:27 PM PDT 24
Finished Jul 04 04:56:28 PM PDT 24
Peak memory 204324 kb
Host smart-dc3d99f4-bde8-4137-8fa3-76e0ee8b0aae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264418006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fm
t.264418006
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.833518217
Short name T348
Test name
Test status
Simulation time 155860124 ps
CPU time 7.7 seconds
Started Jul 04 04:56:26 PM PDT 24
Finished Jul 04 04:56:34 PM PDT 24
Peak memory 204708 kb
Host smart-4e4fd4f3-dd37-41bd-bee7-b4e9afa58a72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833518217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.
833518217
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.215502381
Short name T1099
Test name
Test status
Simulation time 17123380424 ps
CPU time 117.25 seconds
Started Jul 04 04:56:24 PM PDT 24
Finished Jul 04 04:58:21 PM PDT 24
Peak memory 1156312 kb
Host smart-ce048818-1342-499e-8499-b44a213d0015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215502381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.215502381
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.3447367705
Short name T809
Test name
Test status
Simulation time 678881734 ps
CPU time 28.37 seconds
Started Jul 04 04:56:31 PM PDT 24
Finished Jul 04 04:56:59 PM PDT 24
Peak memory 204672 kb
Host smart-bf768d8c-612e-41a4-baa1-7ff79f2023e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447367705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.3447367705
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.2600106718
Short name T250
Test name
Test status
Simulation time 1725136697 ps
CPU time 32.64 seconds
Started Jul 04 04:56:30 PM PDT 24
Finished Jul 04 04:57:03 PM PDT 24
Peak memory 348476 kb
Host smart-a48a8b8f-6b5c-44e0-85ca-be37499b3233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600106718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.2600106718
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_perf.771977731
Short name T1493
Test name
Test status
Simulation time 1637808737 ps
CPU time 65.42 seconds
Started Jul 04 04:56:33 PM PDT 24
Finished Jul 04 04:57:39 PM PDT 24
Peak memory 204720 kb
Host smart-0bbda8b9-f691-4074-98c0-18cca128fc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771977731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.771977731
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.3687349737
Short name T406
Test name
Test status
Simulation time 267170608 ps
CPU time 1.28 seconds
Started Jul 04 04:56:34 PM PDT 24
Finished Jul 04 04:56:35 PM PDT 24
Peak memory 204540 kb
Host smart-87abdcd1-6d00-4b2c-b36e-39ce413cb90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687349737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.3687349737
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.1839492059
Short name T787
Test name
Test status
Simulation time 6683620729 ps
CPU time 70.11 seconds
Started Jul 04 04:56:22 PM PDT 24
Finished Jul 04 04:57:33 PM PDT 24
Peak memory 327116 kb
Host smart-cef5c74f-6115-438d-815c-cd64217bc1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839492059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.1839492059
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.2746849959
Short name T1319
Test name
Test status
Simulation time 34175265018 ps
CPU time 737 seconds
Started Jul 04 04:56:34 PM PDT 24
Finished Jul 04 05:08:51 PM PDT 24
Peak memory 1972228 kb
Host smart-224ad259-067c-48c0-9109-946354df19ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746849959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.2746849959
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.834083850
Short name T382
Test name
Test status
Simulation time 940108299 ps
CPU time 17.45 seconds
Started Jul 04 04:56:32 PM PDT 24
Finished Jul 04 04:56:49 PM PDT 24
Peak memory 220812 kb
Host smart-b0d95efb-963a-494e-a6da-447e2e073708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834083850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.834083850
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.99634954
Short name T1399
Test name
Test status
Simulation time 1808427617 ps
CPU time 4.85 seconds
Started Jul 04 04:56:32 PM PDT 24
Finished Jul 04 04:56:37 PM PDT 24
Peak memory 213100 kb
Host smart-59ae463b-e16c-4c7c-b6d7-5fc907f9b8cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99634954 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_bad_addr.99634954
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.2717020143
Short name T955
Test name
Test status
Simulation time 610297953 ps
CPU time 1.31 seconds
Started Jul 04 04:56:31 PM PDT 24
Finished Jul 04 04:56:33 PM PDT 24
Peak memory 204700 kb
Host smart-5b8509fa-bc17-43ef-bf1d-02c913a043c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717020143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.2717020143
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.3316065324
Short name T14
Test name
Test status
Simulation time 571589797 ps
CPU time 1.22 seconds
Started Jul 04 04:56:32 PM PDT 24
Finished Jul 04 04:56:33 PM PDT 24
Peak memory 205080 kb
Host smart-6e4e387b-feb4-44f8-871c-6f39b88b1f5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316065324 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.3316065324
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.169853037
Short name T1288
Test name
Test status
Simulation time 462511137 ps
CPU time 2.46 seconds
Started Jul 04 04:56:31 PM PDT 24
Finished Jul 04 04:56:34 PM PDT 24
Peak memory 204708 kb
Host smart-00d48eb1-4ae0-4c06-9d54-293549e09389
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169853037 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.169853037
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.3439375839
Short name T911
Test name
Test status
Simulation time 113226828 ps
CPU time 1.16 seconds
Started Jul 04 04:56:31 PM PDT 24
Finished Jul 04 04:56:33 PM PDT 24
Peak memory 204460 kb
Host smart-c59b5b56-1be3-4b7d-a281-c256ddc5bdef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439375839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.3439375839
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.916109935
Short name T1480
Test name
Test status
Simulation time 818146454 ps
CPU time 3.21 seconds
Started Jul 04 04:56:32 PM PDT 24
Finished Jul 04 04:56:35 PM PDT 24
Peak memory 204704 kb
Host smart-da59a8f5-a1a9-4fae-9d3c-a39c86f789dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916109935 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.i2c_target_hrst.916109935
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.197401164
Short name T562
Test name
Test status
Simulation time 1050812944 ps
CPU time 5.61 seconds
Started Jul 04 04:56:33 PM PDT 24
Finished Jul 04 04:56:39 PM PDT 24
Peak memory 218304 kb
Host smart-7f953803-0680-4716-a1a1-18d39bc825e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197401164 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_intr_smoke.197401164
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.160909955
Short name T896
Test name
Test status
Simulation time 17276382135 ps
CPU time 334.53 seconds
Started Jul 04 04:56:31 PM PDT 24
Finished Jul 04 05:02:06 PM PDT 24
Peak memory 4304556 kb
Host smart-f65f6ecc-af3c-4a55-b83e-8f0e191a6045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160909955 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.160909955
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.3128158954
Short name T395
Test name
Test status
Simulation time 2649190029 ps
CPU time 22.26 seconds
Started Jul 04 04:56:30 PM PDT 24
Finished Jul 04 04:56:53 PM PDT 24
Peak memory 204684 kb
Host smart-ec04b8c4-6daf-48cd-9e3e-3bcd7a19e7ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128158954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.3128158954
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.402584951
Short name T1413
Test name
Test status
Simulation time 2758948952 ps
CPU time 21.68 seconds
Started Jul 04 04:56:30 PM PDT 24
Finished Jul 04 04:56:52 PM PDT 24
Peak memory 228332 kb
Host smart-f90cb36a-3567-4e4d-90c0-e98759cecbdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402584951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_rd.402584951
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.4057245418
Short name T246
Test name
Test status
Simulation time 13544786062 ps
CPU time 12.82 seconds
Started Jul 04 04:56:32 PM PDT 24
Finished Jul 04 04:56:45 PM PDT 24
Peak memory 204856 kb
Host smart-f94bdc68-d015-4d2f-8afe-b4b9bd10a9e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057245418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.4057245418
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.1556540930
Short name T466
Test name
Test status
Simulation time 22492419752 ps
CPU time 1096.44 seconds
Started Jul 04 04:56:31 PM PDT 24
Finished Jul 04 05:14:49 PM PDT 24
Peak memory 5385736 kb
Host smart-e1e8e04c-d235-4cde-b262-dbe73b728f12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556540930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.1556540930
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.315791217
Short name T1320
Test name
Test status
Simulation time 5579244079 ps
CPU time 6.89 seconds
Started Jul 04 04:56:31 PM PDT 24
Finished Jul 04 04:56:38 PM PDT 24
Peak memory 212964 kb
Host smart-9c8fb223-4775-440f-85df-44789cf5e870
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315791217 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.315791217
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.3314874726
Short name T1295
Test name
Test status
Simulation time 137466288 ps
CPU time 2.85 seconds
Started Jul 04 04:56:31 PM PDT 24
Finished Jul 04 04:56:35 PM PDT 24
Peak memory 204676 kb
Host smart-296703e2-0f82-4c8d-88f8-18798da3b14a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314874726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.3314874726
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2777529469
Short name T736
Test name
Test status
Simulation time 15753716 ps
CPU time 0.62 seconds
Started Jul 04 04:56:46 PM PDT 24
Finished Jul 04 04:56:47 PM PDT 24
Peak memory 204220 kb
Host smart-8cbf0be6-90c3-475d-8c41-5befc1117c19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777529469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2777529469
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.2491434651
Short name T572
Test name
Test status
Simulation time 173795497 ps
CPU time 1.39 seconds
Started Jul 04 04:56:38 PM PDT 24
Finished Jul 04 04:56:40 PM PDT 24
Peak memory 213020 kb
Host smart-a65ee5ec-f903-4010-8cae-d6ca1c07eef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491434651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.2491434651
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1237060688
Short name T684
Test name
Test status
Simulation time 362614971 ps
CPU time 7.29 seconds
Started Jul 04 04:56:39 PM PDT 24
Finished Jul 04 04:56:47 PM PDT 24
Peak memory 285004 kb
Host smart-5cff84c8-9c70-467b-8c72-4019e1e39e6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237060688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1237060688
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.2469731453
Short name T850
Test name
Test status
Simulation time 1723118424 ps
CPU time 87.85 seconds
Started Jul 04 04:56:39 PM PDT 24
Finished Jul 04 04:58:07 PM PDT 24
Peak memory 290816 kb
Host smart-b5e54378-f92b-4e2c-bcf9-7d6d1f094528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469731453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2469731453
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.4162363539
Short name T1502
Test name
Test status
Simulation time 6577012383 ps
CPU time 185.18 seconds
Started Jul 04 04:56:37 PM PDT 24
Finished Jul 04 04:59:42 PM PDT 24
Peak memory 795632 kb
Host smart-5ec87da9-45b5-49b9-9613-8de48889dfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162363539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.4162363539
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.2481792637
Short name T1043
Test name
Test status
Simulation time 189193020 ps
CPU time 0.95 seconds
Started Jul 04 04:56:39 PM PDT 24
Finished Jul 04 04:56:40 PM PDT 24
Peak memory 204280 kb
Host smart-ff99d29b-c4aa-414c-8bfc-336f45de04fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481792637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.2481792637
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3803218247
Short name T1305
Test name
Test status
Simulation time 168459655 ps
CPU time 3.95 seconds
Started Jul 04 04:56:38 PM PDT 24
Finished Jul 04 04:56:42 PM PDT 24
Peak memory 204660 kb
Host smart-0d37c5f9-4629-4f31-9add-f0ab8df23d6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803218247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3803218247
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1672632421
Short name T1035
Test name
Test status
Simulation time 10742831881 ps
CPU time 169.96 seconds
Started Jul 04 04:56:39 PM PDT 24
Finished Jul 04 04:59:29 PM PDT 24
Peak memory 1489356 kb
Host smart-658945f8-75ef-4ab1-9c88-3a2daf34c5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672632421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1672632421
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.3764044098
Short name T563
Test name
Test status
Simulation time 1065038953 ps
CPU time 21.24 seconds
Started Jul 04 04:56:39 PM PDT 24
Finished Jul 04 04:57:01 PM PDT 24
Peak memory 204660 kb
Host smart-57c09dd9-2f58-4081-8f82-4903158f19cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764044098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.3764044098
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.3340359059
Short name T616
Test name
Test status
Simulation time 1238871047 ps
CPU time 17.98 seconds
Started Jul 04 04:56:38 PM PDT 24
Finished Jul 04 04:56:57 PM PDT 24
Peak memory 281996 kb
Host smart-e70a6431-3121-4b9a-9c3f-f1b64cb8e2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340359059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3340359059
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.2142888706
Short name T1512
Test name
Test status
Simulation time 38002202 ps
CPU time 0.68 seconds
Started Jul 04 04:56:33 PM PDT 24
Finished Jul 04 04:56:33 PM PDT 24
Peak memory 204356 kb
Host smart-d281dd87-0793-4df2-a3db-d74989b916f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142888706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2142888706
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.365057428
Short name T958
Test name
Test status
Simulation time 5499679170 ps
CPU time 432.25 seconds
Started Jul 04 04:56:39 PM PDT 24
Finished Jul 04 05:03:52 PM PDT 24
Peak memory 1314216 kb
Host smart-03629f43-6a94-44a8-b52a-edd5b1853a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365057428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.365057428
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.3314933528
Short name T1177
Test name
Test status
Simulation time 148553613 ps
CPU time 1.02 seconds
Started Jul 04 04:56:40 PM PDT 24
Finished Jul 04 04:56:41 PM PDT 24
Peak memory 204984 kb
Host smart-4c5a9223-b0cf-4f4a-bfc4-f6acd0e7f433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314933528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.3314933528
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.2957346531
Short name T892
Test name
Test status
Simulation time 2353084860 ps
CPU time 21.18 seconds
Started Jul 04 04:56:32 PM PDT 24
Finished Jul 04 04:56:54 PM PDT 24
Peak memory 294116 kb
Host smart-6575dd05-2318-4c15-b1f4-2b08e7287067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957346531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.2957346531
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.1192304879
Short name T1007
Test name
Test status
Simulation time 16131342090 ps
CPU time 1147.65 seconds
Started Jul 04 04:56:38 PM PDT 24
Finished Jul 04 05:15:46 PM PDT 24
Peak memory 3689516 kb
Host smart-ef8b0792-588d-46b7-a0d8-cd5cf4f142d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192304879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.1192304879
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.178619064
Short name T929
Test name
Test status
Simulation time 531849004 ps
CPU time 9.87 seconds
Started Jul 04 04:56:39 PM PDT 24
Finished Jul 04 04:56:49 PM PDT 24
Peak memory 212948 kb
Host smart-3f2b914a-cb42-4a4b-9960-9766a5b083d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178619064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.178619064
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.965844299
Short name T1456
Test name
Test status
Simulation time 3421717631 ps
CPU time 3.09 seconds
Started Jul 04 04:56:38 PM PDT 24
Finished Jul 04 04:56:41 PM PDT 24
Peak memory 204820 kb
Host smart-c62ad41d-69f7-474e-a419-826a7fad36c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965844299 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.965844299
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.765312944
Short name T1
Test name
Test status
Simulation time 323450580 ps
CPU time 1.01 seconds
Started Jul 04 04:56:37 PM PDT 24
Finished Jul 04 04:56:39 PM PDT 24
Peak memory 204524 kb
Host smart-6d079836-889d-455f-af8e-865a9b362388
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765312944 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_acq.765312944
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.2901120124
Short name T791
Test name
Test status
Simulation time 188086941 ps
CPU time 1.21 seconds
Started Jul 04 04:56:36 PM PDT 24
Finished Jul 04 04:56:38 PM PDT 24
Peak memory 204712 kb
Host smart-b2f6a78d-7a5c-420b-a171-e99d13455fd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901120124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.2901120124
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.2884873141
Short name T255
Test name
Test status
Simulation time 574802119 ps
CPU time 2.52 seconds
Started Jul 04 04:56:45 PM PDT 24
Finished Jul 04 04:56:48 PM PDT 24
Peak memory 204684 kb
Host smart-631d9034-c62d-4cde-9a3c-f9051072cacf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884873141 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.2884873141
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.3352395160
Short name T617
Test name
Test status
Simulation time 282648798 ps
CPU time 1.22 seconds
Started Jul 04 04:56:47 PM PDT 24
Finished Jul 04 04:56:48 PM PDT 24
Peak memory 204448 kb
Host smart-e5eed945-6b15-4dd9-a2da-ca5d70f33877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352395160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.3352395160
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.3768636772
Short name T263
Test name
Test status
Simulation time 918680031 ps
CPU time 4.96 seconds
Started Jul 04 04:56:37 PM PDT 24
Finished Jul 04 04:56:42 PM PDT 24
Peak memory 204704 kb
Host smart-31396515-2f81-4ed9-8a5f-f3518f919889
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768636772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.3768636772
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.3315331713
Short name T324
Test name
Test status
Simulation time 1154052374 ps
CPU time 5.92 seconds
Started Jul 04 04:56:39 PM PDT 24
Finished Jul 04 04:56:45 PM PDT 24
Peak memory 212916 kb
Host smart-ccaa69ed-18d5-49d4-9a66-43ac9a7c79eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315331713 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.3315331713
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.2693973387
Short name T1029
Test name
Test status
Simulation time 18862512802 ps
CPU time 278.14 seconds
Started Jul 04 04:56:39 PM PDT 24
Finished Jul 04 05:01:18 PM PDT 24
Peak memory 3032328 kb
Host smart-7ba6b561-da77-4f54-be5c-70d381696eaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693973387 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.2693973387
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.1957481765
Short name T685
Test name
Test status
Simulation time 4841120406 ps
CPU time 20 seconds
Started Jul 04 04:56:39 PM PDT 24
Finished Jul 04 04:56:59 PM PDT 24
Peak memory 204864 kb
Host smart-b58ab0ab-5594-4499-b0e9-fae3780c61dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957481765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.1957481765
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.2078427776
Short name T1394
Test name
Test status
Simulation time 7196912555 ps
CPU time 71.9 seconds
Started Jul 04 04:56:38 PM PDT 24
Finished Jul 04 04:57:51 PM PDT 24
Peak memory 209680 kb
Host smart-90cba9b2-9391-4e59-8f20-cf2fd979d614
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078427776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.2078427776
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.3022637472
Short name T23
Test name
Test status
Simulation time 40722877767 ps
CPU time 34.15 seconds
Started Jul 04 04:56:39 PM PDT 24
Finished Jul 04 04:57:14 PM PDT 24
Peak memory 670496 kb
Host smart-9e61fd3f-f2f3-4515-b4a2-cdd3dba4adbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022637472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.3022637472
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2891428822
Short name T657
Test name
Test status
Simulation time 4568215240 ps
CPU time 265.9 seconds
Started Jul 04 04:56:39 PM PDT 24
Finished Jul 04 05:01:05 PM PDT 24
Peak memory 1150784 kb
Host smart-d0eb68d4-8792-4d59-ac6a-6455c40cf282
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891428822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2891428822
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.455161761
Short name T965
Test name
Test status
Simulation time 10496097648 ps
CPU time 7.2 seconds
Started Jul 04 04:56:38 PM PDT 24
Finished Jul 04 04:56:46 PM PDT 24
Peak memory 204972 kb
Host smart-3cdacae6-0864-42ae-ac8c-83dd2a1f962b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455161761 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_timeout.455161761
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.2243998476
Short name T1401
Test name
Test status
Simulation time 107724637 ps
CPU time 2.3 seconds
Started Jul 04 04:56:44 PM PDT 24
Finished Jul 04 04:56:47 PM PDT 24
Peak memory 204716 kb
Host smart-4e8c2d3d-95c5-4b8a-977a-fbfd6468fad9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243998476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.2243998476
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2866220141
Short name T1232
Test name
Test status
Simulation time 15181557 ps
CPU time 0.66 seconds
Started Jul 04 04:56:50 PM PDT 24
Finished Jul 04 04:56:51 PM PDT 24
Peak memory 204300 kb
Host smart-0319b80f-97cf-4d54-8aea-9917ea880b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866220141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2866220141
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.813970063
Short name T42
Test name
Test status
Simulation time 101467066 ps
CPU time 1.63 seconds
Started Jul 04 04:56:47 PM PDT 24
Finished Jul 04 04:56:49 PM PDT 24
Peak memory 221144 kb
Host smart-f0c89bc1-9f78-4e50-8a2c-064f38a0dcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813970063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.813970063
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.1461736710
Short name T1206
Test name
Test status
Simulation time 457222220 ps
CPU time 10.31 seconds
Started Jul 04 04:56:44 PM PDT 24
Finished Jul 04 04:56:55 PM PDT 24
Peak memory 306172 kb
Host smart-5e08efa0-4e51-4ab7-b218-03a3698a8a8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461736710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.1461736710
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2264123497
Short name T1271
Test name
Test status
Simulation time 3190274882 ps
CPU time 46.89 seconds
Started Jul 04 04:56:45 PM PDT 24
Finished Jul 04 04:57:32 PM PDT 24
Peak memory 601228 kb
Host smart-0657fd0d-3d8a-475f-afb6-76f22e936d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264123497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2264123497
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.667656809
Short name T734
Test name
Test status
Simulation time 5983839482 ps
CPU time 39.29 seconds
Started Jul 04 04:56:47 PM PDT 24
Finished Jul 04 04:57:26 PM PDT 24
Peak memory 564976 kb
Host smart-76eeaa96-36bf-40c6-b93f-fb2d291a51d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667656809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.667656809
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.2866118151
Short name T746
Test name
Test status
Simulation time 225015461 ps
CPU time 0.98 seconds
Started Jul 04 04:56:45 PM PDT 24
Finished Jul 04 04:56:47 PM PDT 24
Peak memory 204292 kb
Host smart-d2edd172-efd6-4f8d-8717-12c0db5f7ca6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866118151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.2866118151
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.4130542268
Short name T875
Test name
Test status
Simulation time 322256011 ps
CPU time 3.4 seconds
Started Jul 04 04:56:48 PM PDT 24
Finished Jul 04 04:56:52 PM PDT 24
Peak memory 204752 kb
Host smart-b6458839-de46-41d7-94d3-e8be195ffdbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130542268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.4130542268
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.229167196
Short name T1291
Test name
Test status
Simulation time 2913792275 ps
CPU time 63.4 seconds
Started Jul 04 04:56:45 PM PDT 24
Finished Jul 04 04:57:49 PM PDT 24
Peak memory 921324 kb
Host smart-7ae7e8fa-e7d1-4a1f-b8d7-7bcf6bce3d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229167196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.229167196
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.3980695626
Short name T1357
Test name
Test status
Simulation time 2310995232 ps
CPU time 25.6 seconds
Started Jul 04 04:56:50 PM PDT 24
Finished Jul 04 04:57:16 PM PDT 24
Peak memory 204804 kb
Host smart-872b0af9-5221-4a29-864d-dd0a4ce72c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980695626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.3980695626
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.2750249229
Short name T580
Test name
Test status
Simulation time 996842947 ps
CPU time 14.54 seconds
Started Jul 04 04:56:53 PM PDT 24
Finished Jul 04 04:57:08 PM PDT 24
Peak memory 281840 kb
Host smart-0d7f286d-b6b6-4222-b730-6d429bf7922b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750249229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.2750249229
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.4103360370
Short name T777
Test name
Test status
Simulation time 20155441 ps
CPU time 0.7 seconds
Started Jul 04 04:56:46 PM PDT 24
Finished Jul 04 04:56:47 PM PDT 24
Peak memory 204416 kb
Host smart-e9b48fef-a3b3-4155-a45d-d498ddbf3752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103360370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.4103360370
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.894065135
Short name T1041
Test name
Test status
Simulation time 50736006994 ps
CPU time 1789.89 seconds
Started Jul 04 04:56:46 PM PDT 24
Finished Jul 04 05:26:36 PM PDT 24
Peak memory 204932 kb
Host smart-46c5e92a-0279-4f89-8a06-f03fdc1242e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894065135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.894065135
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.3853747722
Short name T748
Test name
Test status
Simulation time 613988646 ps
CPU time 24.7 seconds
Started Jul 04 04:56:46 PM PDT 24
Finished Jul 04 04:57:11 PM PDT 24
Peak memory 204552 kb
Host smart-9879d673-77cc-4bad-b4a2-e87eb8bbf865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853747722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.3853747722
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.836481954
Short name T1172
Test name
Test status
Simulation time 1944567021 ps
CPU time 96.02 seconds
Started Jul 04 04:56:46 PM PDT 24
Finished Jul 04 04:58:22 PM PDT 24
Peak memory 426416 kb
Host smart-dba0d858-5fc7-47b3-85ba-4cd20ec08462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836481954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.836481954
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.2893087521
Short name T1344
Test name
Test status
Simulation time 1529125963 ps
CPU time 11.78 seconds
Started Jul 04 04:56:44 PM PDT 24
Finished Jul 04 04:56:56 PM PDT 24
Peak memory 221072 kb
Host smart-0d6defa1-8d4f-441b-ba0b-0d424b98a6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893087521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.2893087521
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2880039631
Short name T1242
Test name
Test status
Simulation time 958084647 ps
CPU time 3.03 seconds
Started Jul 04 04:56:51 PM PDT 24
Finished Jul 04 04:56:55 PM PDT 24
Peak memory 204716 kb
Host smart-f59f64e0-e1dd-41ec-88ae-54597a084ea9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880039631 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2880039631
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.2685231333
Short name T807
Test name
Test status
Simulation time 197718612 ps
CPU time 0.94 seconds
Started Jul 04 04:56:45 PM PDT 24
Finished Jul 04 04:56:47 PM PDT 24
Peak memory 204512 kb
Host smart-3b002519-40d8-43f9-a3ec-6d69d626172c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685231333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.2685231333
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.4229684872
Short name T704
Test name
Test status
Simulation time 618829631 ps
CPU time 1.25 seconds
Started Jul 04 04:56:47 PM PDT 24
Finished Jul 04 04:56:48 PM PDT 24
Peak memory 204504 kb
Host smart-df50626b-f0c1-480a-b8c8-43cd60c9b4e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229684872 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.4229684872
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.1076141916
Short name T1246
Test name
Test status
Simulation time 1437473348 ps
CPU time 2.71 seconds
Started Jul 04 04:56:50 PM PDT 24
Finished Jul 04 04:56:53 PM PDT 24
Peak memory 204604 kb
Host smart-8f2f8610-01aa-45db-b50c-1d2d33e354f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076141916 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.1076141916
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.226544504
Short name T607
Test name
Test status
Simulation time 164836789 ps
CPU time 1.34 seconds
Started Jul 04 04:56:51 PM PDT 24
Finished Jul 04 04:56:53 PM PDT 24
Peak memory 204512 kb
Host smart-037c6235-84f6-440e-a393-d469e0e977f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226544504 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.226544504
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.287885013
Short name T541
Test name
Test status
Simulation time 820666946 ps
CPU time 4.45 seconds
Started Jul 04 04:56:45 PM PDT 24
Finished Jul 04 04:56:50 PM PDT 24
Peak memory 212904 kb
Host smart-790e37fa-9097-4fdc-b58f-b840c2919278
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287885013 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_intr_smoke.287885013
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.3300236659
Short name T769
Test name
Test status
Simulation time 15746051683 ps
CPU time 105.99 seconds
Started Jul 04 04:56:44 PM PDT 24
Finished Jul 04 04:58:30 PM PDT 24
Peak memory 2104124 kb
Host smart-0cf75db1-9a70-463a-9c71-c8e0516f49d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300236659 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.3300236659
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.4092411861
Short name T1284
Test name
Test status
Simulation time 8363602511 ps
CPU time 26.37 seconds
Started Jul 04 04:56:45 PM PDT 24
Finished Jul 04 04:57:12 PM PDT 24
Peak memory 204780 kb
Host smart-4beb1fa0-b84e-428e-a6fc-784c2d7950c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092411861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.4092411861
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.331018276
Short name T1410
Test name
Test status
Simulation time 1052329454 ps
CPU time 15.1 seconds
Started Jul 04 04:56:44 PM PDT 24
Finished Jul 04 04:57:00 PM PDT 24
Peak memory 212028 kb
Host smart-6ed17e34-a31b-4aa5-9d71-f99ac63f3950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331018276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.331018276
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.3668273525
Short name T761
Test name
Test status
Simulation time 8674379768 ps
CPU time 16.2 seconds
Started Jul 04 04:56:46 PM PDT 24
Finished Jul 04 04:57:03 PM PDT 24
Peak memory 204800 kb
Host smart-5a079b3b-b08a-4384-b634-0089cebd53c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668273525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.3668273525
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.3605569697
Short name T1031
Test name
Test status
Simulation time 1176247055 ps
CPU time 6.44 seconds
Started Jul 04 04:56:43 PM PDT 24
Finished Jul 04 04:56:50 PM PDT 24
Peak memory 217048 kb
Host smart-24eac8cd-0388-4029-bd50-e59d3d167446
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605569697 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.3605569697
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.2661140314
Short name T733
Test name
Test status
Simulation time 74430501 ps
CPU time 1.71 seconds
Started Jul 04 04:56:52 PM PDT 24
Finished Jul 04 04:56:54 PM PDT 24
Peak memory 204652 kb
Host smart-64c10dc9-bde2-4be9-a447-cf5c9d71f59e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661140314 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.2661140314
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2016572016
Short name T1037
Test name
Test status
Simulation time 51037825 ps
CPU time 0.64 seconds
Started Jul 04 04:57:04 PM PDT 24
Finished Jul 04 04:57:05 PM PDT 24
Peak memory 204344 kb
Host smart-3658fa34-e7e8-4e44-8f6b-4877b14e9e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016572016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2016572016
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.628509811
Short name T52
Test name
Test status
Simulation time 655579032 ps
CPU time 8.14 seconds
Started Jul 04 04:56:52 PM PDT 24
Finished Jul 04 04:57:00 PM PDT 24
Peak memory 289400 kb
Host smart-d6f7d9da-4ccf-4608-b3be-3c4f716212a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628509811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.628509811
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.1322741231
Short name T661
Test name
Test status
Simulation time 653185946 ps
CPU time 16.58 seconds
Started Jul 04 04:56:51 PM PDT 24
Finished Jul 04 04:57:08 PM PDT 24
Peak memory 268512 kb
Host smart-503d2a76-909b-45b1-921e-039e1571c6a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322741231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.1322741231
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.7773163
Short name T1079
Test name
Test status
Simulation time 6210183228 ps
CPU time 36.2 seconds
Started Jul 04 04:56:53 PM PDT 24
Finished Jul 04 04:57:29 PM PDT 24
Peak memory 485268 kb
Host smart-02b2d97f-4ca5-4298-8534-fca787064617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7773163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.7773163
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1677434671
Short name T1170
Test name
Test status
Simulation time 2428698723 ps
CPU time 174.31 seconds
Started Jul 04 04:56:52 PM PDT 24
Finished Jul 04 04:59:47 PM PDT 24
Peak memory 745236 kb
Host smart-c0c0b8d8-ca5a-4a01-b61e-db99648a91da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677434671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1677434671
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.3428088717
Short name T1204
Test name
Test status
Simulation time 120046234 ps
CPU time 1.09 seconds
Started Jul 04 04:56:52 PM PDT 24
Finished Jul 04 04:56:53 PM PDT 24
Peak memory 204312 kb
Host smart-02e4b6ce-96c7-4862-9bc9-a96d4a8ded4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428088717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.3428088717
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.1288476702
Short name T935
Test name
Test status
Simulation time 194966189 ps
CPU time 11.09 seconds
Started Jul 04 04:56:51 PM PDT 24
Finished Jul 04 04:57:02 PM PDT 24
Peak memory 242304 kb
Host smart-4a1f8f46-b31c-45ee-86bc-8b4023a256b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288476702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.1288476702
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.833500726
Short name T1040
Test name
Test status
Simulation time 4548170000 ps
CPU time 97.88 seconds
Started Jul 04 04:56:53 PM PDT 24
Finished Jul 04 04:58:31 PM PDT 24
Peak memory 1249036 kb
Host smart-45162fe3-95b9-4656-ac2b-730f5f5556a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833500726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.833500726
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.617771302
Short name T670
Test name
Test status
Simulation time 23915061353 ps
CPU time 26.57 seconds
Started Jul 04 04:57:04 PM PDT 24
Finished Jul 04 04:57:31 PM PDT 24
Peak memory 363228 kb
Host smart-c6e6b4fe-17e3-43a7-9b89-9eccbb9d4536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617771302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.617771302
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.1485452634
Short name T1463
Test name
Test status
Simulation time 20323575 ps
CPU time 0.69 seconds
Started Jul 04 04:56:51 PM PDT 24
Finished Jul 04 04:56:53 PM PDT 24
Peak memory 204436 kb
Host smart-1d7645bf-7460-40be-a66d-b1c0996c3271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485452634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1485452634
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.1744605087
Short name T919
Test name
Test status
Simulation time 7352341795 ps
CPU time 95.83 seconds
Started Jul 04 04:56:51 PM PDT 24
Finished Jul 04 04:58:27 PM PDT 24
Peak memory 204820 kb
Host smart-4c821f02-32ca-465d-8839-750f8d05a3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744605087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1744605087
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.1729814905
Short name T233
Test name
Test status
Simulation time 2989533424 ps
CPU time 23.8 seconds
Started Jul 04 04:56:51 PM PDT 24
Finished Jul 04 04:57:15 PM PDT 24
Peak memory 265552 kb
Host smart-c43a4b59-98ec-4a7d-9ce8-b7bb697f881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729814905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.1729814905
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.767128729
Short name T960
Test name
Test status
Simulation time 10194550764 ps
CPU time 102.78 seconds
Started Jul 04 04:56:52 PM PDT 24
Finished Jul 04 04:58:35 PM PDT 24
Peak memory 427136 kb
Host smart-6f155f3d-9e57-4e08-8e05-9f87fca063ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767128729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.767128729
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.1181504341
Short name T134
Test name
Test status
Simulation time 10683439552 ps
CPU time 342.29 seconds
Started Jul 04 04:56:53 PM PDT 24
Finished Jul 04 05:02:36 PM PDT 24
Peak memory 1089448 kb
Host smart-053c0541-2fe4-44a4-be87-77a3927a899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181504341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.1181504341
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.437049773
Short name T1499
Test name
Test status
Simulation time 711292218 ps
CPU time 13.42 seconds
Started Jul 04 04:56:52 PM PDT 24
Finished Jul 04 04:57:06 PM PDT 24
Peak memory 221104 kb
Host smart-b7efe3a5-80ea-4280-9f01-a6f81d638fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437049773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.437049773
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.517874816
Short name T1297
Test name
Test status
Simulation time 525501848 ps
CPU time 3.28 seconds
Started Jul 04 04:57:05 PM PDT 24
Finished Jul 04 04:57:09 PM PDT 24
Peak memory 204812 kb
Host smart-6be18888-fb61-44e9-bb23-f8dca46393b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517874816 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.517874816
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.4261189885
Short name T1304
Test name
Test status
Simulation time 357585696 ps
CPU time 1.03 seconds
Started Jul 04 04:57:03 PM PDT 24
Finished Jul 04 04:57:04 PM PDT 24
Peak memory 204720 kb
Host smart-a98fbe18-8fbf-431a-829c-93ed2067d118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261189885 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.4261189885
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3698575208
Short name T1166
Test name
Test status
Simulation time 450180544 ps
CPU time 1.66 seconds
Started Jul 04 04:57:02 PM PDT 24
Finished Jul 04 04:57:04 PM PDT 24
Peak memory 204692 kb
Host smart-c23e886c-5bdb-4bc4-aff2-07afca0ab57c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698575208 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3698575208
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.3271794568
Short name T879
Test name
Test status
Simulation time 656732220 ps
CPU time 2.01 seconds
Started Jul 04 04:57:04 PM PDT 24
Finished Jul 04 04:57:07 PM PDT 24
Peak memory 204820 kb
Host smart-d80585ca-a52e-419d-8677-f031305d99b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271794568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.3271794568
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.1089600170
Short name T773
Test name
Test status
Simulation time 471814905 ps
CPU time 1.05 seconds
Started Jul 04 04:57:03 PM PDT 24
Finished Jul 04 04:57:05 PM PDT 24
Peak memory 204556 kb
Host smart-5caa8bf2-0da6-4689-a8f7-f03dca0ec233
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089600170 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.1089600170
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1042904871
Short name T904
Test name
Test status
Simulation time 871904535 ps
CPU time 3.29 seconds
Started Jul 04 04:57:03 PM PDT 24
Finished Jul 04 04:57:07 PM PDT 24
Peak memory 204820 kb
Host smart-5db9422e-c541-4c08-8783-d0ced35dfafc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042904871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.1042904871
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2963154478
Short name T366
Test name
Test status
Simulation time 913675423 ps
CPU time 5.34 seconds
Started Jul 04 04:56:53 PM PDT 24
Finished Jul 04 04:56:59 PM PDT 24
Peak memory 215752 kb
Host smart-03c50ee6-a39f-4366-a0bd-1e872b7e8215
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963154478 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2963154478
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.2475494837
Short name T179
Test name
Test status
Simulation time 3595602660 ps
CPU time 4.35 seconds
Started Jul 04 04:56:51 PM PDT 24
Finished Jul 04 04:56:56 PM PDT 24
Peak memory 204764 kb
Host smart-6bdd644d-1100-4dd6-89e2-457037834fac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475494837 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.2475494837
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.1711043136
Short name T144
Test name
Test status
Simulation time 3147696959 ps
CPU time 17.45 seconds
Started Jul 04 04:56:53 PM PDT 24
Finished Jul 04 04:57:11 PM PDT 24
Peak memory 204768 kb
Host smart-5ba9ac0f-ff0a-4db9-8036-f8fdfcfdae42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711043136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.1711043136
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.1322739305
Short name T1520
Test name
Test status
Simulation time 9258406317 ps
CPU time 21.64 seconds
Started Jul 04 04:56:51 PM PDT 24
Finished Jul 04 04:57:13 PM PDT 24
Peak memory 236312 kb
Host smart-eae824a8-a520-447a-bb43-935c6aa33369
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322739305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.1322739305
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.2164930711
Short name T1253
Test name
Test status
Simulation time 15904950127 ps
CPU time 30.14 seconds
Started Jul 04 04:56:51 PM PDT 24
Finished Jul 04 04:57:22 PM PDT 24
Peak memory 204788 kb
Host smart-a1d9e034-f3a4-4b81-9698-296a56ec161b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164930711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.2164930711
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.1200737409
Short name T301
Test name
Test status
Simulation time 39224665302 ps
CPU time 355.62 seconds
Started Jul 04 04:56:53 PM PDT 24
Finished Jul 04 05:02:49 PM PDT 24
Peak memory 2458968 kb
Host smart-5ef7e289-999c-42d4-99ec-b8f15323c32c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200737409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.1200737409
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.2517209344
Short name T566
Test name
Test status
Simulation time 2364288016 ps
CPU time 6.94 seconds
Started Jul 04 04:57:03 PM PDT 24
Finished Jul 04 04:57:10 PM PDT 24
Peak memory 212060 kb
Host smart-153455d4-214d-44ed-a885-4eba9a1da878
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517209344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.2517209344
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.2619211436
Short name T942
Test name
Test status
Simulation time 88655274 ps
CPU time 2.12 seconds
Started Jul 04 04:57:05 PM PDT 24
Finished Jul 04 04:57:08 PM PDT 24
Peak memory 204720 kb
Host smart-39f5236f-0a34-4e48-8b16-c769d29abdd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619211436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.2619211436
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.840868404
Short name T180
Test name
Test status
Simulation time 16765449 ps
CPU time 0.64 seconds
Started Jul 04 04:57:05 PM PDT 24
Finished Jul 04 04:57:06 PM PDT 24
Peak memory 204352 kb
Host smart-f28550b0-180f-411e-b8fb-626c19878cdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840868404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.840868404
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.2168669365
Short name T578
Test name
Test status
Simulation time 90351517 ps
CPU time 1.88 seconds
Started Jul 04 04:57:04 PM PDT 24
Finished Jul 04 04:57:06 PM PDT 24
Peak memory 213036 kb
Host smart-65de4c86-211f-4221-af09-b264052dadf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168669365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2168669365
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.840477766
Short name T565
Test name
Test status
Simulation time 541743306 ps
CPU time 27.91 seconds
Started Jul 04 04:57:05 PM PDT 24
Finished Jul 04 04:57:33 PM PDT 24
Peak memory 323048 kb
Host smart-020acc92-d5f3-4a9f-8ccc-f22b2f6aa5cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840477766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empt
y.840477766
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.4250153965
Short name T1022
Test name
Test status
Simulation time 1976236286 ps
CPU time 45.97 seconds
Started Jul 04 04:57:08 PM PDT 24
Finished Jul 04 04:57:54 PM PDT 24
Peak memory 462684 kb
Host smart-00e5549c-605c-4cbf-985e-9161a2037f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250153965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.4250153965
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.3216198547
Short name T1127
Test name
Test status
Simulation time 9616799224 ps
CPU time 175.09 seconds
Started Jul 04 04:57:03 PM PDT 24
Finished Jul 04 04:59:59 PM PDT 24
Peak memory 748956 kb
Host smart-c536d06c-5f72-4841-a950-a83a2a317d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216198547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.3216198547
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.4091358899
Short name T1192
Test name
Test status
Simulation time 93629741 ps
CPU time 0.95 seconds
Started Jul 04 04:57:03 PM PDT 24
Finished Jul 04 04:57:04 PM PDT 24
Peak memory 204324 kb
Host smart-708c75e4-8bf2-4e74-a2f3-a7d0092ccf14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091358899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.4091358899
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.4013794146
Short name T1523
Test name
Test status
Simulation time 796472168 ps
CPU time 5.03 seconds
Started Jul 04 04:57:09 PM PDT 24
Finished Jul 04 04:57:14 PM PDT 24
Peak memory 242280 kb
Host smart-62ffce2e-4fa5-4add-866a-82ee647b114a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013794146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.4013794146
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.2055502691
Short name T117
Test name
Test status
Simulation time 6146283644 ps
CPU time 67.26 seconds
Started Jul 04 04:57:02 PM PDT 24
Finished Jul 04 04:58:09 PM PDT 24
Peak memory 957256 kb
Host smart-bdf71c0d-71a8-4fa9-a313-f02ce4de4658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055502691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.2055502691
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.2985960654
Short name T1167
Test name
Test status
Simulation time 12597497869 ps
CPU time 7.84 seconds
Started Jul 04 04:57:09 PM PDT 24
Finished Jul 04 04:57:17 PM PDT 24
Peak memory 204912 kb
Host smart-1777be46-365b-4a20-a9c2-d8c08dce12d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985960654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.2985960654
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.727270908
Short name T378
Test name
Test status
Simulation time 1442489033 ps
CPU time 19.4 seconds
Started Jul 04 04:57:05 PM PDT 24
Finished Jul 04 04:57:25 PM PDT 24
Peak memory 278712 kb
Host smart-9e1ee43b-cbdc-4047-87c4-ffaefbed57ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727270908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.727270908
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.1240346141
Short name T1300
Test name
Test status
Simulation time 26217272 ps
CPU time 0.69 seconds
Started Jul 04 04:57:04 PM PDT 24
Finished Jul 04 04:57:05 PM PDT 24
Peak memory 204352 kb
Host smart-f8194053-391d-4e6c-91d0-40d8d43d8f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240346141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1240346141
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.64876997
Short name T712
Test name
Test status
Simulation time 5425061457 ps
CPU time 133.15 seconds
Started Jul 04 04:57:06 PM PDT 24
Finished Jul 04 04:59:20 PM PDT 24
Peak memory 205612 kb
Host smart-7552dd65-63b5-4e38-8efb-4b4ec8ece050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64876997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.64876997
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.2234852154
Short name T841
Test name
Test status
Simulation time 205650856 ps
CPU time 2.87 seconds
Started Jul 04 04:57:04 PM PDT 24
Finished Jul 04 04:57:07 PM PDT 24
Peak memory 222120 kb
Host smart-09a6e947-e2e7-427f-bcea-2228386eaeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234852154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.2234852154
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.191429121
Short name T288
Test name
Test status
Simulation time 5123601214 ps
CPU time 25.37 seconds
Started Jul 04 04:57:02 PM PDT 24
Finished Jul 04 04:57:28 PM PDT 24
Peak memory 324340 kb
Host smart-77dc72f4-78fb-4a2e-b653-390a97a492aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191429121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.191429121
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.4182964364
Short name T1356
Test name
Test status
Simulation time 27923303291 ps
CPU time 194.06 seconds
Started Jul 04 04:57:06 PM PDT 24
Finished Jul 04 05:00:20 PM PDT 24
Peak memory 1053576 kb
Host smart-05517094-35e6-4b71-8377-a8fd9a6585af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182964364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.4182964364
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.3858872773
Short name T323
Test name
Test status
Simulation time 3032154174 ps
CPU time 18.65 seconds
Started Jul 04 04:57:02 PM PDT 24
Finished Jul 04 04:57:22 PM PDT 24
Peak memory 212920 kb
Host smart-af52783a-a4ee-400d-9c68-7fdee6e6ae59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858872773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3858872773
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.2616196543
Short name T1110
Test name
Test status
Simulation time 3226520283 ps
CPU time 4.18 seconds
Started Jul 04 04:57:06 PM PDT 24
Finished Jul 04 04:57:10 PM PDT 24
Peak memory 212952 kb
Host smart-6f2688aa-60a7-42df-b53a-bc6fbb0e0b5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616196543 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.2616196543
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.2306377653
Short name T439
Test name
Test status
Simulation time 468117054 ps
CPU time 1.08 seconds
Started Jul 04 04:57:08 PM PDT 24
Finished Jul 04 04:57:09 PM PDT 24
Peak memory 204516 kb
Host smart-a7101396-5f89-45f6-898d-c4ed2f96ccc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306377653 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.2306377653
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3311847628
Short name T92
Test name
Test status
Simulation time 957901330 ps
CPU time 1.6 seconds
Started Jul 04 04:57:04 PM PDT 24
Finished Jul 04 04:57:06 PM PDT 24
Peak memory 207832 kb
Host smart-4e0c77dd-5d73-49ab-a4ca-bbddea5e8478
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311847628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3311847628
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.3789656102
Short name T623
Test name
Test status
Simulation time 971614082 ps
CPU time 2.41 seconds
Started Jul 04 04:57:08 PM PDT 24
Finished Jul 04 04:57:10 PM PDT 24
Peak memory 204636 kb
Host smart-5af433bd-1289-4cd6-bc4c-b5bf38a8c91d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789656102 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.3789656102
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.4289975046
Short name T448
Test name
Test status
Simulation time 132414959 ps
CPU time 1.24 seconds
Started Jul 04 04:57:02 PM PDT 24
Finished Jul 04 04:57:03 PM PDT 24
Peak memory 204436 kb
Host smart-7f3b754b-9f72-4b00-9952-ae546c7c757e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289975046 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.4289975046
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.505709875
Short name T1135
Test name
Test status
Simulation time 1059400112 ps
CPU time 5.72 seconds
Started Jul 04 04:57:08 PM PDT 24
Finished Jul 04 04:57:14 PM PDT 24
Peak memory 215772 kb
Host smart-c978fba3-9184-47b3-bbc0-065191a1fe04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505709875 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.505709875
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.2607373865
Short name T1004
Test name
Test status
Simulation time 26180434263 ps
CPU time 27.19 seconds
Started Jul 04 04:57:06 PM PDT 24
Finished Jul 04 04:57:33 PM PDT 24
Peak memory 668004 kb
Host smart-ef7a3e27-48f2-4507-a916-8719dfac8ab4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607373865 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2607373865
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.4207901713
Short name T669
Test name
Test status
Simulation time 540352672 ps
CPU time 4.2 seconds
Started Jul 04 04:57:08 PM PDT 24
Finished Jul 04 04:57:12 PM PDT 24
Peak memory 204700 kb
Host smart-a20b9716-bf79-4726-8802-c99e5ed2b7e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207901713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.4207901713
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3271548177
Short name T731
Test name
Test status
Simulation time 1221175017 ps
CPU time 53.6 seconds
Started Jul 04 04:57:03 PM PDT 24
Finished Jul 04 04:57:57 PM PDT 24
Peak memory 206212 kb
Host smart-6cb4990f-4151-44b0-aa60-8898d992643a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271548177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3271548177
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.1727877500
Short name T767
Test name
Test status
Simulation time 20781079060 ps
CPU time 43.17 seconds
Started Jul 04 04:57:07 PM PDT 24
Finished Jul 04 04:57:50 PM PDT 24
Peak memory 276552 kb
Host smart-8ad983f7-2531-43c1-bbd5-d07e8c988a30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727877500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.1727877500
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.377736475
Short name T442
Test name
Test status
Simulation time 33905478502 ps
CPU time 2539.04 seconds
Started Jul 04 04:57:04 PM PDT 24
Finished Jul 04 05:39:24 PM PDT 24
Peak memory 7783616 kb
Host smart-e2c4a538-bdeb-4ebe-b939-904d4770ebbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377736475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.377736475
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.4169259205
Short name T1353
Test name
Test status
Simulation time 4874900773 ps
CPU time 7.28 seconds
Started Jul 04 04:57:07 PM PDT 24
Finished Jul 04 04:57:15 PM PDT 24
Peak memory 220104 kb
Host smart-231542b8-e5cf-4890-a338-0b1aa95b5720
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169259205 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.4169259205
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.1815200550
Short name T1484
Test name
Test status
Simulation time 61211441 ps
CPU time 1.35 seconds
Started Jul 04 04:57:08 PM PDT 24
Finished Jul 04 04:57:09 PM PDT 24
Peak memory 204740 kb
Host smart-e102ea3c-1d90-4334-9acb-a6278d4c0f41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815200550 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.1815200550
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.2645682579
Short name T747
Test name
Test status
Simulation time 25371367 ps
CPU time 0.66 seconds
Started Jul 04 04:57:19 PM PDT 24
Finished Jul 04 04:57:20 PM PDT 24
Peak memory 204376 kb
Host smart-f0e533b7-f9ba-4554-b7a3-4e0f290c7972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645682579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.2645682579
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2335790492
Short name T811
Test name
Test status
Simulation time 429239309 ps
CPU time 3.39 seconds
Started Jul 04 04:57:13 PM PDT 24
Finished Jul 04 04:57:17 PM PDT 24
Peak memory 220712 kb
Host smart-1e2c6a57-7618-4c27-ab5a-793b8ca0216f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335790492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2335790492
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.4165650883
Short name T1176
Test name
Test status
Simulation time 1327470203 ps
CPU time 4.7 seconds
Started Jul 04 04:57:10 PM PDT 24
Finished Jul 04 04:57:15 PM PDT 24
Peak memory 256388 kb
Host smart-f49a4d71-b1a3-4ba4-85d8-24b2e6f0923d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165650883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.4165650883
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.502452038
Short name T827
Test name
Test status
Simulation time 1567002802 ps
CPU time 52.07 seconds
Started Jul 04 04:57:09 PM PDT 24
Finished Jul 04 04:58:02 PM PDT 24
Peak memory 565408 kb
Host smart-14cf6388-ff71-4bec-a7a7-3f61a6e2cc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502452038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.502452038
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.72364460
Short name T989
Test name
Test status
Simulation time 1713149618 ps
CPU time 1.06 seconds
Started Jul 04 04:57:11 PM PDT 24
Finished Jul 04 04:57:12 PM PDT 24
Peak memory 204440 kb
Host smart-6cb69ec3-bb0b-4965-9f44-03d9eabf1b44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72364460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fmt
.72364460
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.332023525
Short name T569
Test name
Test status
Simulation time 165643380 ps
CPU time 8.83 seconds
Started Jul 04 04:57:10 PM PDT 24
Finished Jul 04 04:57:19 PM PDT 24
Peak memory 204668 kb
Host smart-a01b2b4d-bbac-4b82-ac91-325c80a5a598
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332023525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.
332023525
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.395245767
Short name T115
Test name
Test status
Simulation time 20207739287 ps
CPU time 115.71 seconds
Started Jul 04 04:57:12 PM PDT 24
Finished Jul 04 04:59:08 PM PDT 24
Peak memory 1443332 kb
Host smart-c8db09af-43c0-4282-9950-d8742e325496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395245767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.395245767
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.3038342406
Short name T1118
Test name
Test status
Simulation time 1663736653 ps
CPU time 6.27 seconds
Started Jul 04 04:57:12 PM PDT 24
Finished Jul 04 04:57:19 PM PDT 24
Peak memory 204644 kb
Host smart-cffa6ddd-127b-4320-a90b-8364b3414708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038342406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.3038342406
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_override.922425902
Short name T5
Test name
Test status
Simulation time 28186930 ps
CPU time 0.74 seconds
Started Jul 04 04:57:12 PM PDT 24
Finished Jul 04 04:57:12 PM PDT 24
Peak memory 204400 kb
Host smart-87346b76-ed86-4da8-8b99-3aa282b4523d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922425902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.922425902
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2124399045
Short name T1149
Test name
Test status
Simulation time 6277251662 ps
CPU time 238.14 seconds
Started Jul 04 04:57:12 PM PDT 24
Finished Jul 04 05:01:10 PM PDT 24
Peak memory 229204 kb
Host smart-3e7f18ef-3eb7-417f-9570-d6aca7652781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124399045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2124399045
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.3357137158
Short name T346
Test name
Test status
Simulation time 52502414 ps
CPU time 2.78 seconds
Started Jul 04 04:57:12 PM PDT 24
Finished Jul 04 04:57:15 PM PDT 24
Peak memory 226416 kb
Host smart-4b9ee22d-4e8c-465d-ac80-9d4efa7dd326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357137158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.3357137158
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.4203203080
Short name T1318
Test name
Test status
Simulation time 3096626958 ps
CPU time 25.46 seconds
Started Jul 04 04:57:05 PM PDT 24
Finished Jul 04 04:57:31 PM PDT 24
Peak memory 341088 kb
Host smart-6e00cd23-2f0b-4f23-81b9-21df4bdd2056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203203080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.4203203080
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.3286986005
Short name T267
Test name
Test status
Simulation time 93380904383 ps
CPU time 832.86 seconds
Started Jul 04 04:57:11 PM PDT 24
Finished Jul 04 05:11:04 PM PDT 24
Peak memory 2436168 kb
Host smart-b9be00d9-b061-40d8-baf4-3150938c16cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286986005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.3286986005
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.195976120
Short name T1432
Test name
Test status
Simulation time 323128953 ps
CPU time 6.76 seconds
Started Jul 04 04:57:11 PM PDT 24
Finished Jul 04 04:57:17 PM PDT 24
Peak memory 212872 kb
Host smart-cf536a35-e69c-40c2-a45f-65ddc4abb661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195976120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.195976120
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.860766357
Short name T1245
Test name
Test status
Simulation time 4416886519 ps
CPU time 4.89 seconds
Started Jul 04 04:57:14 PM PDT 24
Finished Jul 04 04:57:19 PM PDT 24
Peak memory 212988 kb
Host smart-bf23555f-cecd-458c-bc84-fe7d2da8a840
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860766357 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.860766357
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1440389036
Short name T1396
Test name
Test status
Simulation time 543610246 ps
CPU time 1.21 seconds
Started Jul 04 04:57:11 PM PDT 24
Finished Jul 04 04:57:13 PM PDT 24
Peak memory 204420 kb
Host smart-91b27136-4566-4abf-b435-0cb481a31164
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440389036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1440389036
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.1210081863
Short name T926
Test name
Test status
Simulation time 251450760 ps
CPU time 1.51 seconds
Started Jul 04 04:57:12 PM PDT 24
Finished Jul 04 04:57:14 PM PDT 24
Peak memory 212900 kb
Host smart-3d8d06a0-8d62-4384-b1f9-ea1d72ff3329
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210081863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.1210081863
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.3220647052
Short name T1055
Test name
Test status
Simulation time 2926051690 ps
CPU time 2.81 seconds
Started Jul 04 04:57:18 PM PDT 24
Finished Jul 04 04:57:21 PM PDT 24
Peak memory 204780 kb
Host smart-c4eb14b2-b198-4429-ac85-b8d2e9cd2945
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220647052 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.3220647052
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.3939577728
Short name T178
Test name
Test status
Simulation time 299409646 ps
CPU time 1.25 seconds
Started Jul 04 04:57:17 PM PDT 24
Finished Jul 04 04:57:18 PM PDT 24
Peak memory 204508 kb
Host smart-007971e1-aaa7-4f63-a732-7626adc675a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939577728 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.3939577728
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.4106758037
Short name T783
Test name
Test status
Simulation time 293900370 ps
CPU time 2.56 seconds
Started Jul 04 04:57:12 PM PDT 24
Finished Jul 04 04:57:15 PM PDT 24
Peak memory 204704 kb
Host smart-ee9a059b-8e4a-464b-813a-73ce8609cd27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106758037 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.4106758037
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2302133764
Short name T1365
Test name
Test status
Simulation time 761130499 ps
CPU time 4.47 seconds
Started Jul 04 04:57:13 PM PDT 24
Finished Jul 04 04:57:18 PM PDT 24
Peak memory 212900 kb
Host smart-b7191b29-28c0-4e81-ba13-96b43c9a1bff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302133764 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2302133764
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.3340761502
Short name T494
Test name
Test status
Simulation time 17107553218 ps
CPU time 43.29 seconds
Started Jul 04 04:57:09 PM PDT 24
Finished Jul 04 04:57:53 PM PDT 24
Peak memory 1009000 kb
Host smart-af5b30bd-5b41-458c-85d2-3e49bbd34eea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340761502 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.3340761502
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.1781394751
Short name T1524
Test name
Test status
Simulation time 4803012403 ps
CPU time 16.04 seconds
Started Jul 04 04:57:14 PM PDT 24
Finished Jul 04 04:57:30 PM PDT 24
Peak memory 204832 kb
Host smart-c71c6319-ce03-4568-bc43-674b65e7edff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781394751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.1781394751
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.340479864
Short name T1372
Test name
Test status
Simulation time 4740448993 ps
CPU time 36.22 seconds
Started Jul 04 04:57:13 PM PDT 24
Finished Jul 04 04:57:49 PM PDT 24
Peak memory 204920 kb
Host smart-c711d14a-ff08-4deb-ad11-3eca9c56553d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340479864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.340479864
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.3142680135
Short name T1473
Test name
Test status
Simulation time 35605211863 ps
CPU time 393.26 seconds
Started Jul 04 04:57:13 PM PDT 24
Finished Jul 04 05:03:46 PM PDT 24
Peak memory 3956180 kb
Host smart-c63d9286-14b0-4020-b4b1-ba56265c8081
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142680135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.3142680135
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.1945449378
Short name T308
Test name
Test status
Simulation time 21611835199 ps
CPU time 699.7 seconds
Started Jul 04 04:57:13 PM PDT 24
Finished Jul 04 05:08:53 PM PDT 24
Peak memory 2135528 kb
Host smart-41d12b06-aaaf-461a-8c52-90456fa16645
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945449378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.1945449378
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2847868271
Short name T474
Test name
Test status
Simulation time 4608182887 ps
CPU time 6.87 seconds
Started Jul 04 04:57:10 PM PDT 24
Finished Jul 04 04:57:17 PM PDT 24
Peak memory 204880 kb
Host smart-c9e2e370-bab6-4537-b6e7-4ad42963b14e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847868271 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2847868271
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.2632202122
Short name T781
Test name
Test status
Simulation time 173260980 ps
CPU time 2.6 seconds
Started Jul 04 04:57:18 PM PDT 24
Finished Jul 04 04:57:21 PM PDT 24
Peak memory 204640 kb
Host smart-28482bbe-248d-439d-82e2-126e94741b6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632202122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.2632202122
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.4000348111
Short name T1518
Test name
Test status
Simulation time 14528170 ps
CPU time 0.63 seconds
Started Jul 04 04:52:24 PM PDT 24
Finished Jul 04 04:52:25 PM PDT 24
Peak memory 204432 kb
Host smart-d822730f-5bce-4b55-a966-4e5084993cc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000348111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.4000348111
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.2912049534
Short name T48
Test name
Test status
Simulation time 463521115 ps
CPU time 3.32 seconds
Started Jul 04 04:52:21 PM PDT 24
Finished Jul 04 04:52:25 PM PDT 24
Peak memory 212992 kb
Host smart-2e522983-da63-4ee1-8827-4416df10f879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912049534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.2912049534
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.518573313
Short name T457
Test name
Test status
Simulation time 443586079 ps
CPU time 10.28 seconds
Started Jul 04 04:52:21 PM PDT 24
Finished Jul 04 04:52:32 PM PDT 24
Peak memory 302708 kb
Host smart-44b3ed81-26f4-44b1-a6b7-2cc8a43c1455
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518573313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.518573313
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.2011930826
Short name T667
Test name
Test status
Simulation time 40940402130 ps
CPU time 225.47 seconds
Started Jul 04 04:52:30 PM PDT 24
Finished Jul 04 04:56:15 PM PDT 24
Peak memory 920024 kb
Host smart-0d1970b4-2e3e-4063-b810-d76d33613cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011930826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2011930826
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.287266483
Short name T1152
Test name
Test status
Simulation time 3857484756 ps
CPU time 187.75 seconds
Started Jul 04 04:52:24 PM PDT 24
Finished Jul 04 04:55:32 PM PDT 24
Peak memory 782812 kb
Host smart-9ddab0e8-0f09-48fd-90f5-0d085eda4d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287266483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.287266483
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.163512160
Short name T742
Test name
Test status
Simulation time 329094098 ps
CPU time 1.02 seconds
Started Jul 04 04:52:20 PM PDT 24
Finished Jul 04 04:52:21 PM PDT 24
Peak memory 204356 kb
Host smart-d11c6717-f0a9-459a-97dc-8bed3a83bbe4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163512160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.163512160
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2143767563
Short name T1034
Test name
Test status
Simulation time 306196723 ps
CPU time 9.09 seconds
Started Jul 04 04:52:21 PM PDT 24
Finished Jul 04 04:52:30 PM PDT 24
Peak memory 229644 kb
Host smart-dac8eecf-3a3e-4772-a2e2-ed076b28274f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143767563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2143767563
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.3555359977
Short name T271
Test name
Test status
Simulation time 22345829525 ps
CPU time 224.52 seconds
Started Jul 04 04:52:23 PM PDT 24
Finished Jul 04 04:56:08 PM PDT 24
Peak memory 982784 kb
Host smart-661e7131-10dd-46d1-88d7-0c24a64c10f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555359977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.3555359977
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.4202938575
Short name T1267
Test name
Test status
Simulation time 580427514 ps
CPU time 4.1 seconds
Started Jul 04 04:52:21 PM PDT 24
Finished Jul 04 04:52:25 PM PDT 24
Peak memory 204704 kb
Host smart-3f82fde2-65b9-41dc-be81-c2034b54dec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202938575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.4202938575
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.4233812514
Short name T931
Test name
Test status
Simulation time 8780774734 ps
CPU time 83.18 seconds
Started Jul 04 04:52:30 PM PDT 24
Finished Jul 04 04:53:53 PM PDT 24
Peak memory 417116 kb
Host smart-31a1fa9c-a162-4be5-a902-0cf504d9d043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233812514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.4233812514
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.519243418
Short name T150
Test name
Test status
Simulation time 20229985 ps
CPU time 0.67 seconds
Started Jul 04 04:52:17 PM PDT 24
Finished Jul 04 04:52:18 PM PDT 24
Peak memory 204424 kb
Host smart-35be1d78-d484-4491-8a7e-c514879c2bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519243418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.519243418
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.1555603089
Short name T1341
Test name
Test status
Simulation time 13320398970 ps
CPU time 49.07 seconds
Started Jul 04 04:52:23 PM PDT 24
Finished Jul 04 04:53:13 PM PDT 24
Peak memory 606832 kb
Host smart-754ac186-8b1f-42cd-b4f8-666f58009467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555603089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1555603089
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.3481470017
Short name T1323
Test name
Test status
Simulation time 6232798825 ps
CPU time 15.84 seconds
Started Jul 04 04:52:28 PM PDT 24
Finished Jul 04 04:52:44 PM PDT 24
Peak memory 204724 kb
Host smart-967d6f06-2f4b-4cf2-ab1f-20c2bd802e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481470017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.3481470017
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1398032707
Short name T59
Test name
Test status
Simulation time 3226378249 ps
CPU time 25.75 seconds
Started Jul 04 04:52:20 PM PDT 24
Finished Jul 04 04:52:46 PM PDT 24
Peak memory 333532 kb
Host smart-9812d061-b1fa-4ca7-8178-60dcc6ed850a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398032707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1398032707
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.2456339801
Short name T281
Test name
Test status
Simulation time 15497993892 ps
CPU time 498.49 seconds
Started Jul 04 04:52:23 PM PDT 24
Finished Jul 04 05:00:42 PM PDT 24
Peak memory 1364076 kb
Host smart-14b77314-03a3-43ba-8f86-2a74f15b9d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456339801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.2456339801
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.956754966
Short name T338
Test name
Test status
Simulation time 2663840573 ps
CPU time 8.99 seconds
Started Jul 04 04:52:23 PM PDT 24
Finished Jul 04 04:52:33 PM PDT 24
Peak memory 214188 kb
Host smart-16abd770-26ff-4712-8880-151317a07ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956754966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.956754966
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.69376368
Short name T22
Test name
Test status
Simulation time 11585560705 ps
CPU time 4.58 seconds
Started Jul 04 04:52:21 PM PDT 24
Finished Jul 04 04:52:26 PM PDT 24
Peak memory 213068 kb
Host smart-30cdd2ad-9b97-4342-9183-42a6ec63dc21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69376368 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_bad_addr.69376368
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.4011170601
Short name T1095
Test name
Test status
Simulation time 250765950 ps
CPU time 1.02 seconds
Started Jul 04 04:52:22 PM PDT 24
Finished Jul 04 04:52:24 PM PDT 24
Peak memory 204536 kb
Host smart-5d64fa8a-a1e3-4a20-87f0-35b9f042f706
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011170601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.4011170601
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2225439690
Short name T651
Test name
Test status
Simulation time 1328665682 ps
CPU time 1.25 seconds
Started Jul 04 04:52:27 PM PDT 24
Finished Jul 04 04:52:29 PM PDT 24
Peak memory 205496 kb
Host smart-43f6deab-cf1a-4c8c-b5e5-f436b0e04b65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225439690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2225439690
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.3782637921
Short name T452
Test name
Test status
Simulation time 1390565579 ps
CPU time 1.9 seconds
Started Jul 04 04:52:24 PM PDT 24
Finished Jul 04 04:52:27 PM PDT 24
Peak memory 204692 kb
Host smart-12fcbe9a-7636-49ea-96d1-05e90583aa93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782637921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.3782637921
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.2456213984
Short name T1345
Test name
Test status
Simulation time 646923976 ps
CPU time 1.31 seconds
Started Jul 04 04:52:21 PM PDT 24
Finished Jul 04 04:52:22 PM PDT 24
Peak memory 204500 kb
Host smart-e2cdb08b-7e0b-4622-a4cc-396a8ba949b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456213984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.2456213984
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.1483430918
Short name T587
Test name
Test status
Simulation time 22044763194 ps
CPU time 7.65 seconds
Started Jul 04 04:52:23 PM PDT 24
Finished Jul 04 04:52:31 PM PDT 24
Peak memory 214292 kb
Host smart-be6147cb-668c-478e-bd5c-5916c602874b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483430918 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.1483430918
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.4094284957
Short name T1490
Test name
Test status
Simulation time 6083701727 ps
CPU time 4.91 seconds
Started Jul 04 04:52:22 PM PDT 24
Finished Jul 04 04:52:27 PM PDT 24
Peak memory 204800 kb
Host smart-8be4f896-1298-4606-941a-f02e6ce03b45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094284957 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.4094284957
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3076576475
Short name T407
Test name
Test status
Simulation time 775734486 ps
CPU time 10.69 seconds
Started Jul 04 04:52:30 PM PDT 24
Finished Jul 04 04:52:41 PM PDT 24
Peak memory 204668 kb
Host smart-36f4d73b-8b02-41ff-9937-b237e9be3d79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076576475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3076576475
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.2519063278
Short name T992
Test name
Test status
Simulation time 693596838 ps
CPU time 6.18 seconds
Started Jul 04 04:52:29 PM PDT 24
Finished Jul 04 04:52:36 PM PDT 24
Peak memory 204716 kb
Host smart-9e5811c9-2425-429b-bc1f-ec036329a69f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519063278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.2519063278
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2886385117
Short name T1036
Test name
Test status
Simulation time 6672082295 ps
CPU time 12.32 seconds
Started Jul 04 04:52:27 PM PDT 24
Finished Jul 04 04:52:39 PM PDT 24
Peak memory 204624 kb
Host smart-963d24ca-7e32-4e5f-bcce-2518c4b48e56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886385117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2886385117
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.62227355
Short name T1196
Test name
Test status
Simulation time 7039573049 ps
CPU time 37.64 seconds
Started Jul 04 04:52:23 PM PDT 24
Finished Jul 04 04:53:01 PM PDT 24
Peak memory 344224 kb
Host smart-62443cf7-ee58-4442-a339-1e420ce94f1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62227355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_stretch.62227355
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.2163689236
Short name T212
Test name
Test status
Simulation time 2171847073 ps
CPU time 7.11 seconds
Started Jul 04 04:52:27 PM PDT 24
Finished Jul 04 04:52:34 PM PDT 24
Peak memory 221032 kb
Host smart-73308f3d-a530-4f65-bbd6-cff8877c5554
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163689236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.2163689236
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.240006498
Short name T936
Test name
Test status
Simulation time 63310125 ps
CPU time 1.44 seconds
Started Jul 04 04:52:22 PM PDT 24
Finished Jul 04 04:52:24 PM PDT 24
Peak memory 204732 kb
Host smart-267d77de-7406-48f3-a675-0bb869523763
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240006498 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.240006498
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2356760543
Short name T1142
Test name
Test status
Simulation time 43040048 ps
CPU time 0.62 seconds
Started Jul 04 04:57:25 PM PDT 24
Finished Jul 04 04:57:26 PM PDT 24
Peak memory 204356 kb
Host smart-b1db367a-eaab-4122-9d95-c0d154edee65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356760543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2356760543
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3665895761
Short name T846
Test name
Test status
Simulation time 168968687 ps
CPU time 1.26 seconds
Started Jul 04 04:57:21 PM PDT 24
Finished Jul 04 04:57:22 PM PDT 24
Peak memory 212960 kb
Host smart-87731005-2579-4716-ab83-4581ad63b240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665895761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3665895761
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.443972618
Short name T414
Test name
Test status
Simulation time 1220796677 ps
CPU time 7.83 seconds
Started Jul 04 04:57:18 PM PDT 24
Finished Jul 04 04:57:26 PM PDT 24
Peak memory 276188 kb
Host smart-ac98dac8-5b85-44d4-bd36-e3395bdc87b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443972618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empt
y.443972618
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.4021251321
Short name T1298
Test name
Test status
Simulation time 10923012381 ps
CPU time 197.46 seconds
Started Jul 04 04:57:16 PM PDT 24
Finished Jul 04 05:00:34 PM PDT 24
Peak memory 847096 kb
Host smart-2d467a38-2529-41c3-aef9-d4fb97a57420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021251321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.4021251321
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.1050795544
Short name T335
Test name
Test status
Simulation time 8361192519 ps
CPU time 70.62 seconds
Started Jul 04 04:57:19 PM PDT 24
Finished Jul 04 04:58:30 PM PDT 24
Peak memory 707940 kb
Host smart-929ebfbe-56d1-4967-8554-0c2f5ed83f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050795544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1050795544
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3380702568
Short name T1290
Test name
Test status
Simulation time 102443504 ps
CPU time 0.94 seconds
Started Jul 04 04:57:19 PM PDT 24
Finished Jul 04 04:57:20 PM PDT 24
Peak memory 204312 kb
Host smart-811c4a44-b062-406a-8003-87d335ed2db8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380702568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3380702568
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2104255295
Short name T1388
Test name
Test status
Simulation time 346276016 ps
CPU time 4.16 seconds
Started Jul 04 04:57:19 PM PDT 24
Finished Jul 04 04:57:24 PM PDT 24
Peak memory 204732 kb
Host smart-1348e580-a1c8-43ae-a5c4-87f15e1d6328
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104255295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.2104255295
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.423901573
Short name T329
Test name
Test status
Simulation time 4293215640 ps
CPU time 122.31 seconds
Started Jul 04 04:57:17 PM PDT 24
Finished Jul 04 04:59:20 PM PDT 24
Peak memory 1242208 kb
Host smart-fe167e7c-fed0-468c-a6f3-d7a24ec24b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423901573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.423901573
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.4090508180
Short name T705
Test name
Test status
Simulation time 623806636 ps
CPU time 11.82 seconds
Started Jul 04 04:57:23 PM PDT 24
Finished Jul 04 04:57:35 PM PDT 24
Peak memory 204704 kb
Host smart-fa8c590a-3524-4937-9087-9122b0187e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090508180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.4090508180
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.4282304060
Short name T579
Test name
Test status
Simulation time 1736902642 ps
CPU time 32.16 seconds
Started Jul 04 04:57:26 PM PDT 24
Finished Jul 04 04:57:59 PM PDT 24
Peak memory 348904 kb
Host smart-fcb1acc8-4183-4436-b780-a0753e196dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282304060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.4282304060
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.2815822461
Short name T1307
Test name
Test status
Simulation time 29451108 ps
CPU time 0.74 seconds
Started Jul 04 04:57:18 PM PDT 24
Finished Jul 04 04:57:19 PM PDT 24
Peak memory 204416 kb
Host smart-7f1754a7-5d88-4f6a-921c-df7b98d686b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815822461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2815822461
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3996923001
Short name T1385
Test name
Test status
Simulation time 2558483313 ps
CPU time 28.43 seconds
Started Jul 04 04:57:17 PM PDT 24
Finished Jul 04 04:57:45 PM PDT 24
Peak memory 226252 kb
Host smart-84d26985-8e95-480e-a794-e18a93274694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996923001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3996923001
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.4070766705
Short name T1143
Test name
Test status
Simulation time 2426480725 ps
CPU time 19.14 seconds
Started Jul 04 04:57:17 PM PDT 24
Finished Jul 04 04:57:37 PM PDT 24
Peak memory 205472 kb
Host smart-3c06684d-543d-4c08-a583-aa6df4c327cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070766705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.4070766705
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.4000479523
Short name T520
Test name
Test status
Simulation time 1916494471 ps
CPU time 37.36 seconds
Started Jul 04 04:57:18 PM PDT 24
Finished Jul 04 04:57:55 PM PDT 24
Peak memory 349992 kb
Host smart-3c914338-8347-48c4-9e8c-090bf31a89ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000479523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.4000479523
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.4206858794
Short name T280
Test name
Test status
Simulation time 78258811198 ps
CPU time 955.16 seconds
Started Jul 04 04:57:18 PM PDT 24
Finished Jul 04 05:13:13 PM PDT 24
Peak memory 2541476 kb
Host smart-bef6565e-2645-4bfb-ade9-051943f673c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206858794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.4206858794
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.2259901204
Short name T1199
Test name
Test status
Simulation time 3612249557 ps
CPU time 14.56 seconds
Started Jul 04 04:57:17 PM PDT 24
Finished Jul 04 04:57:32 PM PDT 24
Peak memory 220032 kb
Host smart-604417ce-0697-4cea-8873-eb46be9d1c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259901204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.2259901204
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.2304682082
Short name T814
Test name
Test status
Simulation time 847337103 ps
CPU time 4.15 seconds
Started Jul 04 04:57:27 PM PDT 24
Finished Jul 04 04:57:31 PM PDT 24
Peak memory 212912 kb
Host smart-11c8d67e-0500-4fbd-af84-3cdf3ddb0917
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304682082 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2304682082
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2812173728
Short name T327
Test name
Test status
Simulation time 1262317588 ps
CPU time 1.27 seconds
Started Jul 04 04:57:24 PM PDT 24
Finished Jul 04 04:57:25 PM PDT 24
Peak memory 204832 kb
Host smart-3bb9ae96-d030-4726-9605-52a5373fbf4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812173728 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2812173728
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.2119540899
Short name T125
Test name
Test status
Simulation time 264442466 ps
CPU time 1.54 seconds
Started Jul 04 04:57:30 PM PDT 24
Finished Jul 04 04:57:31 PM PDT 24
Peak memory 212904 kb
Host smart-c505bf06-a896-4733-baee-3739218a4c97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119540899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.2119540899
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.1363969690
Short name T970
Test name
Test status
Simulation time 4725022097 ps
CPU time 2.39 seconds
Started Jul 04 04:57:25 PM PDT 24
Finished Jul 04 04:57:28 PM PDT 24
Peak memory 204932 kb
Host smart-9e64e6ee-2796-47e6-9779-819430a3effa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363969690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.1363969690
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.3444773534
Short name T988
Test name
Test status
Simulation time 311880842 ps
CPU time 1.34 seconds
Started Jul 04 04:57:25 PM PDT 24
Finished Jul 04 04:57:27 PM PDT 24
Peak memory 204464 kb
Host smart-6735a7f0-702d-4680-b8cf-9d2b4435f08e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444773534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.3444773534
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.528308199
Short name T1030
Test name
Test status
Simulation time 5468256446 ps
CPU time 7.72 seconds
Started Jul 04 04:57:25 PM PDT 24
Finished Jul 04 04:57:33 PM PDT 24
Peak memory 204904 kb
Host smart-6b3d7a37-579c-4b64-be6f-271029277a93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528308199 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_intr_smoke.528308199
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.1047949514
Short name T658
Test name
Test status
Simulation time 16286972612 ps
CPU time 206.09 seconds
Started Jul 04 04:57:25 PM PDT 24
Finished Jul 04 05:00:52 PM PDT 24
Peak memory 2497272 kb
Host smart-f3861b44-5dec-4986-9fa7-4c7d1459ae0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047949514 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.1047949514
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.1242385400
Short name T1060
Test name
Test status
Simulation time 670999514 ps
CPU time 24.64 seconds
Started Jul 04 04:57:20 PM PDT 24
Finished Jul 04 04:57:44 PM PDT 24
Peak memory 204660 kb
Host smart-0c278b31-9e4a-495d-a124-b626894a229b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242385400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.1242385400
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2341559027
Short name T680
Test name
Test status
Simulation time 474631685 ps
CPU time 19.2 seconds
Started Jul 04 04:57:17 PM PDT 24
Finished Jul 04 04:57:37 PM PDT 24
Peak memory 204740 kb
Host smart-d2bd34af-3403-4e6e-a13c-df77576be467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341559027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2341559027
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.1681971193
Short name T1474
Test name
Test status
Simulation time 60569490899 ps
CPU time 183.01 seconds
Started Jul 04 04:57:20 PM PDT 24
Finished Jul 04 05:00:23 PM PDT 24
Peak memory 2130496 kb
Host smart-462e8581-020f-4c07-8d21-b28abf8ff395
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681971193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.1681971193
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.3263209887
Short name T796
Test name
Test status
Simulation time 27757395682 ps
CPU time 406.61 seconds
Started Jul 04 04:57:25 PM PDT 24
Finished Jul 04 05:04:12 PM PDT 24
Peak memory 1407792 kb
Host smart-ad847c0c-968e-460c-9a38-eca928327f5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263209887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.3263209887
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1662784569
Short name T1265
Test name
Test status
Simulation time 6167353374 ps
CPU time 7.24 seconds
Started Jul 04 04:57:24 PM PDT 24
Finished Jul 04 04:57:31 PM PDT 24
Peak memory 221136 kb
Host smart-ce9efb6e-0bb3-4c46-8a33-2a07fb261c5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662784569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1662784569
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.6707939
Short name T1349
Test name
Test status
Simulation time 272442557 ps
CPU time 2.96 seconds
Started Jul 04 04:57:30 PM PDT 24
Finished Jul 04 04:57:33 PM PDT 24
Peak memory 204708 kb
Host smart-b052910f-54ee-4cce-8918-5ff6a7a43a9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6707939 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_tx_stretch_ctrl.6707939
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.2282015530
Short name T339
Test name
Test status
Simulation time 37604513 ps
CPU time 0.63 seconds
Started Jul 04 04:57:31 PM PDT 24
Finished Jul 04 04:57:32 PM PDT 24
Peak memory 204372 kb
Host smart-84ab99e3-5673-40be-b3f7-f02cfbe0ed48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282015530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2282015530
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.513439325
Short name T908
Test name
Test status
Simulation time 313585304 ps
CPU time 1.76 seconds
Started Jul 04 04:57:36 PM PDT 24
Finished Jul 04 04:57:38 PM PDT 24
Peak memory 204824 kb
Host smart-9685d87f-4656-4e6c-b812-cbf9f6ec597f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513439325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.513439325
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.122040004
Short name T1466
Test name
Test status
Simulation time 244863041 ps
CPU time 3.97 seconds
Started Jul 04 04:57:28 PM PDT 24
Finished Jul 04 04:57:32 PM PDT 24
Peak memory 238216 kb
Host smart-17ddb64a-2ff7-4dcb-b248-8f58a621f32b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122040004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empt
y.122040004
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.644280615
Short name T46
Test name
Test status
Simulation time 12369551786 ps
CPU time 120.09 seconds
Started Jul 04 04:57:25 PM PDT 24
Finished Jul 04 04:59:25 PM PDT 24
Peak memory 946800 kb
Host smart-69649489-cedb-4148-b42d-52bc0b5d82a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644280615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.644280615
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.4201017017
Short name T573
Test name
Test status
Simulation time 5553864436 ps
CPU time 40.41 seconds
Started Jul 04 04:57:26 PM PDT 24
Finished Jul 04 04:58:07 PM PDT 24
Peak memory 465108 kb
Host smart-a4346187-218b-4523-9c70-4b84db03580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201017017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.4201017017
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3549089897
Short name T1184
Test name
Test status
Simulation time 84813693 ps
CPU time 0.87 seconds
Started Jul 04 04:57:26 PM PDT 24
Finished Jul 04 04:57:27 PM PDT 24
Peak memory 204356 kb
Host smart-a637dc67-01ed-4b24-b832-2542ac0dc230
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549089897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3549089897
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.583685963
Short name T1507
Test name
Test status
Simulation time 286483526 ps
CPU time 4.58 seconds
Started Jul 04 04:57:25 PM PDT 24
Finished Jul 04 04:57:30 PM PDT 24
Peak memory 230388 kb
Host smart-eb3a8b57-023d-46c6-bc64-0cf3fd85aecc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583685963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.
583685963
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2720059982
Short name T383
Test name
Test status
Simulation time 22109401956 ps
CPU time 162.21 seconds
Started Jul 04 04:57:23 PM PDT 24
Finished Jul 04 05:00:05 PM PDT 24
Peak memory 1521088 kb
Host smart-8cb07c63-fb76-4afb-af7d-47dafecaff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720059982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2720059982
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.2569380902
Short name T987
Test name
Test status
Simulation time 1022385495 ps
CPU time 11.15 seconds
Started Jul 04 04:57:33 PM PDT 24
Finished Jul 04 04:57:45 PM PDT 24
Peak memory 204616 kb
Host smart-b09009fb-7717-4ca7-93c1-2731eeb53c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569380902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.2569380902
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1112066913
Short name T77
Test name
Test status
Simulation time 1328933683 ps
CPU time 62.44 seconds
Started Jul 04 04:57:29 PM PDT 24
Finished Jul 04 04:58:32 PM PDT 24
Peak memory 334280 kb
Host smart-6e0641e4-67f5-4ba7-8f35-fd0ff7a26511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112066913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1112066913
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.845970941
Short name T152
Test name
Test status
Simulation time 52039528 ps
CPU time 0.72 seconds
Started Jul 04 04:57:26 PM PDT 24
Finished Jul 04 04:57:27 PM PDT 24
Peak memory 204440 kb
Host smart-df22f1e7-3316-44b8-9c91-310d1c69bd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845970941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.845970941
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.777570938
Short name T1210
Test name
Test status
Simulation time 51441808910 ps
CPU time 495.53 seconds
Started Jul 04 04:57:25 PM PDT 24
Finished Jul 04 05:05:41 PM PDT 24
Peak memory 221104 kb
Host smart-208c5986-8c5c-4bfe-b2d1-48da5361ba16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777570938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.777570938
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.4107447887
Short name T432
Test name
Test status
Simulation time 288344306 ps
CPU time 2.9 seconds
Started Jul 04 04:57:24 PM PDT 24
Finished Jul 04 04:57:27 PM PDT 24
Peak memory 220868 kb
Host smart-142eee25-151c-4ed0-a276-8faca159167a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107447887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.4107447887
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.238592458
Short name T287
Test name
Test status
Simulation time 2605245457 ps
CPU time 23.19 seconds
Started Jul 04 04:57:25 PM PDT 24
Finished Jul 04 04:57:48 PM PDT 24
Peak memory 335716 kb
Host smart-6073fdce-8dd4-450f-b460-16042cf39818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238592458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.238592458
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.1851388112
Short name T1489
Test name
Test status
Simulation time 99126240652 ps
CPU time 1391.08 seconds
Started Jul 04 04:57:31 PM PDT 24
Finished Jul 04 05:20:43 PM PDT 24
Peak memory 3386984 kb
Host smart-bc8622b8-f28c-424f-a09e-e1b0a82d0735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851388112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.1851388112
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.4072081356
Short name T581
Test name
Test status
Simulation time 741822292 ps
CPU time 16.24 seconds
Started Jul 04 04:57:29 PM PDT 24
Finished Jul 04 04:57:46 PM PDT 24
Peak memory 212948 kb
Host smart-760e6637-bd43-4a48-9939-7c33de4052bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072081356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.4072081356
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.1904485916
Short name T1252
Test name
Test status
Simulation time 624119603 ps
CPU time 3.59 seconds
Started Jul 04 04:57:36 PM PDT 24
Finished Jul 04 04:57:40 PM PDT 24
Peak memory 212900 kb
Host smart-37cc7b55-9aae-48c8-b5da-a1fcc705dac6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904485916 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.1904485916
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.931803537
Short name T334
Test name
Test status
Simulation time 258377711 ps
CPU time 1.54 seconds
Started Jul 04 04:57:35 PM PDT 24
Finished Jul 04 04:57:37 PM PDT 24
Peak memory 204708 kb
Host smart-2e4e8776-759c-453e-b74d-5397b280a6b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931803537 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.931803537
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.89310562
Short name T1346
Test name
Test status
Simulation time 788839936 ps
CPU time 1.4 seconds
Started Jul 04 04:57:34 PM PDT 24
Finished Jul 04 04:57:35 PM PDT 24
Peak memory 204700 kb
Host smart-8c64d66f-5c7e-48b8-9401-40243622df90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89310562 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_fifo_reset_tx.89310562
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.1308430476
Short name T1187
Test name
Test status
Simulation time 3063076991 ps
CPU time 2.68 seconds
Started Jul 04 04:57:31 PM PDT 24
Finished Jul 04 04:57:33 PM PDT 24
Peak memory 204764 kb
Host smart-51404c05-5a64-45ae-b564-c7eaf41b60e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308430476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.1308430476
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.789996719
Short name T979
Test name
Test status
Simulation time 365681990 ps
CPU time 1.04 seconds
Started Jul 04 04:57:36 PM PDT 24
Finished Jul 04 04:57:37 PM PDT 24
Peak memory 204500 kb
Host smart-cd02d61b-5f9c-4288-a20e-0804b38035b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789996719 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.789996719
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.3400567896
Short name T1212
Test name
Test status
Simulation time 1511484951 ps
CPU time 8.05 seconds
Started Jul 04 04:57:31 PM PDT 24
Finished Jul 04 04:57:40 PM PDT 24
Peak memory 219736 kb
Host smart-9b16e6df-5108-41a9-acbb-6796ec3169f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400567896 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.3400567896
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.1433481189
Short name T626
Test name
Test status
Simulation time 17203556024 ps
CPU time 334.65 seconds
Started Jul 04 04:57:33 PM PDT 24
Finished Jul 04 05:03:08 PM PDT 24
Peak memory 4247704 kb
Host smart-17131e14-e8b3-4872-a8e2-aa1a63bf0fc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433481189 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.1433481189
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.316355443
Short name T982
Test name
Test status
Simulation time 830576471 ps
CPU time 11.33 seconds
Started Jul 04 04:57:33 PM PDT 24
Finished Jul 04 04:57:44 PM PDT 24
Peak memory 204692 kb
Host smart-f897c427-eff7-4532-ad73-3ea8be287466
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316355443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_tar
get_smoke.316355443
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.1988551982
Short name T1299
Test name
Test status
Simulation time 6607019571 ps
CPU time 10.93 seconds
Started Jul 04 04:57:34 PM PDT 24
Finished Jul 04 04:57:45 PM PDT 24
Peak memory 214716 kb
Host smart-e9418585-b450-452b-84d0-6d31492d8d91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988551982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.1988551982
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.658405312
Short name T858
Test name
Test status
Simulation time 33161731542 ps
CPU time 157.81 seconds
Started Jul 04 04:57:36 PM PDT 24
Finished Jul 04 05:00:14 PM PDT 24
Peak memory 2183592 kb
Host smart-3e996d02-ecf5-4715-84cd-6ebd2dc9bb75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658405312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_wr.658405312
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.3114729652
Short name T1392
Test name
Test status
Simulation time 5734012839 ps
CPU time 170.62 seconds
Started Jul 04 04:57:35 PM PDT 24
Finished Jul 04 05:00:26 PM PDT 24
Peak memory 1541556 kb
Host smart-225e3aff-07de-4527-8840-650e4554516f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114729652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.3114729652
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2830538760
Short name T650
Test name
Test status
Simulation time 1349295983 ps
CPU time 8.21 seconds
Started Jul 04 04:57:33 PM PDT 24
Finished Jul 04 04:57:41 PM PDT 24
Peak memory 220984 kb
Host smart-215b01d8-ee1d-4275-ab1e-ec6628a2b9ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830538760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2830538760
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.781553006
Short name T1434
Test name
Test status
Simulation time 270948086 ps
CPU time 3.71 seconds
Started Jul 04 04:57:36 PM PDT 24
Finished Jul 04 04:57:40 PM PDT 24
Peak memory 204696 kb
Host smart-bcdbf1d7-5f6c-4d34-a18e-c2eb47f1ef99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781553006 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.781553006
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.3646403771
Short name T381
Test name
Test status
Simulation time 16548865 ps
CPU time 0.65 seconds
Started Jul 04 04:57:45 PM PDT 24
Finished Jul 04 04:57:46 PM PDT 24
Peak memory 204456 kb
Host smart-e1e09a1e-7627-4ae9-832e-3022f4b1ac2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646403771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3646403771
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.4138581784
Short name T123
Test name
Test status
Simulation time 376548330 ps
CPU time 1.71 seconds
Started Jul 04 04:57:37 PM PDT 24
Finished Jul 04 04:57:40 PM PDT 24
Peak memory 212964 kb
Host smart-59b53176-9a9c-4101-b40f-5f59db5749ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138581784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.4138581784
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.437844452
Short name T1517
Test name
Test status
Simulation time 1153005706 ps
CPU time 5.83 seconds
Started Jul 04 04:57:33 PM PDT 24
Finished Jul 04 04:57:39 PM PDT 24
Peak memory 267628 kb
Host smart-ec538d74-b483-4023-892f-70e5a5ea39b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437844452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.437844452
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.1146244
Short name T637
Test name
Test status
Simulation time 9056243233 ps
CPU time 79.45 seconds
Started Jul 04 04:57:36 PM PDT 24
Finished Jul 04 04:58:56 PM PDT 24
Peak memory 750248 kb
Host smart-78ea0ad1-8caf-4e77-b77e-57bc6ee03368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1146244
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.3854708737
Short name T415
Test name
Test status
Simulation time 6500440544 ps
CPU time 115.73 seconds
Started Jul 04 04:57:34 PM PDT 24
Finished Jul 04 04:59:30 PM PDT 24
Peak memory 578000 kb
Host smart-4ce17242-2d6b-416a-9aa0-0d9001e56172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854708737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.3854708737
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.1606056819
Short name T431
Test name
Test status
Simulation time 713293270 ps
CPU time 0.98 seconds
Started Jul 04 04:57:31 PM PDT 24
Finished Jul 04 04:57:32 PM PDT 24
Peak memory 204440 kb
Host smart-aa5bbaa3-820f-492b-b21a-875d07f436c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606056819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.1606056819
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3345244422
Short name T1326
Test name
Test status
Simulation time 585329846 ps
CPU time 8.98 seconds
Started Jul 04 04:57:39 PM PDT 24
Finished Jul 04 04:57:49 PM PDT 24
Peak memory 231468 kb
Host smart-74b443ba-4025-424d-853c-a7d2df91e2b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345244422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3345244422
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3179682353
Short name T182
Test name
Test status
Simulation time 66088663109 ps
CPU time 290.57 seconds
Started Jul 04 04:57:32 PM PDT 24
Finished Jul 04 05:02:23 PM PDT 24
Peak memory 1193908 kb
Host smart-586ff986-de2d-4181-be58-2ddeeca3cdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179682353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3179682353
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.2429149315
Short name T1063
Test name
Test status
Simulation time 2297590099 ps
CPU time 14.82 seconds
Started Jul 04 04:57:37 PM PDT 24
Finished Jul 04 04:57:52 PM PDT 24
Peak memory 205192 kb
Host smart-3909e73d-254b-40c0-9087-7c8b80cc0dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429149315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.2429149315
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_override.2621819138
Short name T780
Test name
Test status
Simulation time 26744242 ps
CPU time 0.7 seconds
Started Jul 04 04:57:32 PM PDT 24
Finished Jul 04 04:57:33 PM PDT 24
Peak memory 204420 kb
Host smart-f262cd6d-ef40-4e6b-a4f3-0113488c6fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621819138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2621819138
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.241592433
Short name T1186
Test name
Test status
Simulation time 6129625219 ps
CPU time 58.57 seconds
Started Jul 04 04:57:38 PM PDT 24
Finished Jul 04 04:58:37 PM PDT 24
Peak memory 213112 kb
Host smart-9894c2c7-92fa-45ba-9338-49dc697a6ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241592433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.241592433
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.486884266
Short name T291
Test name
Test status
Simulation time 378681575 ps
CPU time 2.56 seconds
Started Jul 04 04:57:37 PM PDT 24
Finished Jul 04 04:57:40 PM PDT 24
Peak memory 204644 kb
Host smart-97648819-3596-4a4f-9567-ea9354f113cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486884266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.486884266
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.4133511923
Short name T1266
Test name
Test status
Simulation time 11447191082 ps
CPU time 104.59 seconds
Started Jul 04 04:57:33 PM PDT 24
Finished Jul 04 04:59:18 PM PDT 24
Peak memory 438292 kb
Host smart-f09ab68f-565e-4390-b2f5-20bb7aa5cee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133511923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.4133511923
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.241723962
Short name T855
Test name
Test status
Simulation time 2972111331 ps
CPU time 32.22 seconds
Started Jul 04 04:57:41 PM PDT 24
Finished Jul 04 04:58:14 PM PDT 24
Peak memory 212604 kb
Host smart-f0973deb-c99f-466e-b464-b5afe64622d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241723962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.241723962
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.455184578
Short name T868
Test name
Test status
Simulation time 3189798663 ps
CPU time 4.44 seconds
Started Jul 04 04:57:37 PM PDT 24
Finished Jul 04 04:57:42 PM PDT 24
Peak memory 212956 kb
Host smart-fee0277b-e2f3-4f3e-989d-76c67de93ea3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455184578 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.455184578
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.2835800372
Short name T1033
Test name
Test status
Simulation time 406169707 ps
CPU time 1.19 seconds
Started Jul 04 04:57:37 PM PDT 24
Finished Jul 04 04:57:39 PM PDT 24
Peak memory 212900 kb
Host smart-03e597fa-55b8-4cf4-a4ac-988cebfec997
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835800372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.2835800372
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.3745339855
Short name T766
Test name
Test status
Simulation time 637788826 ps
CPU time 0.92 seconds
Started Jul 04 04:57:36 PM PDT 24
Finished Jul 04 04:57:37 PM PDT 24
Peak memory 204524 kb
Host smart-714d2e7c-e5f4-4546-a6a9-ce2c6680cf90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745339855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.3745339855
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.301523731
Short name T964
Test name
Test status
Simulation time 427766511 ps
CPU time 2.4 seconds
Started Jul 04 04:57:37 PM PDT 24
Finished Jul 04 04:57:40 PM PDT 24
Peak memory 204816 kb
Host smart-7b868336-adeb-4440-a33b-9f24e5bbd52e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301523731 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.301523731
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.3195358431
Short name T633
Test name
Test status
Simulation time 127834200 ps
CPU time 1.17 seconds
Started Jul 04 04:57:46 PM PDT 24
Finished Jul 04 04:57:48 PM PDT 24
Peak memory 204500 kb
Host smart-f87051e1-c800-4d8c-a091-fa1e45b63d99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195358431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.3195358431
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.2205249592
Short name T874
Test name
Test status
Simulation time 267031518 ps
CPU time 3.4 seconds
Started Jul 04 04:57:39 PM PDT 24
Finished Jul 04 04:57:43 PM PDT 24
Peak memory 204744 kb
Host smart-feee6e88-201b-46e8-a8a2-856712f43bf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205249592 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.2205249592
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2203743190
Short name T1374
Test name
Test status
Simulation time 3462574056 ps
CPU time 4.93 seconds
Started Jul 04 04:57:41 PM PDT 24
Finished Jul 04 04:57:46 PM PDT 24
Peak memory 212580 kb
Host smart-f058b590-2dc4-4a8e-9f65-235c4843a9fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203743190 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2203743190
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.695057174
Short name T355
Test name
Test status
Simulation time 12143080501 ps
CPU time 7.16 seconds
Started Jul 04 04:57:39 PM PDT 24
Finished Jul 04 04:57:46 PM PDT 24
Peak memory 217036 kb
Host smart-f1f54b21-4b0a-4ba9-b6d4-ec98496eb0bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695057174 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.695057174
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.3380670264
Short name T1522
Test name
Test status
Simulation time 1169746636 ps
CPU time 17.38 seconds
Started Jul 04 04:57:42 PM PDT 24
Finished Jul 04 04:57:59 PM PDT 24
Peak memory 204712 kb
Host smart-50f65ec3-f4c7-4fcf-812f-2652a39fbae8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380670264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.3380670264
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.361517054
Short name T1044
Test name
Test status
Simulation time 1194328976 ps
CPU time 10.83 seconds
Started Jul 04 04:57:38 PM PDT 24
Finished Jul 04 04:57:49 PM PDT 24
Peak memory 209016 kb
Host smart-c0212d98-3a27-4630-9cf4-e413929fbded
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361517054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.361517054
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.161833566
Short name T1005
Test name
Test status
Simulation time 51095978837 ps
CPU time 126.52 seconds
Started Jul 04 04:57:42 PM PDT 24
Finished Jul 04 04:59:48 PM PDT 24
Peak memory 1773548 kb
Host smart-8d673fa9-d5f8-4cef-9487-e0e7ae1e2bcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161833566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_wr.161833566
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.3549013001
Short name T824
Test name
Test status
Simulation time 41291828796 ps
CPU time 813.73 seconds
Started Jul 04 04:57:39 PM PDT 24
Finished Jul 04 05:11:14 PM PDT 24
Peak memory 4463800 kb
Host smart-09efb71d-1895-44ad-8660-d3443d041c02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549013001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.3549013001
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.765979808
Short name T834
Test name
Test status
Simulation time 1273849321 ps
CPU time 6.73 seconds
Started Jul 04 04:57:39 PM PDT 24
Finished Jul 04 04:57:46 PM PDT 24
Peak memory 214580 kb
Host smart-4a299ba0-78c2-48e2-8573-6461b610e0c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765979808 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_timeout.765979808
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.3617446747
Short name T924
Test name
Test status
Simulation time 216857251 ps
CPU time 3.53 seconds
Started Jul 04 04:57:46 PM PDT 24
Finished Jul 04 04:57:50 PM PDT 24
Peak memory 213600 kb
Host smart-cbe22366-3036-4bf8-b8f0-747fd77f2c86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617446747 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.3617446747
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1484286079
Short name T1316
Test name
Test status
Simulation time 17954923 ps
CPU time 0.63 seconds
Started Jul 04 04:57:57 PM PDT 24
Finished Jul 04 04:57:57 PM PDT 24
Peak memory 204376 kb
Host smart-a8bd2d02-2ebd-46bb-ae65-4319eb5826f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484286079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1484286079
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.943421636
Short name T804
Test name
Test status
Simulation time 179786997 ps
CPU time 1.15 seconds
Started Jul 04 04:57:49 PM PDT 24
Finished Jul 04 04:57:50 PM PDT 24
Peak memory 212988 kb
Host smart-19997e70-6bb4-428d-80eb-41f26568b2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943421636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.943421636
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.3566747078
Short name T1436
Test name
Test status
Simulation time 910060764 ps
CPU time 3.84 seconds
Started Jul 04 04:57:45 PM PDT 24
Finished Jul 04 04:57:49 PM PDT 24
Peak memory 229764 kb
Host smart-695537eb-2672-4e7e-a205-a1ab6970f84f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566747078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.3566747078
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.2741129011
Short name T163
Test name
Test status
Simulation time 3981878071 ps
CPU time 72.23 seconds
Started Jul 04 04:57:46 PM PDT 24
Finished Jul 04 04:58:58 PM PDT 24
Peak memory 703588 kb
Host smart-d3f5f396-a342-418a-87d2-c7b53e0fc1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741129011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2741129011
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.3436533311
Short name T967
Test name
Test status
Simulation time 2757970973 ps
CPU time 83.09 seconds
Started Jul 04 04:57:46 PM PDT 24
Finished Jul 04 04:59:09 PM PDT 24
Peak memory 781612 kb
Host smart-8b158de1-4677-496a-9e0b-cbed4aa7fb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436533311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.3436533311
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.4022279883
Short name T871
Test name
Test status
Simulation time 301494555 ps
CPU time 0.79 seconds
Started Jul 04 04:57:46 PM PDT 24
Finished Jul 04 04:57:47 PM PDT 24
Peak memory 204348 kb
Host smart-f07a9a29-6e13-49c7-9cea-321a26ae2d07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022279883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.4022279883
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.590557777
Short name T939
Test name
Test status
Simulation time 867130215 ps
CPU time 5.57 seconds
Started Jul 04 04:57:47 PM PDT 24
Finished Jul 04 04:57:52 PM PDT 24
Peak memory 204680 kb
Host smart-2c874dac-d64e-4807-bf8e-fc48655dee83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590557777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.
590557777
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2153944616
Short name T921
Test name
Test status
Simulation time 15782373187 ps
CPU time 88.55 seconds
Started Jul 04 04:57:47 PM PDT 24
Finished Jul 04 04:59:16 PM PDT 24
Peak memory 1151760 kb
Host smart-13b551ee-70af-4a6e-a3fa-1de99108aa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153944616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2153944616
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.1501482679
Short name T1433
Test name
Test status
Simulation time 563250773 ps
CPU time 9.22 seconds
Started Jul 04 04:57:52 PM PDT 24
Finished Jul 04 04:58:01 PM PDT 24
Peak memory 204644 kb
Host smart-58a85748-b4ff-4abe-b164-87de7a87cdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501482679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.1501482679
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.29691318
Short name T1526
Test name
Test status
Simulation time 9229119854 ps
CPU time 33.74 seconds
Started Jul 04 04:57:52 PM PDT 24
Finished Jul 04 04:58:26 PM PDT 24
Peak memory 335980 kb
Host smart-721d721a-ae7b-4c1d-83b9-b3ae2f9616dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29691318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.29691318
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.1885556409
Short name T1080
Test name
Test status
Simulation time 16463861 ps
CPU time 0.67 seconds
Started Jul 04 04:57:48 PM PDT 24
Finished Jul 04 04:57:48 PM PDT 24
Peak memory 204360 kb
Host smart-8ea0893f-75d6-44dd-b3fd-c6f3f2eb219e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885556409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1885556409
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.2748410049
Short name T1486
Test name
Test status
Simulation time 26767552404 ps
CPU time 475.06 seconds
Started Jul 04 04:57:46 PM PDT 24
Finished Jul 04 05:05:41 PM PDT 24
Peak memory 908668 kb
Host smart-61bca325-d5b6-4c66-95ac-1ade74231dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748410049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.2748410049
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.581279657
Short name T1428
Test name
Test status
Simulation time 676780322 ps
CPU time 14.78 seconds
Started Jul 04 04:57:46 PM PDT 24
Finished Jul 04 04:58:01 PM PDT 24
Peak memory 212788 kb
Host smart-7ec3748f-2a5c-40db-a169-782eaceb4ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581279657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.581279657
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2560445340
Short name T1237
Test name
Test status
Simulation time 1573432310 ps
CPU time 23.46 seconds
Started Jul 04 04:57:48 PM PDT 24
Finished Jul 04 04:58:11 PM PDT 24
Peak memory 343548 kb
Host smart-96e1dec0-1236-4f37-911c-3c1e9f346aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560445340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2560445340
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.2019243690
Short name T753
Test name
Test status
Simulation time 85564002013 ps
CPU time 1484.13 seconds
Started Jul 04 04:57:46 PM PDT 24
Finished Jul 04 05:22:30 PM PDT 24
Peak memory 1902084 kb
Host smart-c24b2702-2995-4701-983c-ad65f58066b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019243690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.2019243690
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.909100872
Short name T735
Test name
Test status
Simulation time 6697761944 ps
CPU time 11.55 seconds
Started Jul 04 04:57:46 PM PDT 24
Finished Jul 04 04:57:58 PM PDT 24
Peak memory 221084 kb
Host smart-7a6ff9a5-7cac-419b-b279-a1ed40d8a48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909100872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.909100872
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.3640558793
Short name T347
Test name
Test status
Simulation time 982111403 ps
CPU time 4.66 seconds
Started Jul 04 04:57:57 PM PDT 24
Finished Jul 04 04:58:02 PM PDT 24
Peak memory 204708 kb
Host smart-e60f452a-c7d6-4f79-8497-0e1b2938cb40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640558793 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.3640558793
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.3937629443
Short name T447
Test name
Test status
Simulation time 174939391 ps
CPU time 1.14 seconds
Started Jul 04 04:57:46 PM PDT 24
Finished Jul 04 04:57:47 PM PDT 24
Peak memory 204532 kb
Host smart-c8aa8065-5c8f-4f92-8620-c5cde267edc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937629443 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.3937629443
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.2155033194
Short name T526
Test name
Test status
Simulation time 203318486 ps
CPU time 0.84 seconds
Started Jul 04 04:57:47 PM PDT 24
Finished Jul 04 04:57:48 PM PDT 24
Peak memory 204456 kb
Host smart-3c5004aa-11fd-41d1-8d0a-259d3fe9752a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155033194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.2155033194
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.53444772
Short name T1076
Test name
Test status
Simulation time 1269810159 ps
CPU time 2 seconds
Started Jul 04 04:57:59 PM PDT 24
Finished Jul 04 04:58:01 PM PDT 24
Peak memory 204704 kb
Host smart-43dd00a7-53b0-497c-a8ad-5687ffbaa7d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53444772 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.53444772
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.2565084618
Short name T168
Test name
Test status
Simulation time 81460680 ps
CPU time 0.78 seconds
Started Jul 04 04:57:53 PM PDT 24
Finished Jul 04 04:57:54 PM PDT 24
Peak memory 204452 kb
Host smart-a5679d5e-bfbf-4b9a-8b60-21e4237c22c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565084618 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.2565084618
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.529457286
Short name T693
Test name
Test status
Simulation time 232266142 ps
CPU time 3.14 seconds
Started Jul 04 04:57:57 PM PDT 24
Finished Jul 04 04:58:00 PM PDT 24
Peak memory 204628 kb
Host smart-2b971fa1-bd4e-4faa-9768-c9bb25edb317
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529457286 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.i2c_target_hrst.529457286
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3180254819
Short name T778
Test name
Test status
Simulation time 1091954017 ps
CPU time 5.69 seconds
Started Jul 04 04:57:47 PM PDT 24
Finished Jul 04 04:57:53 PM PDT 24
Peak memory 212900 kb
Host smart-a0e65ad4-da94-47e7-b9ba-21ade9539027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180254819 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3180254819
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.675024718
Short name T511
Test name
Test status
Simulation time 3856172952 ps
CPU time 5.4 seconds
Started Jul 04 04:57:45 PM PDT 24
Finished Jul 04 04:57:50 PM PDT 24
Peak memory 327688 kb
Host smart-36b6a7a3-4134-41d2-9a3a-7b2f7774bb82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675024718 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.675024718
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3345435688
Short name T1220
Test name
Test status
Simulation time 910137049 ps
CPU time 34.3 seconds
Started Jul 04 04:57:48 PM PDT 24
Finished Jul 04 04:58:22 PM PDT 24
Peak memory 204728 kb
Host smart-02cadc86-12f0-44d6-9f8c-8fbcd82bb8b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345435688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3345435688
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2557775611
Short name T325
Test name
Test status
Simulation time 823653123 ps
CPU time 36.02 seconds
Started Jul 04 04:57:48 PM PDT 24
Finished Jul 04 04:58:24 PM PDT 24
Peak memory 204708 kb
Host smart-dea328cd-5e09-41fa-9763-8a705eb9bb0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557775611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2557775611
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.888754752
Short name T313
Test name
Test status
Simulation time 55247981157 ps
CPU time 479.24 seconds
Started Jul 04 04:57:48 PM PDT 24
Finished Jul 04 05:05:47 PM PDT 24
Peak memory 4327404 kb
Host smart-7d62e71c-8d01-4df8-8ea9-abe86ebc296c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888754752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_wr.888754752
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.1301289829
Short name T1006
Test name
Test status
Simulation time 29175054959 ps
CPU time 503.26 seconds
Started Jul 04 04:57:46 PM PDT 24
Finished Jul 04 05:06:10 PM PDT 24
Peak memory 1742532 kb
Host smart-4b3d9c79-26fa-4cc9-b394-932d1d1e7244
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301289829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.1301289829
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.849435058
Short name T337
Test name
Test status
Simulation time 5191300431 ps
CPU time 7.2 seconds
Started Jul 04 04:57:46 PM PDT 24
Finished Jul 04 04:57:54 PM PDT 24
Peak memory 213644 kb
Host smart-9c969427-8017-4046-a897-16a875c79788
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849435058 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_timeout.849435058
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.1601586747
Short name T597
Test name
Test status
Simulation time 197698346 ps
CPU time 2.68 seconds
Started Jul 04 04:57:55 PM PDT 24
Finished Jul 04 04:57:58 PM PDT 24
Peak memory 204672 kb
Host smart-0f53ad70-f778-495c-af07-c5e9f022a13f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601586747 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.1601586747
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.3842503650
Short name T946
Test name
Test status
Simulation time 27870767 ps
CPU time 0.64 seconds
Started Jul 04 04:58:04 PM PDT 24
Finished Jul 04 04:58:05 PM PDT 24
Peak memory 204356 kb
Host smart-3adf0d47-b68f-4801-8788-e6700e0d5a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842503650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3842503650
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.1126072565
Short name T1215
Test name
Test status
Simulation time 1155525524 ps
CPU time 6.21 seconds
Started Jul 04 04:57:58 PM PDT 24
Finished Jul 04 04:58:04 PM PDT 24
Peak memory 259524 kb
Host smart-4b18d41a-e824-48f0-83f6-610110e4d8fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126072565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.1126072565
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2996939335
Short name T85
Test name
Test status
Simulation time 11175588736 ps
CPU time 192.43 seconds
Started Jul 04 04:57:52 PM PDT 24
Finished Jul 04 05:01:04 PM PDT 24
Peak memory 845760 kb
Host smart-7a8fe59c-277c-46b9-a791-0d70322b4861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996939335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2996939335
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2500404587
Short name T1479
Test name
Test status
Simulation time 8175473304 ps
CPU time 67.04 seconds
Started Jul 04 04:57:54 PM PDT 24
Finished Jul 04 04:59:01 PM PDT 24
Peak memory 621284 kb
Host smart-6c60ffbe-f34f-4781-9408-80cc722f066c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500404587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2500404587
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.64522731
Short name T690
Test name
Test status
Simulation time 509511117 ps
CPU time 0.97 seconds
Started Jul 04 04:57:54 PM PDT 24
Finished Jul 04 04:57:55 PM PDT 24
Peak memory 204360 kb
Host smart-64e59b38-9129-4d7d-b64e-600afeb4f9ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64522731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fmt
.64522731
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1716227216
Short name T1321
Test name
Test status
Simulation time 164206488 ps
CPU time 3.53 seconds
Started Jul 04 04:57:58 PM PDT 24
Finished Jul 04 04:58:02 PM PDT 24
Peak memory 204724 kb
Host smart-7880eb1f-97df-47d0-bc60-d9d56ea98d9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716227216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1716227216
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.3730785868
Short name T462
Test name
Test status
Simulation time 14123047044 ps
CPU time 317.13 seconds
Started Jul 04 04:57:53 PM PDT 24
Finished Jul 04 05:03:10 PM PDT 24
Peak memory 1126092 kb
Host smart-98e278bb-5f87-4b1b-a39d-16a240e00780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730785868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.3730785868
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.3429199211
Short name T371
Test name
Test status
Simulation time 1585360718 ps
CPU time 14.85 seconds
Started Jul 04 04:58:05 PM PDT 24
Finished Jul 04 04:58:20 PM PDT 24
Peak memory 204676 kb
Host smart-64951ca7-7a6b-4e35-84dd-62e364c81798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429199211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3429199211
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.935733851
Short name T603
Test name
Test status
Simulation time 2029482332 ps
CPU time 43.9 seconds
Started Jul 04 04:58:03 PM PDT 24
Finished Jul 04 04:58:47 PM PDT 24
Peak memory 517984 kb
Host smart-0ae8711a-e3d5-41bd-a4c6-bdd2ad84110d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935733851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.935733851
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.1534816707
Short name T720
Test name
Test status
Simulation time 44637263 ps
CPU time 0.71 seconds
Started Jul 04 04:57:50 PM PDT 24
Finished Jul 04 04:57:51 PM PDT 24
Peak memory 204420 kb
Host smart-242ec5a5-6813-4c09-a1c8-3048462eddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534816707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.1534816707
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.386185765
Short name T36
Test name
Test status
Simulation time 5312508354 ps
CPU time 58.78 seconds
Started Jul 04 04:57:59 PM PDT 24
Finished Jul 04 04:58:58 PM PDT 24
Peak memory 690512 kb
Host smart-2c34cf8a-bbd8-45a8-8281-a55fefc1cfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386185765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.386185765
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.1502494126
Short name T1364
Test name
Test status
Simulation time 98675033 ps
CPU time 1.31 seconds
Started Jul 04 04:57:51 PM PDT 24
Finished Jul 04 04:57:53 PM PDT 24
Peak memory 212948 kb
Host smart-ff3d68d0-f72a-4b9e-82af-84b3bdedeac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502494126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.1502494126
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.3080508144
Short name T332
Test name
Test status
Simulation time 35678337734 ps
CPU time 87.3 seconds
Started Jul 04 04:57:52 PM PDT 24
Finished Jul 04 04:59:20 PM PDT 24
Peak memory 372572 kb
Host smart-2aaf1d79-deb6-408a-9840-340f2dfe9796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080508144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3080508144
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.2927653420
Short name T1151
Test name
Test status
Simulation time 941126697 ps
CPU time 14.83 seconds
Started Jul 04 04:57:55 PM PDT 24
Finished Jul 04 04:58:10 PM PDT 24
Peak memory 221048 kb
Host smart-0d765b5f-8b02-4eea-8173-6645b3f279fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927653420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.2927653420
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.1945223223
Short name T956
Test name
Test status
Simulation time 281230002 ps
CPU time 1.62 seconds
Started Jul 04 04:58:01 PM PDT 24
Finished Jul 04 04:58:03 PM PDT 24
Peak memory 204740 kb
Host smart-660cabe0-87af-4411-8050-902040611b60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945223223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.1945223223
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.933194858
Short name T1011
Test name
Test status
Simulation time 2163016865 ps
CPU time 1.29 seconds
Started Jul 04 04:58:00 PM PDT 24
Finished Jul 04 04:58:01 PM PDT 24
Peak memory 204788 kb
Host smart-f3b8045f-c149-40bd-a842-af87e06762ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933194858 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_fifo_reset_tx.933194858
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.3118405058
Short name T405
Test name
Test status
Simulation time 1088443808 ps
CPU time 1.56 seconds
Started Jul 04 04:58:17 PM PDT 24
Finished Jul 04 04:58:19 PM PDT 24
Peak memory 204460 kb
Host smart-525f333e-2269-4302-9c3d-1d94b1c37d8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118405058 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.3118405058
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.2516837631
Short name T292
Test name
Test status
Simulation time 158107691 ps
CPU time 1.27 seconds
Started Jul 04 04:58:17 PM PDT 24
Finished Jul 04 04:58:18 PM PDT 24
Peak memory 204456 kb
Host smart-889c83ce-a9bd-47cc-82a4-ac8803499752
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516837631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.2516837631
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.3424152238
Short name T728
Test name
Test status
Simulation time 1540099767 ps
CPU time 2.7 seconds
Started Jul 04 04:58:04 PM PDT 24
Finished Jul 04 04:58:07 PM PDT 24
Peak memory 204724 kb
Host smart-ea04a9b3-ae79-49cb-97f1-55d6a0f0b0f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424152238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.3424152238
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.1272837285
Short name T718
Test name
Test status
Simulation time 1971486715 ps
CPU time 6.17 seconds
Started Jul 04 04:58:01 PM PDT 24
Finished Jul 04 04:58:07 PM PDT 24
Peak memory 212896 kb
Host smart-8b2414ff-f022-4467-8979-2f144662940f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272837285 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.1272837285
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.1118791636
Short name T638
Test name
Test status
Simulation time 6736083657 ps
CPU time 5.05 seconds
Started Jul 04 04:57:58 PM PDT 24
Finished Jul 04 04:58:03 PM PDT 24
Peak memory 204708 kb
Host smart-80a15354-b918-4b29-aef8-c71bd68a574a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118791636 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1118791636
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.1595591922
Short name T819
Test name
Test status
Simulation time 1809423700 ps
CPU time 17.86 seconds
Started Jul 04 04:57:56 PM PDT 24
Finished Jul 04 04:58:14 PM PDT 24
Peak memory 204644 kb
Host smart-38c2c17b-f729-4e12-af13-8b88737c5b4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595591922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.1595591922
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.162073779
Short name T165
Test name
Test status
Simulation time 5668832641 ps
CPU time 59.55 seconds
Started Jul 04 04:58:03 PM PDT 24
Finished Jul 04 04:59:03 PM PDT 24
Peak memory 207400 kb
Host smart-2910bc3a-906a-43f7-b6b5-2d6e1d9b1221
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162073779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.162073779
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.2290015700
Short name T749
Test name
Test status
Simulation time 7863141747 ps
CPU time 10.67 seconds
Started Jul 04 04:58:00 PM PDT 24
Finished Jul 04 04:58:11 PM PDT 24
Peak memory 204844 kb
Host smart-da497cdb-cbd3-485a-8c2a-80216d9d414f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290015700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.2290015700
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.1454987430
Short name T296
Test name
Test status
Simulation time 37033980163 ps
CPU time 2008.08 seconds
Started Jul 04 04:57:56 PM PDT 24
Finished Jul 04 05:31:25 PM PDT 24
Peak memory 8406032 kb
Host smart-ec1e5e6d-df8b-4750-90cf-8f5c5f6b3c82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454987430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.1454987430
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.2465299642
Short name T79
Test name
Test status
Simulation time 1434734270 ps
CPU time 7.14 seconds
Started Jul 04 04:58:12 PM PDT 24
Finished Jul 04 04:58:20 PM PDT 24
Peak memory 212912 kb
Host smart-cf526728-cbcd-4c80-90b9-0a13f8e7e69d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465299642 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.2465299642
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.3759962139
Short name T1014
Test name
Test status
Simulation time 510108783 ps
CPU time 6.92 seconds
Started Jul 04 04:58:04 PM PDT 24
Finished Jul 04 04:58:11 PM PDT 24
Peak memory 204708 kb
Host smart-09fd84fb-a2be-4cbf-aecc-f7d99e0fff57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759962139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.3759962139
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.606369856
Short name T1444
Test name
Test status
Simulation time 48540727 ps
CPU time 0.67 seconds
Started Jul 04 04:58:30 PM PDT 24
Finished Jul 04 04:58:31 PM PDT 24
Peak memory 204360 kb
Host smart-efc1c467-5266-4ea0-a664-bedc1b9cc7f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606369856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.606369856
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.443342545
Short name T844
Test name
Test status
Simulation time 175647474 ps
CPU time 2.39 seconds
Started Jul 04 04:58:11 PM PDT 24
Finished Jul 04 04:58:14 PM PDT 24
Peak memory 212988 kb
Host smart-6e18c543-d316-41e9-a394-0e2c66394a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443342545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.443342545
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.3992377878
Short name T974
Test name
Test status
Simulation time 668756210 ps
CPU time 4.34 seconds
Started Jul 04 04:58:12 PM PDT 24
Finished Jul 04 04:58:17 PM PDT 24
Peak memory 237340 kb
Host smart-e3075c5c-5c1c-45ad-b2a6-ac5e592e13fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992377878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.3992377878
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1886382657
Short name T675
Test name
Test status
Simulation time 2011075724 ps
CPU time 114.44 seconds
Started Jul 04 04:58:14 PM PDT 24
Finished Jul 04 05:00:09 PM PDT 24
Peak memory 585672 kb
Host smart-d9852e3a-37ea-4343-952a-49a199d5cec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886382657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1886382657
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.4253524167
Short name T101
Test name
Test status
Simulation time 4868933524 ps
CPU time 174.28 seconds
Started Jul 04 04:58:14 PM PDT 24
Finished Jul 04 05:01:08 PM PDT 24
Peak memory 742460 kb
Host smart-9a1d0ad2-7610-45b1-ac7a-99f2f1983a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253524167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.4253524167
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2320694972
Short name T314
Test name
Test status
Simulation time 159977110 ps
CPU time 0.86 seconds
Started Jul 04 04:58:10 PM PDT 24
Finished Jul 04 04:58:11 PM PDT 24
Peak memory 204356 kb
Host smart-cfa85f43-f83e-4c0b-b7ef-66d4f2b76257
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320694972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2320694972
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.3067876807
Short name T621
Test name
Test status
Simulation time 389735919 ps
CPU time 9.69 seconds
Started Jul 04 04:58:11 PM PDT 24
Finished Jul 04 04:58:21 PM PDT 24
Peak memory 234804 kb
Host smart-cdf8e563-e928-4b38-9c45-185d5156d5d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067876807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.3067876807
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2818245721
Short name T530
Test name
Test status
Simulation time 21241390293 ps
CPU time 355.55 seconds
Started Jul 04 04:58:16 PM PDT 24
Finished Jul 04 05:04:12 PM PDT 24
Peak memory 1369520 kb
Host smart-cee68610-d3a8-4572-8ec5-147e28cccd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818245721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2818245721
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.3936361261
Short name T509
Test name
Test status
Simulation time 265464373 ps
CPU time 3.51 seconds
Started Jul 04 04:58:19 PM PDT 24
Finished Jul 04 04:58:23 PM PDT 24
Peak memory 204452 kb
Host smart-296917d6-b2be-41ea-8040-e3618ea056ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936361261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.3936361261
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.2217461661
Short name T71
Test name
Test status
Simulation time 4773180953 ps
CPU time 59.55 seconds
Started Jul 04 04:58:20 PM PDT 24
Finished Jul 04 04:59:20 PM PDT 24
Peak memory 327872 kb
Host smart-cfa39742-808a-410a-9542-2140c5a1b302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217461661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.2217461661
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.1365382325
Short name T147
Test name
Test status
Simulation time 149857868 ps
CPU time 0.7 seconds
Started Jul 04 04:58:05 PM PDT 24
Finished Jul 04 04:58:06 PM PDT 24
Peak memory 204360 kb
Host smart-58b8e194-2503-4976-a159-558a9aa2de2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365382325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1365382325
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.3667087324
Short name T315
Test name
Test status
Simulation time 1628697690 ps
CPU time 13.46 seconds
Started Jul 04 04:58:14 PM PDT 24
Finished Jul 04 04:58:27 PM PDT 24
Peak memory 261264 kb
Host smart-d23f1773-8ecf-4fd6-ba28-867e563d6563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667087324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.3667087324
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.1878140491
Short name T1384
Test name
Test status
Simulation time 5749172331 ps
CPU time 24.18 seconds
Started Jul 04 04:58:12 PM PDT 24
Finished Jul 04 04:58:37 PM PDT 24
Peak memory 204748 kb
Host smart-187a7318-3918-4222-b2fb-2f9e9e243e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878140491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.1878140491
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2593383130
Short name T1311
Test name
Test status
Simulation time 1526925258 ps
CPU time 23.4 seconds
Started Jul 04 04:58:16 PM PDT 24
Finished Jul 04 04:58:40 PM PDT 24
Peak memory 350480 kb
Host smart-e4343bf9-3c37-4bf7-970c-18e79b4d2914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593383130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2593383130
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.175988629
Short name T1191
Test name
Test status
Simulation time 45643802940 ps
CPU time 485.86 seconds
Started Jul 04 04:58:11 PM PDT 24
Finished Jul 04 05:06:17 PM PDT 24
Peak memory 2493020 kb
Host smart-3939e39a-a414-4fe7-a75d-79d75a884876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175988629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.175988629
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.2683662941
Short name T1189
Test name
Test status
Simulation time 9122949937 ps
CPU time 28.93 seconds
Started Jul 04 04:58:13 PM PDT 24
Finished Jul 04 04:58:42 PM PDT 24
Peak memory 213036 kb
Host smart-9947cd4b-93bf-4a77-99ed-c7265651ebd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683662941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.2683662941
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.170428323
Short name T21
Test name
Test status
Simulation time 3020935120 ps
CPU time 3.65 seconds
Started Jul 04 04:58:20 PM PDT 24
Finished Jul 04 04:58:24 PM PDT 24
Peak memory 212960 kb
Host smart-da949a86-6f57-47c9-9d33-26d81982633f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170428323 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.170428323
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1038214310
Short name T851
Test name
Test status
Simulation time 355445481 ps
CPU time 0.9 seconds
Started Jul 04 04:58:18 PM PDT 24
Finished Jul 04 04:58:19 PM PDT 24
Peak memory 204596 kb
Host smart-b6dc052b-0f70-4957-980f-f47212b32351
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038214310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1038214310
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1095625667
Short name T635
Test name
Test status
Simulation time 266702825 ps
CPU time 1.01 seconds
Started Jul 04 04:58:21 PM PDT 24
Finished Jul 04 04:58:22 PM PDT 24
Peak memory 204464 kb
Host smart-edc4d65d-9766-4be6-8f8e-6341044db94f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095625667 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1095625667
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.1225656975
Short name T877
Test name
Test status
Simulation time 838551690 ps
CPU time 1.46 seconds
Started Jul 04 04:58:18 PM PDT 24
Finished Jul 04 04:58:20 PM PDT 24
Peak memory 204448 kb
Host smart-24d8cae7-d781-4c1f-b4ef-ec9244129bd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225656975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.1225656975
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.3821007110
Short name T15
Test name
Test status
Simulation time 201314552 ps
CPU time 1.18 seconds
Started Jul 04 04:58:19 PM PDT 24
Finished Jul 04 04:58:21 PM PDT 24
Peak memory 204524 kb
Host smart-e5b269a3-36ab-4895-81a3-f58014ace417
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821007110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.3821007110
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.4002929976
Short name T762
Test name
Test status
Simulation time 1063896196 ps
CPU time 2.52 seconds
Started Jul 04 04:58:19 PM PDT 24
Finished Jul 04 04:58:22 PM PDT 24
Peak memory 204408 kb
Host smart-f03c2f82-0659-49aa-8781-24f9b66d2dbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002929976 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.4002929976
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.4055766525
Short name T326
Test name
Test status
Simulation time 1545481522 ps
CPU time 4.24 seconds
Started Jul 04 04:58:17 PM PDT 24
Finished Jul 04 04:58:21 PM PDT 24
Peak memory 207544 kb
Host smart-6a1a63f0-93d5-47e9-bbe2-2c22a5a8b51e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055766525 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.4055766525
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1768531276
Short name T895
Test name
Test status
Simulation time 15207107323 ps
CPU time 128.54 seconds
Started Jul 04 04:58:19 PM PDT 24
Finished Jul 04 05:00:28 PM PDT 24
Peak memory 1859520 kb
Host smart-d4848602-7564-4da7-88ec-d70a03102695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768531276 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1768531276
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.772732201
Short name T102
Test name
Test status
Simulation time 5682397687 ps
CPU time 15.16 seconds
Started Jul 04 04:58:11 PM PDT 24
Finished Jul 04 04:58:27 PM PDT 24
Peak memory 204796 kb
Host smart-bfdfde86-ba5d-4094-90e0-9a2f1adfb26c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772732201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_tar
get_smoke.772732201
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.2871552353
Short name T897
Test name
Test status
Simulation time 1282473513 ps
CPU time 56.94 seconds
Started Jul 04 04:58:11 PM PDT 24
Finished Jul 04 04:59:08 PM PDT 24
Peak memory 206272 kb
Host smart-de9f9f5d-ea92-48b3-86e9-effb7af2ea9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871552353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.2871552353
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.443135899
Short name T1243
Test name
Test status
Simulation time 49664332340 ps
CPU time 1170.65 seconds
Started Jul 04 04:58:11 PM PDT 24
Finished Jul 04 05:17:42 PM PDT 24
Peak memory 7673664 kb
Host smart-5c150c1a-28b6-4ee8-b409-49a2b7372099
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443135899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_wr.443135899
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.2479322778
Short name T321
Test name
Test status
Simulation time 22553354540 ps
CPU time 243.33 seconds
Started Jul 04 04:58:12 PM PDT 24
Finished Jul 04 05:02:16 PM PDT 24
Peak memory 976660 kb
Host smart-b386fddf-fdaf-49b6-91fc-915b10ce391b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479322778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.2479322778
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.3835446093
Short name T1230
Test name
Test status
Simulation time 6472489513 ps
CPU time 6.45 seconds
Started Jul 04 04:58:19 PM PDT 24
Finished Jul 04 04:58:26 PM PDT 24
Peak memory 220792 kb
Host smart-078b57a1-d331-4403-81c2-d7d8fac370a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835446093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.3835446093
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.3939507699
Short name T1016
Test name
Test status
Simulation time 30172429 ps
CPU time 0.91 seconds
Started Jul 04 04:58:17 PM PDT 24
Finished Jul 04 04:58:18 PM PDT 24
Peak memory 204688 kb
Host smart-c5926099-0e99-4ae0-bca6-6a80a91d635f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939507699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.3939507699
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1758411337
Short name T930
Test name
Test status
Simulation time 14402093 ps
CPU time 0.62 seconds
Started Jul 04 04:58:41 PM PDT 24
Finished Jul 04 04:58:42 PM PDT 24
Peak memory 204368 kb
Host smart-5f6387c7-a565-4b50-a753-3d13378182ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758411337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1758411337
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.116292881
Short name T1089
Test name
Test status
Simulation time 649267376 ps
CPU time 3.14 seconds
Started Jul 04 04:58:27 PM PDT 24
Finished Jul 04 04:58:30 PM PDT 24
Peak memory 212924 kb
Host smart-0504dfa0-02e3-4005-a433-38afb4039075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116292881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.116292881
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.4002323706
Short name T350
Test name
Test status
Simulation time 539803956 ps
CPU time 5.81 seconds
Started Jul 04 04:58:26 PM PDT 24
Finished Jul 04 04:58:32 PM PDT 24
Peak memory 257240 kb
Host smart-0197bbf1-50bb-43d3-a5f4-74b5a4fdd459
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002323706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.4002323706
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.3625944204
Short name T1469
Test name
Test status
Simulation time 2489535783 ps
CPU time 70.79 seconds
Started Jul 04 04:58:23 PM PDT 24
Finished Jul 04 04:59:34 PM PDT 24
Peak memory 678084 kb
Host smart-80fa570d-1ec6-4d6e-af6f-efe0fe40f58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625944204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.3625944204
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2280567562
Short name T627
Test name
Test status
Simulation time 8744395774 ps
CPU time 153.05 seconds
Started Jul 04 04:58:25 PM PDT 24
Finished Jul 04 05:00:58 PM PDT 24
Peak memory 675440 kb
Host smart-2fa4779f-4291-486f-b869-10eb1e7d9f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280567562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2280567562
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2246426807
Short name T446
Test name
Test status
Simulation time 539164282 ps
CPU time 1.02 seconds
Started Jul 04 04:58:27 PM PDT 24
Finished Jul 04 04:58:28 PM PDT 24
Peak memory 204348 kb
Host smart-26caa450-19f8-4d05-93f9-169dc8be93c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246426807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2246426807
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2679341447
Short name T805
Test name
Test status
Simulation time 446366933 ps
CPU time 4.78 seconds
Started Jul 04 04:58:25 PM PDT 24
Finished Jul 04 04:58:30 PM PDT 24
Peak memory 204680 kb
Host smart-de3dd348-22c7-4dd4-abce-0e4fa07df935
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679341447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2679341447
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1050301568
Short name T120
Test name
Test status
Simulation time 12016378125 ps
CPU time 74.36 seconds
Started Jul 04 04:58:30 PM PDT 24
Finished Jul 04 04:59:44 PM PDT 24
Peak memory 920284 kb
Host smart-6f2cae51-cfd1-4466-8419-03a63366c15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050301568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1050301568
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.504493220
Short name T241
Test name
Test status
Simulation time 715767370 ps
CPU time 2.39 seconds
Started Jul 04 04:58:38 PM PDT 24
Finished Jul 04 04:58:40 PM PDT 24
Peak memory 204756 kb
Host smart-3f2df3f2-2cc2-4f5c-a52e-c4f9af617e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504493220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.504493220
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.584633383
Short name T622
Test name
Test status
Simulation time 1262947622 ps
CPU time 23.39 seconds
Started Jul 04 04:58:31 PM PDT 24
Finished Jul 04 04:58:55 PM PDT 24
Peak memory 277996 kb
Host smart-f58b6392-68b2-4ba7-a583-af4774d37ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584633383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.584633383
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.1005184077
Short name T1352
Test name
Test status
Simulation time 100486073 ps
CPU time 0.66 seconds
Started Jul 04 04:58:29 PM PDT 24
Finished Jul 04 04:58:30 PM PDT 24
Peak memory 204400 kb
Host smart-d6c1f4d1-e89a-4955-a6fb-4835bff09680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005184077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.1005184077
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1921978635
Short name T232
Test name
Test status
Simulation time 3379905941 ps
CPU time 65.99 seconds
Started Jul 04 04:58:23 PM PDT 24
Finished Jul 04 04:59:30 PM PDT 24
Peak memory 253248 kb
Host smart-3d4763f4-d577-44cc-920d-eeea59810e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921978635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1921978635
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.606198492
Short name T1262
Test name
Test status
Simulation time 50590547 ps
CPU time 1.69 seconds
Started Jul 04 04:58:26 PM PDT 24
Finished Jul 04 04:58:28 PM PDT 24
Peak memory 205144 kb
Host smart-45314ce2-d087-4555-91ed-3286c017a7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606198492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.606198492
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.1628826459
Short name T1144
Test name
Test status
Simulation time 7227670786 ps
CPU time 83.15 seconds
Started Jul 04 04:58:25 PM PDT 24
Finished Jul 04 04:59:48 PM PDT 24
Peak memory 294272 kb
Host smart-d8500e77-9d9b-4b6d-be0a-c8efaf7054c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628826459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1628826459
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.1295465169
Short name T58
Test name
Test status
Simulation time 88037011560 ps
CPU time 1413.83 seconds
Started Jul 04 04:58:26 PM PDT 24
Finished Jul 04 05:22:01 PM PDT 24
Peak memory 1807708 kb
Host smart-47797635-6591-4c61-a5c2-827ad8c73f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295465169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.1295465169
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.1015423169
Short name T1139
Test name
Test status
Simulation time 923073311 ps
CPU time 12.74 seconds
Started Jul 04 04:58:27 PM PDT 24
Finished Jul 04 04:58:40 PM PDT 24
Peak memory 221092 kb
Host smart-7aed13ca-171b-4404-8a53-e3bdfe12f452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015423169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1015423169
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.4178716401
Short name T916
Test name
Test status
Simulation time 2208336445 ps
CPU time 3.14 seconds
Started Jul 04 04:58:31 PM PDT 24
Finished Jul 04 04:58:34 PM PDT 24
Peak memory 204816 kb
Host smart-877db085-6e52-41c8-9159-38954cb5f179
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178716401 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.4178716401
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2166162007
Short name T3
Test name
Test status
Simulation time 200745331 ps
CPU time 1.16 seconds
Started Jul 04 04:58:30 PM PDT 24
Finished Jul 04 04:58:32 PM PDT 24
Peak memory 204592 kb
Host smart-84eea640-d0ff-4ddc-aa0b-4f037b84be34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166162007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2166162007
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.1424697966
Short name T687
Test name
Test status
Simulation time 845015691 ps
CPU time 1.37 seconds
Started Jul 04 04:58:31 PM PDT 24
Finished Jul 04 04:58:33 PM PDT 24
Peak memory 204704 kb
Host smart-fcfeb1f7-c165-4db3-93ef-92e3d1cb2527
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424697966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.1424697966
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.3099408321
Short name T732
Test name
Test status
Simulation time 577929885 ps
CPU time 2.82 seconds
Started Jul 04 04:58:39 PM PDT 24
Finished Jul 04 04:58:42 PM PDT 24
Peak memory 204740 kb
Host smart-fed4a7a7-ae12-4b74-9c2f-71b55ba5be0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099408321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.3099408321
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.3848480661
Short name T534
Test name
Test status
Simulation time 479303512 ps
CPU time 0.88 seconds
Started Jul 04 04:58:39 PM PDT 24
Finished Jul 04 04:58:40 PM PDT 24
Peak memory 204512 kb
Host smart-9a975cb9-0847-4554-ad0f-dbf93bb6bca7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848480661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.3848480661
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.277769571
Short name T1389
Test name
Test status
Simulation time 1121471315 ps
CPU time 3.3 seconds
Started Jul 04 04:58:32 PM PDT 24
Finished Jul 04 04:58:35 PM PDT 24
Peak memory 204688 kb
Host smart-482edcd8-9e89-4ac1-88a9-0db185afad83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277769571 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.277769571
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.4128730858
Short name T894
Test name
Test status
Simulation time 11865677612 ps
CPU time 10.86 seconds
Started Jul 04 04:58:34 PM PDT 24
Finished Jul 04 04:58:45 PM PDT 24
Peak memory 307880 kb
Host smart-b84569b1-f37c-4a28-afa0-1519b640e367
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128730858 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.4128730858
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.3807264234
Short name T815
Test name
Test status
Simulation time 1408614161 ps
CPU time 13.33 seconds
Started Jul 04 04:58:29 PM PDT 24
Finished Jul 04 04:58:43 PM PDT 24
Peak memory 204628 kb
Host smart-96129d2f-83d0-4557-be20-2657315418f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807264234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.3807264234
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.1675898182
Short name T674
Test name
Test status
Simulation time 1787874767 ps
CPU time 18.22 seconds
Started Jul 04 04:58:25 PM PDT 24
Finished Jul 04 04:58:44 PM PDT 24
Peak memory 212596 kb
Host smart-90576f39-a5f9-4268-9691-54b536c72ba6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675898182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.1675898182
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.2424039758
Short name T726
Test name
Test status
Simulation time 28504886801 ps
CPU time 28.99 seconds
Started Jul 04 04:58:23 PM PDT 24
Finished Jul 04 04:58:52 PM PDT 24
Peak memory 595224 kb
Host smart-1047abd6-cbd6-4966-8a72-25a0a5550545
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424039758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.2424039758
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3969062722
Short name T1528
Test name
Test status
Simulation time 19428071429 ps
CPU time 236.54 seconds
Started Jul 04 04:58:30 PM PDT 24
Finished Jul 04 05:02:27 PM PDT 24
Peak memory 994956 kb
Host smart-2429250c-009c-4c7d-a8ad-1c0c93009090
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969062722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3969062722
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.768202209
Short name T453
Test name
Test status
Simulation time 18490753547 ps
CPU time 6.37 seconds
Started Jul 04 04:58:30 PM PDT 24
Finished Jul 04 04:58:36 PM PDT 24
Peak memory 213856 kb
Host smart-82a876a7-ff0a-438d-a4ad-5db727a609d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768202209 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_timeout.768202209
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.4213747600
Short name T1426
Test name
Test status
Simulation time 571676615 ps
CPU time 7.67 seconds
Started Jul 04 04:58:43 PM PDT 24
Finished Jul 04 04:58:51 PM PDT 24
Peak memory 212908 kb
Host smart-97af59d1-719a-4a2a-a19b-5eb2ba8bcb92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213747600 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.4213747600
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.18429646
Short name T683
Test name
Test status
Simulation time 36145958 ps
CPU time 0.63 seconds
Started Jul 04 04:58:53 PM PDT 24
Finished Jul 04 04:58:53 PM PDT 24
Peak memory 204324 kb
Host smart-26c61e14-efa0-40f0-868d-9da25f05d52b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18429646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.18429646
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.3954868142
Short name T1510
Test name
Test status
Simulation time 297338008 ps
CPU time 5.87 seconds
Started Jul 04 04:58:41 PM PDT 24
Finished Jul 04 04:58:47 PM PDT 24
Peak memory 254400 kb
Host smart-d1c7fc2a-89d3-405c-b411-863d60a355dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954868142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.3954868142
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.2921504279
Short name T1257
Test name
Test status
Simulation time 1686773541 ps
CPU time 5.46 seconds
Started Jul 04 04:58:38 PM PDT 24
Finished Jul 04 04:58:43 PM PDT 24
Peak memory 250952 kb
Host smart-4e45064e-db32-47e6-980b-9299f73e3e6d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921504279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.2921504279
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.574607210
Short name T1168
Test name
Test status
Simulation time 13036738838 ps
CPU time 194.11 seconds
Started Jul 04 04:58:36 PM PDT 24
Finished Jul 04 05:01:51 PM PDT 24
Peak memory 797748 kb
Host smart-9b725d76-a66a-4447-982d-566c7f3544aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574607210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.574607210
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.3418334846
Short name T845
Test name
Test status
Simulation time 4768254732 ps
CPU time 85.54 seconds
Started Jul 04 04:58:41 PM PDT 24
Finished Jul 04 05:00:07 PM PDT 24
Peak memory 778596 kb
Host smart-da84b97b-fb47-4044-b251-c8f12c3a0b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418334846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.3418334846
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.94960262
Short name T1094
Test name
Test status
Simulation time 96064645 ps
CPU time 1.05 seconds
Started Jul 04 04:58:37 PM PDT 24
Finished Jul 04 04:58:38 PM PDT 24
Peak memory 204304 kb
Host smart-410b5726-8f7c-440b-9fe7-d26d84b49bcf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94960262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fmt
.94960262
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.106999003
Short name T319
Test name
Test status
Simulation time 733706481 ps
CPU time 5.06 seconds
Started Jul 04 04:58:38 PM PDT 24
Finished Jul 04 04:58:43 PM PDT 24
Peak memory 204740 kb
Host smart-b5e92065-74d0-41c1-852e-95438af92bea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106999003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.
106999003
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1429409041
Short name T75
Test name
Test status
Simulation time 3866959819 ps
CPU time 247.12 seconds
Started Jul 04 04:58:41 PM PDT 24
Finished Jul 04 05:02:48 PM PDT 24
Peak memory 1044784 kb
Host smart-e363c86f-81d9-48bd-917a-5259b85f6ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429409041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1429409041
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.86768394
Short name T689
Test name
Test status
Simulation time 348498298 ps
CPU time 3.13 seconds
Started Jul 04 04:58:43 PM PDT 24
Finished Jul 04 04:58:46 PM PDT 24
Peak memory 204732 kb
Host smart-2dad2676-6e34-40ab-8b59-c7c3aff13f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86768394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.86768394
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_override.1407867648
Short name T309
Test name
Test status
Simulation time 29434395 ps
CPU time 0.7 seconds
Started Jul 04 04:58:37 PM PDT 24
Finished Jul 04 04:58:38 PM PDT 24
Peak memory 204412 kb
Host smart-7c3c71a0-e51b-4090-9e87-f5160b24a9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407867648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.1407867648
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.3463402551
Short name T523
Test name
Test status
Simulation time 51055516412 ps
CPU time 305.04 seconds
Started Jul 04 04:58:37 PM PDT 24
Finished Jul 04 05:03:43 PM PDT 24
Peak memory 1768076 kb
Host smart-b147ee1e-5b30-4f43-ae70-d11d026f3c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463402551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.3463402551
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.2018590395
Short name T864
Test name
Test status
Simulation time 23649384723 ps
CPU time 57.77 seconds
Started Jul 04 04:58:37 PM PDT 24
Finished Jul 04 04:59:35 PM PDT 24
Peak memory 204748 kb
Host smart-c6e001aa-0ee3-404a-a02e-0db582212720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018590395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.2018590395
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.2325819619
Short name T342
Test name
Test status
Simulation time 1615884716 ps
CPU time 79.12 seconds
Started Jul 04 04:58:39 PM PDT 24
Finished Jul 04 04:59:59 PM PDT 24
Peak memory 397920 kb
Host smart-a909b051-9f08-43ff-bdf5-894729c12aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325819619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.2325819619
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.1170045017
Short name T278
Test name
Test status
Simulation time 8042419029 ps
CPU time 318.49 seconds
Started Jul 04 04:58:39 PM PDT 24
Finished Jul 04 05:03:58 PM PDT 24
Peak memory 1741508 kb
Host smart-f62934a5-c605-417c-87b9-86e401ff669c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170045017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.1170045017
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.2539248974
Short name T385
Test name
Test status
Simulation time 1575957961 ps
CPU time 35.77 seconds
Started Jul 04 04:58:41 PM PDT 24
Finished Jul 04 04:59:17 PM PDT 24
Peak memory 212892 kb
Host smart-8751dfda-6fb1-4834-866e-27716233c4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539248974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.2539248974
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.3846019359
Short name T499
Test name
Test status
Simulation time 3568922932 ps
CPU time 4.73 seconds
Started Jul 04 04:58:44 PM PDT 24
Finished Jul 04 04:58:49 PM PDT 24
Peak memory 212920 kb
Host smart-5e484ec6-8748-410c-a242-f8ed9088bd03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846019359 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.3846019359
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.589131911
Short name T676
Test name
Test status
Simulation time 369112871 ps
CPU time 0.97 seconds
Started Jul 04 04:58:45 PM PDT 24
Finished Jul 04 04:58:47 PM PDT 24
Peak memory 204676 kb
Host smart-a5c87569-ea5a-4157-9b80-50ba61f20bb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589131911 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_acq.589131911
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.3825679341
Short name T1141
Test name
Test status
Simulation time 120873528 ps
CPU time 0.84 seconds
Started Jul 04 04:58:42 PM PDT 24
Finished Jul 04 04:58:43 PM PDT 24
Peak memory 204436 kb
Host smart-a8b14789-0ad2-4b91-8d22-75049864cf54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825679341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.3825679341
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.769421134
Short name T801
Test name
Test status
Simulation time 504198813 ps
CPU time 2.88 seconds
Started Jul 04 04:58:44 PM PDT 24
Finished Jul 04 04:58:47 PM PDT 24
Peak memory 204672 kb
Host smart-18fd5fa5-fddf-4dc6-b28d-459237a7f696
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769421134 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.769421134
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.319548147
Short name T1132
Test name
Test status
Simulation time 529580288 ps
CPU time 1.22 seconds
Started Jul 04 04:58:52 PM PDT 24
Finished Jul 04 04:58:53 PM PDT 24
Peak memory 204508 kb
Host smart-96dab2c9-71d7-4788-bd34-67da8e59b7c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319548147 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.319548147
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.140298956
Short name T1053
Test name
Test status
Simulation time 308165844 ps
CPU time 2.72 seconds
Started Jul 04 04:58:45 PM PDT 24
Finished Jul 04 04:58:48 PM PDT 24
Peak memory 204680 kb
Host smart-a7a1d471-4d5e-4785-81f3-447d10472c5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140298956 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_hrst.140298956
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.4146766091
Short name T688
Test name
Test status
Simulation time 2071364690 ps
CPU time 3.47 seconds
Started Jul 04 04:58:44 PM PDT 24
Finished Jul 04 04:58:47 PM PDT 24
Peak memory 204796 kb
Host smart-5de042d9-c34a-46bf-837e-21faf101356f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146766091 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.4146766091
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.3105478949
Short name T1153
Test name
Test status
Simulation time 11565028903 ps
CPU time 11.32 seconds
Started Jul 04 04:58:45 PM PDT 24
Finished Jul 04 04:58:56 PM PDT 24
Peak memory 319808 kb
Host smart-5c6f8f4c-02b0-4cec-bf98-dd1feefb9fbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105478949 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.3105478949
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.3591013439
Short name T512
Test name
Test status
Simulation time 19863003235 ps
CPU time 18.09 seconds
Started Jul 04 04:58:45 PM PDT 24
Finished Jul 04 04:59:03 PM PDT 24
Peak memory 204860 kb
Host smart-bf5a4fc8-a8a4-4f3b-b71f-976fabc379cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591013439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.3591013439
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.3958069763
Short name T242
Test name
Test status
Simulation time 2232593947 ps
CPU time 45.86 seconds
Started Jul 04 04:58:45 PM PDT 24
Finished Jul 04 04:59:31 PM PDT 24
Peak memory 204744 kb
Host smart-b8e4d7dc-436c-4826-99a1-7e7531c093da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958069763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.3958069763
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.2001163149
Short name T971
Test name
Test status
Simulation time 15484145543 ps
CPU time 10.58 seconds
Started Jul 04 04:58:36 PM PDT 24
Finished Jul 04 04:58:47 PM PDT 24
Peak memory 204784 kb
Host smart-05b61c1c-0417-42b5-8de0-a4f3e6753fb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001163149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.2001163149
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.2003654584
Short name T1354
Test name
Test status
Simulation time 15216826863 ps
CPU time 440.33 seconds
Started Jul 04 04:58:46 PM PDT 24
Finished Jul 04 05:06:06 PM PDT 24
Peak memory 2842464 kb
Host smart-34fd4cf1-c982-4d41-a462-97779473750c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003654584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.2003654584
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.2672448213
Short name T1333
Test name
Test status
Simulation time 1483098539 ps
CPU time 7.65 seconds
Started Jul 04 04:58:45 PM PDT 24
Finished Jul 04 04:58:53 PM PDT 24
Peak memory 218264 kb
Host smart-1d1a4e6e-d143-414f-a093-378f095ad187
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672448213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.2672448213
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.2056283626
Short name T1059
Test name
Test status
Simulation time 133063144 ps
CPU time 2.05 seconds
Started Jul 04 04:58:52 PM PDT 24
Finished Jul 04 04:58:54 PM PDT 24
Peak memory 204708 kb
Host smart-be901966-eade-4493-9b2f-b5dc582454ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056283626 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.2056283626
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.3948515259
Short name T1024
Test name
Test status
Simulation time 21155310 ps
CPU time 0.64 seconds
Started Jul 04 04:59:08 PM PDT 24
Finished Jul 04 04:59:09 PM PDT 24
Peak memory 204428 kb
Host smart-9c043912-8a2a-460f-8f56-6210ef73a7bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948515259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.3948515259
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.2063768327
Short name T53
Test name
Test status
Simulation time 974911773 ps
CPU time 11.31 seconds
Started Jul 04 04:59:02 PM PDT 24
Finished Jul 04 04:59:13 PM PDT 24
Peak memory 248980 kb
Host smart-168e8f24-d0eb-433e-a904-cc7436d5f090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063768327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2063768327
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3976948139
Short name T533
Test name
Test status
Simulation time 1276322755 ps
CPU time 6.8 seconds
Started Jul 04 04:58:51 PM PDT 24
Finished Jul 04 04:58:58 PM PDT 24
Peak memory 269676 kb
Host smart-68fc5522-469d-42a1-b556-e6a4a43fbe4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976948139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3976948139
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3183069194
Short name T211
Test name
Test status
Simulation time 10266618347 ps
CPU time 92.67 seconds
Started Jul 04 04:58:53 PM PDT 24
Finished Jul 04 05:00:26 PM PDT 24
Peak memory 798460 kb
Host smart-f4049d57-95d9-4231-91dc-d64aeb2a14b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183069194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3183069194
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3288456482
Short name T727
Test name
Test status
Simulation time 2097197391 ps
CPU time 78.07 seconds
Started Jul 04 04:58:51 PM PDT 24
Finished Jul 04 05:00:09 PM PDT 24
Peak memory 728376 kb
Host smart-a4f019da-513c-474b-9ae4-7e57abd7de24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288456482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3288456482
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.1485520046
Short name T604
Test name
Test status
Simulation time 517168707 ps
CPU time 0.9 seconds
Started Jul 04 04:58:52 PM PDT 24
Finished Jul 04 04:58:54 PM PDT 24
Peak memory 204400 kb
Host smart-0cd86ef2-5d99-4a34-a773-c61286c373fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485520046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.1485520046
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3819480261
Short name T619
Test name
Test status
Simulation time 317532846 ps
CPU time 4.33 seconds
Started Jul 04 04:58:52 PM PDT 24
Finished Jul 04 04:58:56 PM PDT 24
Peak memory 234048 kb
Host smart-4af13f00-0c49-4b4d-9338-514e03a44902
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819480261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3819480261
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.1577632436
Short name T1208
Test name
Test status
Simulation time 8519910257 ps
CPU time 121.22 seconds
Started Jul 04 04:58:52 PM PDT 24
Finished Jul 04 05:00:53 PM PDT 24
Peak memory 1233204 kb
Host smart-6a830229-fdd8-4103-ada2-26b864f06e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577632436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.1577632436
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.3110296348
Short name T1241
Test name
Test status
Simulation time 364006599 ps
CPU time 14.47 seconds
Started Jul 04 04:59:02 PM PDT 24
Finished Jul 04 04:59:17 PM PDT 24
Peak memory 204700 kb
Host smart-dc15b685-6eb5-433b-8597-2ac0e631c0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110296348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.3110296348
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.3421904205
Short name T653
Test name
Test status
Simulation time 1472848436 ps
CPU time 29.46 seconds
Started Jul 04 04:58:57 PM PDT 24
Finished Jul 04 04:59:27 PM PDT 24
Peak memory 360676 kb
Host smart-9a9c5e71-8438-4d0c-b7fb-47ff2ff48f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421904205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.3421904205
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.3772101946
Short name T1381
Test name
Test status
Simulation time 29149691 ps
CPU time 0.64 seconds
Started Jul 04 04:58:51 PM PDT 24
Finished Jul 04 04:58:52 PM PDT 24
Peak memory 204420 kb
Host smart-2f186464-184d-4b90-affc-30fa81628b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772101946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3772101946
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1995327727
Short name T757
Test name
Test status
Simulation time 358096318 ps
CPU time 14.35 seconds
Started Jul 04 04:58:51 PM PDT 24
Finished Jul 04 04:59:06 PM PDT 24
Peak memory 229184 kb
Host smart-0c38e1b6-ec00-417e-a8c2-767e19c99eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995327727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1995327727
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.4109289739
Short name T708
Test name
Test status
Simulation time 227277579 ps
CPU time 2.95 seconds
Started Jul 04 04:59:03 PM PDT 24
Finished Jul 04 04:59:06 PM PDT 24
Peak memory 204568 kb
Host smart-0c50306f-5a28-42d9-93f4-888474811c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109289739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.4109289739
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.3112108836
Short name T1482
Test name
Test status
Simulation time 12013475587 ps
CPU time 102.37 seconds
Started Jul 04 04:58:52 PM PDT 24
Finished Jul 04 05:00:35 PM PDT 24
Peak memory 409420 kb
Host smart-1ff028c0-0542-47e6-8ad9-8ff01fd79d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112108836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3112108836
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.403087925
Short name T55
Test name
Test status
Simulation time 13122968010 ps
CPU time 537.46 seconds
Started Jul 04 04:58:57 PM PDT 24
Finished Jul 04 05:07:54 PM PDT 24
Peak memory 1178340 kb
Host smart-e60947b9-af2b-4bac-93fd-f308c63c35df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403087925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.403087925
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3546992839
Short name T909
Test name
Test status
Simulation time 1174289014 ps
CPU time 13.02 seconds
Started Jul 04 04:58:58 PM PDT 24
Finished Jul 04 04:59:11 PM PDT 24
Peak memory 212908 kb
Host smart-43962802-0226-4ebd-88fc-4ed72c85fdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546992839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3546992839
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1107885403
Short name T574
Test name
Test status
Simulation time 2499845580 ps
CPU time 3.32 seconds
Started Jul 04 04:59:03 PM PDT 24
Finished Jul 04 04:59:06 PM PDT 24
Peak memory 212984 kb
Host smart-90783962-5263-4b00-8563-bef922f28691
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107885403 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1107885403
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2399632391
Short name T790
Test name
Test status
Simulation time 723370080 ps
CPU time 1.42 seconds
Started Jul 04 04:58:58 PM PDT 24
Finished Jul 04 04:58:59 PM PDT 24
Peak memory 204848 kb
Host smart-cdb6626d-b0da-440a-9024-1fa10a72c8e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399632391 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2399632391
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.4081482321
Short name T823
Test name
Test status
Simulation time 191051924 ps
CPU time 0.96 seconds
Started Jul 04 04:59:01 PM PDT 24
Finished Jul 04 04:59:02 PM PDT 24
Peak memory 204508 kb
Host smart-d3248a7c-a3b3-498e-adc9-6a655d82a81c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081482321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.4081482321
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.2403841071
Short name T497
Test name
Test status
Simulation time 814246531 ps
CPU time 2.21 seconds
Started Jul 04 04:59:05 PM PDT 24
Finished Jul 04 04:59:07 PM PDT 24
Peak memory 204716 kb
Host smart-e19087db-6fe9-409c-a7ca-2ca75ecc7f41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403841071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.2403841071
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.1940307504
Short name T441
Test name
Test status
Simulation time 169746422 ps
CPU time 1.43 seconds
Started Jul 04 04:59:04 PM PDT 24
Finished Jul 04 04:59:06 PM PDT 24
Peak memory 204524 kb
Host smart-d476a78c-be3f-4270-b353-1f86fdadb161
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940307504 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.1940307504
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.3108116721
Short name T915
Test name
Test status
Simulation time 1361568677 ps
CPU time 5.46 seconds
Started Jul 04 04:59:00 PM PDT 24
Finished Jul 04 04:59:05 PM PDT 24
Peak memory 215112 kb
Host smart-4431e90e-5638-409f-97c5-d7b021f629fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108116721 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.3108116721
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2469833942
Short name T10
Test name
Test status
Simulation time 8034364336 ps
CPU time 18.91 seconds
Started Jul 04 04:58:57 PM PDT 24
Finished Jul 04 04:59:17 PM PDT 24
Peak memory 325776 kb
Host smart-e4bb67c6-06d4-4ebc-a82e-0aff11aaf4ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469833942 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2469833942
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.2891173604
Short name T1046
Test name
Test status
Simulation time 1162371332 ps
CPU time 13.84 seconds
Started Jul 04 04:59:00 PM PDT 24
Finished Jul 04 04:59:14 PM PDT 24
Peak memory 204660 kb
Host smart-b812d912-2c36-4e2c-8395-42deeccc3168
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891173604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.2891173604
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.3838323275
Short name T1419
Test name
Test status
Simulation time 1305722964 ps
CPU time 58.23 seconds
Started Jul 04 04:59:08 PM PDT 24
Finished Jul 04 05:00:07 PM PDT 24
Peak memory 205068 kb
Host smart-5942b1f7-d601-4623-853e-ccb56e3227e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838323275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.3838323275
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.1182440198
Short name T800
Test name
Test status
Simulation time 40057584550 ps
CPU time 455.02 seconds
Started Jul 04 04:59:00 PM PDT 24
Finished Jul 04 05:06:35 PM PDT 24
Peak memory 4509864 kb
Host smart-22d75ee7-b411-49ff-8d5b-3a56183516b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182440198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.1182440198
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.875088906
Short name T1146
Test name
Test status
Simulation time 15824160038 ps
CPU time 103.33 seconds
Started Jul 04 04:58:59 PM PDT 24
Finished Jul 04 05:00:43 PM PDT 24
Peak memory 985800 kb
Host smart-84879b51-7d06-4a01-9e9f-33ef58d5adef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875088906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_t
arget_stretch.875088906
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3936019635
Short name T636
Test name
Test status
Simulation time 4523855599 ps
CPU time 6.82 seconds
Started Jul 04 04:58:59 PM PDT 24
Finished Jul 04 04:59:06 PM PDT 24
Peak memory 218276 kb
Host smart-d4a2d30a-9f31-414b-bd95-732375667834
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936019635 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3936019635
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.2386901464
Short name T391
Test name
Test status
Simulation time 122842688 ps
CPU time 2.07 seconds
Started Jul 04 04:59:03 PM PDT 24
Finished Jul 04 04:59:05 PM PDT 24
Peak memory 204704 kb
Host smart-00681888-da32-4f6d-8307-047781a7be3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386901464 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.2386901464
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.4214484646
Short name T183
Test name
Test status
Simulation time 18307738 ps
CPU time 0.65 seconds
Started Jul 04 04:59:18 PM PDT 24
Finished Jul 04 04:59:19 PM PDT 24
Peak memory 204356 kb
Host smart-b1147fda-518f-456b-a120-c4f671a5bbe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214484646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.4214484646
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3216889354
Short name T1236
Test name
Test status
Simulation time 275417042 ps
CPU time 2.02 seconds
Started Jul 04 04:59:04 PM PDT 24
Finished Jul 04 04:59:07 PM PDT 24
Peak memory 218852 kb
Host smart-67d316cb-5b49-41eb-9524-9740875e609c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216889354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3216889354
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.4293721001
Short name T1045
Test name
Test status
Simulation time 1425138390 ps
CPU time 16.56 seconds
Started Jul 04 04:59:04 PM PDT 24
Finished Jul 04 04:59:20 PM PDT 24
Peak memory 253848 kb
Host smart-3c974465-0a17-413a-b2fe-770fadf51d2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293721001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.4293721001
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.328675616
Short name T82
Test name
Test status
Simulation time 1650098396 ps
CPU time 112.06 seconds
Started Jul 04 04:59:06 PM PDT 24
Finished Jul 04 05:00:58 PM PDT 24
Peak memory 611760 kb
Host smart-f731a3c0-e0ac-49fd-9c66-57bd799ab6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328675616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.328675616
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3723030972
Short name T803
Test name
Test status
Simulation time 2167772229 ps
CPU time 160.06 seconds
Started Jul 04 04:59:05 PM PDT 24
Finished Jul 04 05:01:46 PM PDT 24
Peak memory 722856 kb
Host smart-fd21311d-24e1-41a8-82cf-5790a5e54c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723030972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3723030972
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3488920014
Short name T1114
Test name
Test status
Simulation time 126859821 ps
CPU time 1.1 seconds
Started Jul 04 04:59:05 PM PDT 24
Finished Jul 04 04:59:07 PM PDT 24
Peak memory 204548 kb
Host smart-c529e672-988b-45ba-a202-8400a97249c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488920014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3488920014
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.251021449
Short name T162
Test name
Test status
Simulation time 121700562 ps
CPU time 3.22 seconds
Started Jul 04 04:59:05 PM PDT 24
Finished Jul 04 04:59:09 PM PDT 24
Peak memory 204732 kb
Host smart-25e10fd8-3845-421f-a6fc-58ac0cba3b6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251021449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.
251021449
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.3050759620
Short name T1338
Test name
Test status
Simulation time 4293179521 ps
CPU time 321.33 seconds
Started Jul 04 04:59:04 PM PDT 24
Finished Jul 04 05:04:25 PM PDT 24
Peak memory 1273980 kb
Host smart-aba4806f-6741-4831-bded-69d4153e3f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050759620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3050759620
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.3767661821
Short name T848
Test name
Test status
Simulation time 479876188 ps
CPU time 7.21 seconds
Started Jul 04 04:59:10 PM PDT 24
Finished Jul 04 04:59:17 PM PDT 24
Peak memory 204736 kb
Host smart-c2db6c8e-3356-419e-98f1-280249358a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767661821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3767661821
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.440716324
Short name T1052
Test name
Test status
Simulation time 5716546823 ps
CPU time 26.36 seconds
Started Jul 04 04:59:10 PM PDT 24
Finished Jul 04 04:59:37 PM PDT 24
Peak memory 300240 kb
Host smart-78864b9a-d900-4e40-9eda-443be64e9a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440716324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.440716324
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.916664843
Short name T927
Test name
Test status
Simulation time 19763874 ps
CPU time 0.66 seconds
Started Jul 04 04:59:02 PM PDT 24
Finished Jul 04 04:59:03 PM PDT 24
Peak memory 204804 kb
Host smart-ed551372-fb25-49e5-8396-c692fa0a0a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916664843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.916664843
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.4244620679
Short name T96
Test name
Test status
Simulation time 3047313586 ps
CPU time 115.97 seconds
Started Jul 04 04:59:06 PM PDT 24
Finished Jul 04 05:01:02 PM PDT 24
Peak memory 237532 kb
Host smart-3d269ec4-ce2b-4832-8ce2-5e2598211f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244620679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.4244620679
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.2082219864
Short name T467
Test name
Test status
Simulation time 319244787 ps
CPU time 2.12 seconds
Started Jul 04 04:59:04 PM PDT 24
Finished Jul 04 04:59:07 PM PDT 24
Peak memory 204596 kb
Host smart-fa29bf14-193e-4432-ae16-8e35e16ecbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082219864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.2082219864
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.3609669796
Short name T1026
Test name
Test status
Simulation time 10220964309 ps
CPU time 46.8 seconds
Started Jul 04 04:59:06 PM PDT 24
Finished Jul 04 04:59:53 PM PDT 24
Peak memory 429172 kb
Host smart-4536b1a9-59a3-45c7-b9c2-02745ded2868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609669796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.3609669796
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.286459430
Short name T652
Test name
Test status
Simulation time 1055775447 ps
CPU time 10.87 seconds
Started Jul 04 04:59:08 PM PDT 24
Finished Jul 04 04:59:19 PM PDT 24
Peak memory 214460 kb
Host smart-3d10d7a1-ec04-401f-9c6d-858ddf624bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286459430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.286459430
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.2790485136
Short name T491
Test name
Test status
Simulation time 3769971973 ps
CPU time 4.67 seconds
Started Jul 04 04:59:11 PM PDT 24
Finished Jul 04 04:59:16 PM PDT 24
Peak memory 212952 kb
Host smart-e05b8e11-0de7-4cd7-89c7-e9a80dcf0cce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790485136 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.2790485136
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.687586851
Short name T873
Test name
Test status
Simulation time 762757982 ps
CPU time 1.51 seconds
Started Jul 04 04:59:10 PM PDT 24
Finished Jul 04 04:59:12 PM PDT 24
Peak memory 205960 kb
Host smart-bcfdc5c1-de06-4fa4-9441-94eb2b6ec5d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687586851 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_acq.687586851
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2852006595
Short name T1417
Test name
Test status
Simulation time 238308202 ps
CPU time 1.58 seconds
Started Jul 04 04:59:10 PM PDT 24
Finished Jul 04 04:59:12 PM PDT 24
Peak memory 207072 kb
Host smart-252d4098-2dd4-48ec-b758-479d6d541fdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852006595 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2852006595
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.1085978017
Short name T124
Test name
Test status
Simulation time 114442481 ps
CPU time 1.11 seconds
Started Jul 04 04:59:10 PM PDT 24
Finished Jul 04 04:59:11 PM PDT 24
Peak memory 204412 kb
Host smart-1cc81cee-8aa3-48a9-a3c8-257a5e4d4226
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085978017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.1085978017
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.904173594
Short name T507
Test name
Test status
Simulation time 283283117 ps
CPU time 1.25 seconds
Started Jul 04 04:59:19 PM PDT 24
Finished Jul 04 04:59:20 PM PDT 24
Peak memory 204512 kb
Host smart-f6fdfa85-81d9-4645-8756-f246a87edfca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904173594 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.904173594
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.2490090729
Short name T743
Test name
Test status
Simulation time 672226789 ps
CPU time 3.94 seconds
Started Jul 04 04:59:11 PM PDT 24
Finished Jul 04 04:59:15 PM PDT 24
Peak memory 204680 kb
Host smart-f728a88c-935c-47b8-b3f4-e736a136dbfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490090729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.2490090729
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.21698049
Short name T829
Test name
Test status
Simulation time 821844896 ps
CPU time 5.29 seconds
Started Jul 04 04:59:12 PM PDT 24
Finished Jul 04 04:59:17 PM PDT 24
Peak memory 212904 kb
Host smart-b0245a73-95a5-4ad5-af35-e5047bc4aef0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21698049 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_intr_smoke.21698049
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.4129322728
Short name T97
Test name
Test status
Simulation time 10158721358 ps
CPU time 20.82 seconds
Started Jul 04 04:59:11 PM PDT 24
Finished Jul 04 04:59:32 PM PDT 24
Peak memory 502464 kb
Host smart-f42031a5-982c-4b18-a144-8ee525d05290
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129322728 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.4129322728
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.480248286
Short name T1260
Test name
Test status
Simulation time 18237676562 ps
CPU time 15.34 seconds
Started Jul 04 04:59:05 PM PDT 24
Finished Jul 04 04:59:20 PM PDT 24
Peak memory 204780 kb
Host smart-28f0037a-b375-4dac-a725-4478d5eda880
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480248286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.480248286
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1465381999
Short name T320
Test name
Test status
Simulation time 1563729074 ps
CPU time 25.85 seconds
Started Jul 04 04:59:15 PM PDT 24
Finished Jul 04 04:59:41 PM PDT 24
Peak memory 231568 kb
Host smart-892b2576-96d7-4a8d-8f67-1a1cf1d6ec30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465381999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1465381999
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2507749514
Short name T857
Test name
Test status
Simulation time 42261705645 ps
CPU time 19.9 seconds
Started Jul 04 04:59:07 PM PDT 24
Finished Jul 04 04:59:28 PM PDT 24
Peak memory 460712 kb
Host smart-8be32408-ba8d-453e-b8aa-e78188b9404b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507749514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2507749514
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.512874249
Short name T583
Test name
Test status
Simulation time 30662873404 ps
CPU time 685.61 seconds
Started Jul 04 04:59:13 PM PDT 24
Finished Jul 04 05:10:38 PM PDT 24
Peak memory 1956192 kb
Host smart-e802b177-181c-4242-a619-db8458d1ef5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512874249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stretch.512874249
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.415778314
Short name T1380
Test name
Test status
Simulation time 18928823867 ps
CPU time 7.85 seconds
Started Jul 04 04:59:11 PM PDT 24
Finished Jul 04 04:59:19 PM PDT 24
Peak memory 216292 kb
Host smart-12414467-aabc-4aa2-8942-aaf2dfe41c10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415778314 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_timeout.415778314
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.1661286148
Short name T768
Test name
Test status
Simulation time 1318564029 ps
CPU time 15.39 seconds
Started Jul 04 04:59:19 PM PDT 24
Finished Jul 04 04:59:35 PM PDT 24
Peak memory 212852 kb
Host smart-7a15cacb-5831-4f54-8b0d-59e2b6aac26a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661286148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.1661286148
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3337823709
Short name T317
Test name
Test status
Simulation time 38188478 ps
CPU time 0.62 seconds
Started Jul 04 04:52:36 PM PDT 24
Finished Jul 04 04:52:36 PM PDT 24
Peak memory 204356 kb
Host smart-ef178647-445f-4980-af46-96e95bba97e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337823709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3337823709
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.1702169257
Short name T1182
Test name
Test status
Simulation time 268756249 ps
CPU time 3.65 seconds
Started Jul 04 04:52:29 PM PDT 24
Finished Jul 04 04:52:33 PM PDT 24
Peak memory 215536 kb
Host smart-60cef0a1-e658-45f1-a785-ea6a6ba6dca3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702169257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.1702169257
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.1805951930
Short name T1491
Test name
Test status
Simulation time 1640627191 ps
CPU time 48.28 seconds
Started Jul 04 04:52:30 PM PDT 24
Finished Jul 04 04:53:19 PM PDT 24
Peak memory 610844 kb
Host smart-6f1013a3-4b4b-4437-abfd-83cc17c37a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805951930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.1805951930
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1949670896
Short name T806
Test name
Test status
Simulation time 1391882779 ps
CPU time 92.88 seconds
Started Jul 04 04:52:28 PM PDT 24
Finished Jul 04 04:54:01 PM PDT 24
Peak memory 550296 kb
Host smart-91451e7c-7cf6-4662-bcc5-d00194c80fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949670896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1949670896
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.2510522050
Short name T714
Test name
Test status
Simulation time 346885456 ps
CPU time 9.27 seconds
Started Jul 04 04:52:21 PM PDT 24
Finished Jul 04 04:52:31 PM PDT 24
Peak memory 204732 kb
Host smart-cd7ab07c-1e11-4ee7-804a-cd18d7d3d1dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510522050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
2510522050
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.2444811844
Short name T1427
Test name
Test status
Simulation time 4977794641 ps
CPU time 377.11 seconds
Started Jul 04 04:52:24 PM PDT 24
Finished Jul 04 04:58:41 PM PDT 24
Peak memory 1454532 kb
Host smart-992f3432-8227-4483-a312-318ab1c85559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444811844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.2444811844
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.2838519363
Short name T654
Test name
Test status
Simulation time 798437064 ps
CPU time 8.49 seconds
Started Jul 04 04:53:50 PM PDT 24
Finished Jul 04 04:53:59 PM PDT 24
Peak memory 204628 kb
Host smart-d27dfc77-a221-4081-bf77-0a4381e92388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838519363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.2838519363
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.1653183163
Short name T478
Test name
Test status
Simulation time 1899697723 ps
CPU time 25.72 seconds
Started Jul 04 04:52:34 PM PDT 24
Finished Jul 04 04:53:00 PM PDT 24
Peak memory 309780 kb
Host smart-247591eb-24b3-4f8b-a560-9c66f855ece7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653183163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.1653183163
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.431586946
Short name T146
Test name
Test status
Simulation time 19563675 ps
CPU time 0.64 seconds
Started Jul 04 04:52:25 PM PDT 24
Finished Jul 04 04:52:26 PM PDT 24
Peak memory 204384 kb
Host smart-7475344e-7a13-4747-8f5f-7f0401124a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431586946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.431586946
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.2058219766
Short name T586
Test name
Test status
Simulation time 5067433771 ps
CPU time 179.5 seconds
Started Jul 04 04:52:25 PM PDT 24
Finished Jul 04 04:55:24 PM PDT 24
Peak memory 1335056 kb
Host smart-751bafc3-7ae9-45bd-8bf9-3215c93068c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058219766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.2058219766
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.2446671928
Short name T1012
Test name
Test status
Simulation time 743443785 ps
CPU time 2.44 seconds
Started Jul 04 04:52:25 PM PDT 24
Finished Jul 04 04:52:28 PM PDT 24
Peak memory 204524 kb
Host smart-8995e55e-817f-4b6e-8faf-2fcae6647eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446671928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.2446671928
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.2995462441
Short name T678
Test name
Test status
Simulation time 5904658103 ps
CPU time 26.54 seconds
Started Jul 04 04:52:23 PM PDT 24
Finished Jul 04 04:52:50 PM PDT 24
Peak memory 300736 kb
Host smart-f350ec7f-9070-4f6d-b583-b5ada3a8659c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995462441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.2995462441
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.1146358175
Short name T1108
Test name
Test status
Simulation time 1383929908 ps
CPU time 13.46 seconds
Started Jul 04 04:52:30 PM PDT 24
Finished Jul 04 04:52:44 PM PDT 24
Peak memory 212912 kb
Host smart-e790a913-1b66-441e-80ce-60d739183d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146358175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1146358175
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.1376672745
Short name T344
Test name
Test status
Simulation time 3531925482 ps
CPU time 3.95 seconds
Started Jul 04 04:52:31 PM PDT 24
Finished Jul 04 04:52:35 PM PDT 24
Peak memory 213008 kb
Host smart-f2f39dbb-31f1-4b74-a27a-60d42f02d264
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376672745 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1376672745
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.1437760290
Short name T612
Test name
Test status
Simulation time 442932219 ps
CPU time 0.86 seconds
Started Jul 04 04:52:31 PM PDT 24
Finished Jul 04 04:52:32 PM PDT 24
Peak memory 204468 kb
Host smart-14205f44-cf81-431a-bf5e-d000eb34eb1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437760290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.1437760290
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.2035575640
Short name T1458
Test name
Test status
Simulation time 313183952 ps
CPU time 0.88 seconds
Started Jul 04 04:52:30 PM PDT 24
Finished Jul 04 04:52:31 PM PDT 24
Peak memory 204508 kb
Host smart-561ef55f-f151-4acd-b3f5-eaee4817db3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035575640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.2035575640
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.841208574
Short name T256
Test name
Test status
Simulation time 1053882178 ps
CPU time 2.47 seconds
Started Jul 04 04:53:50 PM PDT 24
Finished Jul 04 04:53:53 PM PDT 24
Peak memory 204628 kb
Host smart-f324697d-b6e5-40b5-ba5a-cbe03a7e406b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841208574 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.841208574
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.1816693174
Short name T370
Test name
Test status
Simulation time 96403216 ps
CPU time 1.06 seconds
Started Jul 04 04:52:35 PM PDT 24
Finished Jul 04 04:52:36 PM PDT 24
Peak memory 204848 kb
Host smart-904ff4b8-de33-4824-8c3e-aae768db7b5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816693174 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.1816693174
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.2015654828
Short name T1414
Test name
Test status
Simulation time 1103389194 ps
CPU time 7.05 seconds
Started Jul 04 04:52:30 PM PDT 24
Finished Jul 04 04:52:37 PM PDT 24
Peak memory 210144 kb
Host smart-bd7cc20b-aef1-49b5-9e21-ffed03715089
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015654828 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.2015654828
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.1342483320
Short name T1465
Test name
Test status
Simulation time 4939304924 ps
CPU time 4.74 seconds
Started Jul 04 04:52:29 PM PDT 24
Finished Jul 04 04:52:34 PM PDT 24
Peak memory 309648 kb
Host smart-59ca3f1d-d015-4091-ae4e-27007ebe59cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342483320 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.1342483320
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.845105532
Short name T547
Test name
Test status
Simulation time 735261096 ps
CPU time 10.9 seconds
Started Jul 04 04:52:29 PM PDT 24
Finished Jul 04 04:52:40 PM PDT 24
Peak memory 204616 kb
Host smart-a364ba04-b38a-4f0f-a471-b7c92298f10b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845105532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targ
et_smoke.845105532
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.2731717456
Short name T1366
Test name
Test status
Simulation time 880716240 ps
CPU time 39.35 seconds
Started Jul 04 04:52:30 PM PDT 24
Finished Jul 04 04:53:09 PM PDT 24
Peak memory 204720 kb
Host smart-92f5bd6c-b82a-44f0-b151-f958f1261456
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731717456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.2731717456
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.3942398766
Short name T95
Test name
Test status
Simulation time 23202215694 ps
CPU time 63.31 seconds
Started Jul 04 04:52:30 PM PDT 24
Finished Jul 04 04:53:33 PM PDT 24
Peak memory 911316 kb
Host smart-1160da5b-215b-418c-98f0-54878d8265ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942398766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.3942398766
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.2464767187
Short name T914
Test name
Test status
Simulation time 29760473485 ps
CPU time 3417.28 seconds
Started Jul 04 04:52:29 PM PDT 24
Finished Jul 04 05:49:27 PM PDT 24
Peak memory 5916208 kb
Host smart-7bd963fc-1dad-48f2-aa3a-250abd63d2ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464767187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.2464767187
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1339679740
Short name T925
Test name
Test status
Simulation time 2425464016 ps
CPU time 7.07 seconds
Started Jul 04 04:52:29 PM PDT 24
Finished Jul 04 04:52:37 PM PDT 24
Peak memory 217968 kb
Host smart-13e5a207-87a7-4ecf-9388-7f06a09c4fa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339679740 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1339679740
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.194015490
Short name T1150
Test name
Test status
Simulation time 1259100153 ps
CPU time 14.71 seconds
Started Jul 04 04:52:34 PM PDT 24
Finished Jul 04 04:52:48 PM PDT 24
Peak memory 204724 kb
Host smart-2f4ee721-3c6b-4abc-814b-08bfca763b26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194015490 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.194015490
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2602445961
Short name T1025
Test name
Test status
Simulation time 44332401 ps
CPU time 0.69 seconds
Started Jul 04 04:52:41 PM PDT 24
Finished Jul 04 04:52:42 PM PDT 24
Peak memory 204436 kb
Host smart-695d6743-e5f1-4e54-b42e-a1a3041cbab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602445961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2602445961
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1101801423
Short name T959
Test name
Test status
Simulation time 3593936305 ps
CPU time 2.8 seconds
Started Jul 04 04:52:36 PM PDT 24
Finished Jul 04 04:52:39 PM PDT 24
Peak memory 213076 kb
Host smart-7ecccdce-4072-4387-bb96-8def992cc91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101801423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1101801423
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.2400110518
Short name T1525
Test name
Test status
Simulation time 363551627 ps
CPU time 6.8 seconds
Started Jul 04 04:52:37 PM PDT 24
Finished Jul 04 04:52:44 PM PDT 24
Peak memory 266720 kb
Host smart-b1889045-d6b7-4306-a338-a04b941c6029
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400110518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.2400110518
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2363877214
Short name T713
Test name
Test status
Simulation time 7903534895 ps
CPU time 59.66 seconds
Started Jul 04 04:52:33 PM PDT 24
Finished Jul 04 04:53:33 PM PDT 24
Peak memory 575456 kb
Host smart-fb0f0bed-3dca-40b8-a3c4-e5d6276e2e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363877214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2363877214
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1726988252
Short name T1358
Test name
Test status
Simulation time 6288709471 ps
CPU time 83.37 seconds
Started Jul 04 04:52:34 PM PDT 24
Finished Jul 04 04:53:58 PM PDT 24
Peak memory 745572 kb
Host smart-2dd91dac-d56b-4dbc-95b8-28ec8b6064b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726988252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1726988252
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.1294544577
Short name T417
Test name
Test status
Simulation time 279420362 ps
CPU time 1.1 seconds
Started Jul 04 04:52:35 PM PDT 24
Finished Jul 04 04:52:37 PM PDT 24
Peak memory 204596 kb
Host smart-5467ed82-eb0c-47c3-8bc3-dba7e336b512
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294544577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.1294544577
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3421880945
Short name T516
Test name
Test status
Simulation time 921331709 ps
CPU time 4.12 seconds
Started Jul 04 04:53:38 PM PDT 24
Finished Jul 04 04:53:43 PM PDT 24
Peak memory 203780 kb
Host smart-e15e3047-2677-4a0a-8782-2b510a2e4cba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421880945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3421880945
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.3158195138
Short name T744
Test name
Test status
Simulation time 8182116154 ps
CPU time 221.96 seconds
Started Jul 04 04:52:34 PM PDT 24
Finished Jul 04 04:56:17 PM PDT 24
Peak memory 975140 kb
Host smart-74fc108f-d4b2-46b7-973f-6915956b1e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158195138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.3158195138
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.3131378906
Short name T1464
Test name
Test status
Simulation time 1194723981 ps
CPU time 23.6 seconds
Started Jul 04 04:52:42 PM PDT 24
Finished Jul 04 04:53:06 PM PDT 24
Peak memory 204704 kb
Host smart-337e5e5d-8d74-4e3a-8c15-b79d9cf2970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131378906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3131378906
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.576244966
Short name T508
Test name
Test status
Simulation time 35562864303 ps
CPU time 33.76 seconds
Started Jul 04 04:52:42 PM PDT 24
Finished Jul 04 04:53:16 PM PDT 24
Peak memory 375528 kb
Host smart-bbe94694-3ba8-4c87-9c20-f739bf26a357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576244966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.576244966
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.3385354287
Short name T1513
Test name
Test status
Simulation time 64656750 ps
CPU time 0.67 seconds
Started Jul 04 04:52:37 PM PDT 24
Finished Jul 04 04:52:38 PM PDT 24
Peak memory 204356 kb
Host smart-f1f1b5aa-c130-45fc-aafd-3fb7d6d1079d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385354287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3385354287
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.249973239
Short name T397
Test name
Test status
Simulation time 12584403325 ps
CPU time 173.1 seconds
Started Jul 04 04:52:36 PM PDT 24
Finished Jul 04 04:55:29 PM PDT 24
Peak memory 229412 kb
Host smart-622c2eda-ee15-4a61-ad91-485e3d2aaad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249973239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.249973239
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.1166073897
Short name T479
Test name
Test status
Simulation time 2739443258 ps
CPU time 29.39 seconds
Started Jul 04 04:52:37 PM PDT 24
Finished Jul 04 04:53:06 PM PDT 24
Peak memory 204752 kb
Host smart-c26565a4-0ec3-41ed-8c5b-100f7cc0c17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166073897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.1166073897
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1169939588
Short name T368
Test name
Test status
Simulation time 4076109581 ps
CPU time 82.62 seconds
Started Jul 04 04:53:50 PM PDT 24
Finished Jul 04 04:55:13 PM PDT 24
Peak memory 403400 kb
Host smart-2386b6be-1c13-4f77-9676-9b35f605ca26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169939588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1169939588
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.2991687001
Short name T632
Test name
Test status
Simulation time 615071319 ps
CPU time 10.72 seconds
Started Jul 04 04:52:36 PM PDT 24
Finished Jul 04 04:52:47 PM PDT 24
Peak memory 213032 kb
Host smart-83b06fb2-975f-4c7f-b6fc-d96c323cb364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991687001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.2991687001
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.67958396
Short name T1409
Test name
Test status
Simulation time 1571285195 ps
CPU time 4.24 seconds
Started Jul 04 04:52:41 PM PDT 24
Finished Jul 04 04:52:45 PM PDT 24
Peak memory 212944 kb
Host smart-3fc62f1a-db43-42f0-b6db-580ca02a8da5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67958396 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_bad_addr.67958396
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.888242037
Short name T1092
Test name
Test status
Simulation time 1463277203 ps
CPU time 1.2 seconds
Started Jul 04 04:52:43 PM PDT 24
Finished Jul 04 04:52:44 PM PDT 24
Peak memory 204704 kb
Host smart-f5477bee-a11e-45aa-8fbf-e0b579f3391c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888242037 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_acq.888242037
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.3135691172
Short name T542
Test name
Test status
Simulation time 762217897 ps
CPU time 1.52 seconds
Started Jul 04 04:52:40 PM PDT 24
Finished Jul 04 04:52:42 PM PDT 24
Peak memory 204904 kb
Host smart-0234f1a5-8766-41a4-b653-68bb50d86a04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135691172 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.3135691172
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.1884846902
Short name T1403
Test name
Test status
Simulation time 1713441974 ps
CPU time 2.88 seconds
Started Jul 04 04:52:43 PM PDT 24
Finished Jul 04 04:52:46 PM PDT 24
Peak memory 204664 kb
Host smart-284180ff-0b86-4483-998f-3c06b6558c3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884846902 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.1884846902
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.3025680890
Short name T985
Test name
Test status
Simulation time 345605273 ps
CPU time 2.78 seconds
Started Jul 04 04:52:44 PM PDT 24
Finished Jul 04 04:52:47 PM PDT 24
Peak memory 204672 kb
Host smart-0b19bd77-d891-4629-a916-6548a5d2fb7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025680890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.3025680890
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3220951550
Short name T257
Test name
Test status
Simulation time 1919748170 ps
CPU time 6.34 seconds
Started Jul 04 04:52:37 PM PDT 24
Finished Jul 04 04:52:44 PM PDT 24
Peak memory 220508 kb
Host smart-1c850075-4a3f-43b7-819e-e1986de62cd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220951550 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3220951550
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.2258845253
Short name T428
Test name
Test status
Simulation time 17384696330 ps
CPU time 44.04 seconds
Started Jul 04 04:52:34 PM PDT 24
Finished Jul 04 04:53:18 PM PDT 24
Peak memory 1098076 kb
Host smart-98aa4fa7-1420-4096-9a68-c970eccc1c56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258845253 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.2258845253
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.3201479265
Short name T1087
Test name
Test status
Simulation time 1069512105 ps
CPU time 13.84 seconds
Started Jul 04 04:52:36 PM PDT 24
Finished Jul 04 04:52:50 PM PDT 24
Peak memory 204648 kb
Host smart-2122c188-909f-428f-b0bc-3a94092eb524
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201479265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.3201479265
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.2887206457
Short name T719
Test name
Test status
Simulation time 1138584383 ps
CPU time 47.1 seconds
Started Jul 04 04:52:34 PM PDT 24
Finished Jul 04 04:53:22 PM PDT 24
Peak memory 204656 kb
Host smart-0af1bf04-2430-4b39-8392-381c0aa2edaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887206457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.2887206457
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.2429653934
Short name T682
Test name
Test status
Simulation time 46043723294 ps
CPU time 293.51 seconds
Started Jul 04 04:52:35 PM PDT 24
Finished Jul 04 04:57:29 PM PDT 24
Peak memory 3166576 kb
Host smart-331bb4e7-d21a-4261-907b-5bff3fb7a9cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429653934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.2429653934
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.1131755095
Short name T833
Test name
Test status
Simulation time 2295253292 ps
CPU time 6.08 seconds
Started Jul 04 04:53:51 PM PDT 24
Finished Jul 04 04:53:57 PM PDT 24
Peak memory 212892 kb
Host smart-4ee8859d-cc0f-4462-bcdb-54cf5ab85ed0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131755095 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.1131755095
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.736097875
Short name T702
Test name
Test status
Simulation time 159711437 ps
CPU time 3.27 seconds
Started Jul 04 04:52:41 PM PDT 24
Finished Jul 04 04:52:45 PM PDT 24
Peak memory 204708 kb
Host smart-9f31e45c-6dbf-4f9d-a065-13965fe55dd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736097875 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.736097875
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2181041448
Short name T557
Test name
Test status
Simulation time 15354725 ps
CPU time 0.62 seconds
Started Jul 04 04:52:52 PM PDT 24
Finished Jul 04 04:52:54 PM PDT 24
Peak memory 204356 kb
Host smart-60a81e00-02eb-4dfd-8fbf-d14706df9f4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181041448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2181041448
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.382335892
Short name T50
Test name
Test status
Simulation time 76917968 ps
CPU time 1.38 seconds
Started Jul 04 04:53:50 PM PDT 24
Finished Jul 04 04:53:52 PM PDT 24
Peak memory 212904 kb
Host smart-c482ae93-88a6-47e8-b17e-8367d79d5b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382335892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.382335892
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.2429982740
Short name T409
Test name
Test status
Simulation time 375383193 ps
CPU time 19.27 seconds
Started Jul 04 04:52:42 PM PDT 24
Finished Jul 04 04:53:01 PM PDT 24
Peak memory 284524 kb
Host smart-a50cf608-c3a3-40fe-a6f5-394fd447926b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429982740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.2429982740
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.2099668353
Short name T1013
Test name
Test status
Simulation time 4879994155 ps
CPU time 33.78 seconds
Started Jul 04 04:52:44 PM PDT 24
Finished Jul 04 04:53:18 PM PDT 24
Peak memory 497928 kb
Host smart-62623001-9e36-45c6-a69e-a9df0a34a10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099668353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2099668353
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.3411751389
Short name T375
Test name
Test status
Simulation time 2612415887 ps
CPU time 78.03 seconds
Started Jul 04 04:52:45 PM PDT 24
Finished Jul 04 04:54:03 PM PDT 24
Peak memory 411252 kb
Host smart-1e7e113b-e787-43fa-808e-9ca88b83751f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411751389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3411751389
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.933242517
Short name T1331
Test name
Test status
Simulation time 92570953 ps
CPU time 0.87 seconds
Started Jul 04 04:52:42 PM PDT 24
Finished Jul 04 04:52:44 PM PDT 24
Peak memory 204344 kb
Host smart-c34eef15-7c45-4488-9633-f02c85c03256
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933242517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt
.933242517
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.4058402155
Short name T1113
Test name
Test status
Simulation time 139439294 ps
CPU time 7.16 seconds
Started Jul 04 04:52:42 PM PDT 24
Finished Jul 04 04:52:50 PM PDT 24
Peak memory 204720 kb
Host smart-8f018766-a4e4-41b9-84bc-b294b1e711ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058402155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
4058402155
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3349545570
Short name T1081
Test name
Test status
Simulation time 20399385538 ps
CPU time 370.06 seconds
Started Jul 04 04:52:44 PM PDT 24
Finished Jul 04 04:58:54 PM PDT 24
Peak memory 1340144 kb
Host smart-ac696734-b709-4791-938f-2b34cac4e55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349545570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3349545570
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.2024987741
Short name T43
Test name
Test status
Simulation time 1502533039 ps
CPU time 31.97 seconds
Started Jul 04 04:52:54 PM PDT 24
Finished Jul 04 04:53:26 PM PDT 24
Peak memory 204692 kb
Host smart-c185ae00-2178-4aff-9141-fba3d4490d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024987741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.2024987741
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.184011144
Short name T473
Test name
Test status
Simulation time 5776584685 ps
CPU time 80 seconds
Started Jul 04 04:52:52 PM PDT 24
Finished Jul 04 04:54:12 PM PDT 24
Peak memory 434944 kb
Host smart-e05142e9-95bb-412a-a014-f4f267c2e184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184011144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.184011144
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.456261163
Short name T1073
Test name
Test status
Simulation time 15904371 ps
CPU time 0.66 seconds
Started Jul 04 04:52:43 PM PDT 24
Finished Jul 04 04:52:44 PM PDT 24
Peak memory 204424 kb
Host smart-9cb2806e-f8f4-45fe-bce2-c122dcddcd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456261163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.456261163
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.3808518948
Short name T656
Test name
Test status
Simulation time 27339615712 ps
CPU time 375.32 seconds
Started Jul 04 04:52:44 PM PDT 24
Finished Jul 04 04:59:00 PM PDT 24
Peak memory 213108 kb
Host smart-34814c37-554b-4914-a58a-3ac936b7f8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808518948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3808518948
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.3002315608
Short name T977
Test name
Test status
Simulation time 218627612 ps
CPU time 7.71 seconds
Started Jul 04 04:52:42 PM PDT 24
Finished Jul 04 04:52:50 PM PDT 24
Peak memory 204520 kb
Host smart-2e0c1213-74cf-44e6-bc5e-0d16d5f4ca7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002315608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.3002315608
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2381208241
Short name T910
Test name
Test status
Simulation time 1201960608 ps
CPU time 56.28 seconds
Started Jul 04 04:52:42 PM PDT 24
Finished Jul 04 04:53:38 PM PDT 24
Peak memory 316780 kb
Host smart-e12019bb-4744-4c6d-8efa-45a3672482d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381208241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2381208241
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.3144652105
Short name T663
Test name
Test status
Simulation time 8037028789 ps
CPU time 29.45 seconds
Started Jul 04 04:52:42 PM PDT 24
Finished Jul 04 04:53:12 PM PDT 24
Peak memory 212944 kb
Host smart-6ab1b533-16e1-4b0e-a2a6-40a20215b4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144652105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.3144652105
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.196623895
Short name T1477
Test name
Test status
Simulation time 425465574 ps
CPU time 2.74 seconds
Started Jul 04 04:52:54 PM PDT 24
Finished Jul 04 04:52:57 PM PDT 24
Peak memory 204848 kb
Host smart-def302c7-cd00-4ccc-bf9d-622f76dca6eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196623895 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.196623895
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.40654026
Short name T842
Test name
Test status
Simulation time 151607636 ps
CPU time 0.92 seconds
Started Jul 04 04:52:49 PM PDT 24
Finished Jul 04 04:52:50 PM PDT 24
Peak memory 204448 kb
Host smart-9fb4a109-f966-45fe-8116-1525cd5a2303
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40654026 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_fifo_reset_acq.40654026
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.2395148491
Short name T941
Test name
Test status
Simulation time 179853601 ps
CPU time 1.12 seconds
Started Jul 04 04:52:53 PM PDT 24
Finished Jul 04 04:52:55 PM PDT 24
Peak memory 204500 kb
Host smart-28cfd16c-ee76-4663-be31-7ea2d0017c56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395148491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.2395148491
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.189636612
Short name T181
Test name
Test status
Simulation time 1010336604 ps
CPU time 1.74 seconds
Started Jul 04 04:52:52 PM PDT 24
Finished Jul 04 04:52:55 PM PDT 24
Peak memory 204568 kb
Host smart-985588e3-fc8c-4381-9bb6-93e4fa5a6335
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189636612 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.189636612
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.3329247912
Short name T759
Test name
Test status
Simulation time 114496636 ps
CPU time 0.8 seconds
Started Jul 04 04:52:52 PM PDT 24
Finished Jul 04 04:52:53 PM PDT 24
Peak memory 204496 kb
Host smart-06578606-c6c6-448d-b193-353916011542
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329247912 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.3329247912
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.3534904592
Short name T560
Test name
Test status
Simulation time 3781525754 ps
CPU time 6.1 seconds
Started Jul 04 04:52:53 PM PDT 24
Finished Jul 04 04:53:00 PM PDT 24
Peak memory 220964 kb
Host smart-b7bd720f-4a43-42e1-ab99-ee8e103ecfa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534904592 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.3534904592
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.3286881041
Short name T1437
Test name
Test status
Simulation time 2614851896 ps
CPU time 5.43 seconds
Started Jul 04 04:52:52 PM PDT 24
Finished Jul 04 04:52:59 PM PDT 24
Peak memory 204736 kb
Host smart-8615e9ae-b8d6-4f2c-a48e-6f85e0da364b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286881041 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.3286881041
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.2654148309
Short name T1454
Test name
Test status
Simulation time 1548976682 ps
CPU time 11.67 seconds
Started Jul 04 04:52:51 PM PDT 24
Finished Jul 04 04:53:03 PM PDT 24
Peak memory 204764 kb
Host smart-19a70404-2680-493f-b6bc-5ff2559f0568
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654148309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.2654148309
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.2773569048
Short name T245
Test name
Test status
Simulation time 2546325272 ps
CPU time 10.52 seconds
Started Jul 04 04:52:53 PM PDT 24
Finished Jul 04 04:53:04 PM PDT 24
Peak memory 205436 kb
Host smart-f8212711-0a16-45f4-8c23-97c0c9820ff8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773569048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.2773569048
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.3159388064
Short name T490
Test name
Test status
Simulation time 59740319290 ps
CPU time 244.63 seconds
Started Jul 04 04:52:50 PM PDT 24
Finished Jul 04 04:56:55 PM PDT 24
Peak memory 2659672 kb
Host smart-37bb8e58-b0cd-41a5-84db-edeb1ce6c203
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159388064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.3159388064
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.2236803105
Short name T510
Test name
Test status
Simulation time 33016257525 ps
CPU time 594.51 seconds
Started Jul 04 04:52:51 PM PDT 24
Finished Jul 04 05:02:45 PM PDT 24
Peak memory 3715916 kb
Host smart-c704bdd2-5d94-4b9c-8abd-c3dac4cdef0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236803105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.2236803105
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.3424918098
Short name T1429
Test name
Test status
Simulation time 4649692519 ps
CPU time 7.11 seconds
Started Jul 04 04:52:52 PM PDT 24
Finished Jul 04 04:52:59 PM PDT 24
Peak memory 221260 kb
Host smart-5d816423-54fb-4e86-81c7-c12d6713a9ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424918098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.3424918098
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.30208310
Short name T700
Test name
Test status
Simulation time 96624173 ps
CPU time 1.86 seconds
Started Jul 04 04:52:53 PM PDT 24
Finished Jul 04 04:52:55 PM PDT 24
Peak memory 204732 kb
Host smart-11f88242-345d-45de-b693-f45a4b95de23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30208310 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.30208310
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.1378711644
Short name T1067
Test name
Test status
Simulation time 18070207 ps
CPU time 0.62 seconds
Started Jul 04 04:53:25 PM PDT 24
Finished Jul 04 04:53:25 PM PDT 24
Peak memory 204440 kb
Host smart-d30f1ac9-c452-4016-970b-b5f71e2cbee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378711644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1378711644
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.3864464999
Short name T49
Test name
Test status
Simulation time 882441636 ps
CPU time 3.12 seconds
Started Jul 04 04:52:52 PM PDT 24
Finished Jul 04 04:52:55 PM PDT 24
Peak memory 229164 kb
Host smart-ade4f7c7-66c3-4851-bd2a-cfaa3f1d129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864464999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3864464999
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.2617692135
Short name T625
Test name
Test status
Simulation time 590778812 ps
CPU time 5.58 seconds
Started Jul 04 04:52:53 PM PDT 24
Finished Jul 04 04:52:59 PM PDT 24
Peak memory 268148 kb
Host smart-540913b0-1d5d-4a90-8b6b-862c41a5fe8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617692135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.2617692135
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.1057743627
Short name T81
Test name
Test status
Simulation time 1954712981 ps
CPU time 44.57 seconds
Started Jul 04 04:52:54 PM PDT 24
Finished Jul 04 04:53:39 PM PDT 24
Peak memory 466656 kb
Host smart-f1fa2632-2647-4def-8cbd-3b2f9c50022f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057743627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.1057743627
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2416494679
Short name T1216
Test name
Test status
Simulation time 1503192469 ps
CPU time 35.78 seconds
Started Jul 04 04:52:52 PM PDT 24
Finished Jul 04 04:53:29 PM PDT 24
Peak memory 488244 kb
Host smart-69563f25-d720-454f-9765-53071fbfffe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416494679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2416494679
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.1831938429
Short name T1296
Test name
Test status
Simulation time 439100754 ps
CPU time 0.94 seconds
Started Jul 04 04:52:51 PM PDT 24
Finished Jul 04 04:52:53 PM PDT 24
Peak memory 204348 kb
Host smart-6222fff5-4d34-42ac-9499-e6d8e115b3e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831938429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.1831938429
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.1661127729
Short name T606
Test name
Test status
Simulation time 135431816 ps
CPU time 3.21 seconds
Started Jul 04 04:52:53 PM PDT 24
Finished Jul 04 04:52:57 PM PDT 24
Peak memory 223256 kb
Host smart-18c7f2c5-98d7-4761-bde8-57eb88051ac4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661127729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
1661127729
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.981943036
Short name T74
Test name
Test status
Simulation time 3627099153 ps
CPU time 110.8 seconds
Started Jul 04 04:52:51 PM PDT 24
Finished Jul 04 04:54:43 PM PDT 24
Peak memory 1073796 kb
Host smart-5b42e760-3e8d-4583-88c3-5da3b560bdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981943036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.981943036
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2088511617
Short name T1097
Test name
Test status
Simulation time 1282726174 ps
CPU time 25.96 seconds
Started Jul 04 04:53:30 PM PDT 24
Finished Jul 04 04:53:57 PM PDT 24
Peak memory 204696 kb
Host smart-187316d4-d373-4ac7-b821-3db5fe756cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088511617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2088511617
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.3810670904
Short name T493
Test name
Test status
Simulation time 2749459695 ps
CPU time 25.73 seconds
Started Jul 04 04:53:24 PM PDT 24
Finished Jul 04 04:53:50 PM PDT 24
Peak memory 329112 kb
Host smart-c2faf875-cabb-463d-a063-c0b5beb6d818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810670904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.3810670904
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.3907069681
Short name T1476
Test name
Test status
Simulation time 19453300 ps
CPU time 0.67 seconds
Started Jul 04 04:52:51 PM PDT 24
Finished Jul 04 04:52:51 PM PDT 24
Peak memory 204412 kb
Host smart-ce393cba-d718-4c5d-9112-9be042f6dae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907069681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.3907069681
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1303913269
Short name T1106
Test name
Test status
Simulation time 24657961698 ps
CPU time 178.97 seconds
Started Jul 04 04:52:51 PM PDT 24
Finished Jul 04 04:55:50 PM PDT 24
Peak memory 1376716 kb
Host smart-67dfea28-ec73-4f8c-9756-4bdc944472bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303913269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1303913269
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.3974571501
Short name T1137
Test name
Test status
Simulation time 244151339 ps
CPU time 2.72 seconds
Started Jul 04 04:52:52 PM PDT 24
Finished Jul 04 04:52:56 PM PDT 24
Peak memory 204572 kb
Host smart-042caed1-680b-4224-8d4c-ac9999e0987e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974571501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.3974571501
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.838611786
Short name T1054
Test name
Test status
Simulation time 1761854016 ps
CPU time 91.63 seconds
Started Jul 04 04:52:54 PM PDT 24
Finished Jul 04 04:54:26 PM PDT 24
Peak memory 378372 kb
Host smart-e7931cc0-0bd9-44a4-b11d-f33db7fdbea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838611786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.838611786
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.4217576928
Short name T1019
Test name
Test status
Simulation time 243337360982 ps
CPU time 3104.44 seconds
Started Jul 04 04:52:54 PM PDT 24
Finished Jul 04 05:44:39 PM PDT 24
Peak memory 3937620 kb
Host smart-3cb2500d-efb3-4951-91d6-f2a91cc06ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217576928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.4217576928
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.47217904
Short name T865
Test name
Test status
Simulation time 925540582 ps
CPU time 16.56 seconds
Started Jul 04 04:52:53 PM PDT 24
Finished Jul 04 04:53:10 PM PDT 24
Peak memory 228980 kb
Host smart-ad04de61-cc8b-4c4b-af4a-99c57865641b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47217904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.47217904
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3433236993
Short name T544
Test name
Test status
Simulation time 4396948238 ps
CPU time 5.16 seconds
Started Jul 04 04:53:27 PM PDT 24
Finished Jul 04 04:53:33 PM PDT 24
Peak memory 213028 kb
Host smart-6938bdbf-1fb1-411f-891b-5722b5056e07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433236993 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3433236993
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3691075030
Short name T459
Test name
Test status
Simulation time 235900674 ps
CPU time 1.34 seconds
Started Jul 04 04:52:52 PM PDT 24
Finished Jul 04 04:52:54 PM PDT 24
Peak memory 204648 kb
Host smart-a9078a0f-b8c4-4216-863b-e728aea69db7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691075030 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3691075030
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.1251364081
Short name T1115
Test name
Test status
Simulation time 1785832302 ps
CPU time 1.39 seconds
Started Jul 04 04:52:49 PM PDT 24
Finished Jul 04 04:52:51 PM PDT 24
Peak memory 204920 kb
Host smart-3376485b-1a92-4b24-9777-66c1e02554f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251364081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.1251364081
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.81654960
Short name T32
Test name
Test status
Simulation time 559935040 ps
CPU time 2.81 seconds
Started Jul 04 04:53:23 PM PDT 24
Finished Jul 04 04:53:26 PM PDT 24
Peak memory 204820 kb
Host smart-2fb0c015-804c-46c1-8885-92d0e3a3c340
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81654960 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.81654960
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.1983873825
Short name T1179
Test name
Test status
Simulation time 387470664 ps
CPU time 1.47 seconds
Started Jul 04 04:53:24 PM PDT 24
Finished Jul 04 04:53:26 PM PDT 24
Peak memory 204492 kb
Host smart-712061e1-8cd2-4220-8f9e-ade787ffb501
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983873825 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.1983873825
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.1909180057
Short name T1360
Test name
Test status
Simulation time 3741161940 ps
CPU time 5.54 seconds
Started Jul 04 04:52:51 PM PDT 24
Finished Jul 04 04:52:57 PM PDT 24
Peak memory 212928 kb
Host smart-5a8fca16-e413-4d71-902a-d9fcda83472d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909180057 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.1909180057
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.4213516575
Short name T525
Test name
Test status
Simulation time 7725729647 ps
CPU time 3.41 seconds
Started Jul 04 04:52:54 PM PDT 24
Finished Jul 04 04:52:57 PM PDT 24
Peak memory 204916 kb
Host smart-5e7156c2-394e-45fa-9ed2-1a70968c12aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213516575 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.4213516575
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.3574658141
Short name T1448
Test name
Test status
Simulation time 499144404 ps
CPU time 17.31 seconds
Started Jul 04 04:52:53 PM PDT 24
Finished Jul 04 04:53:11 PM PDT 24
Peak memory 204700 kb
Host smart-8c4ef73d-884d-4056-a20e-994d9b6d7f6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574658141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.3574658141
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.359556095
Short name T304
Test name
Test status
Simulation time 1993880332 ps
CPU time 5.03 seconds
Started Jul 04 04:52:51 PM PDT 24
Finished Jul 04 04:52:56 PM PDT 24
Peak memory 205380 kb
Host smart-33d7e345-3c23-4604-8ab4-5ce5f91b1666
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359556095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_rd.359556095
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3450657776
Short name T866
Test name
Test status
Simulation time 23327146556 ps
CPU time 13.91 seconds
Started Jul 04 04:52:53 PM PDT 24
Finished Jul 04 04:53:07 PM PDT 24
Peak memory 286612 kb
Host smart-5faa0ea1-6e86-41b3-a259-d18569d6ccbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450657776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3450657776
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.1922151444
Short name T799
Test name
Test status
Simulation time 38158844045 ps
CPU time 86.94 seconds
Started Jul 04 04:52:51 PM PDT 24
Finished Jul 04 04:54:19 PM PDT 24
Peak memory 442560 kb
Host smart-2bdd4f67-f7c2-4cff-97c9-43679e67b56b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922151444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.1922151444
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.1853063189
Short name T513
Test name
Test status
Simulation time 5154373013 ps
CPU time 7.22 seconds
Started Jul 04 04:52:51 PM PDT 24
Finished Jul 04 04:52:58 PM PDT 24
Peak memory 213064 kb
Host smart-c23e3a05-f3cd-4353-b440-757a2a52bb96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853063189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.1853063189
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.2490212464
Short name T918
Test name
Test status
Simulation time 225502606 ps
CPU time 2.77 seconds
Started Jul 04 04:53:23 PM PDT 24
Finished Jul 04 04:53:26 PM PDT 24
Peak memory 204728 kb
Host smart-61cf345d-301f-42db-9389-5d8ea1892d90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490212464 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.2490212464
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.4063532538
Short name T419
Test name
Test status
Simulation time 23946617 ps
CPU time 0.63 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:36 PM PDT 24
Peak memory 204372 kb
Host smart-94e992be-dd90-4e5f-a806-f411b9d5014d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063532538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.4063532538
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.2793589206
Short name T1475
Test name
Test status
Simulation time 577251431 ps
CPU time 1.54 seconds
Started Jul 04 04:53:22 PM PDT 24
Finished Jul 04 04:53:23 PM PDT 24
Peak memory 213100 kb
Host smart-cb77886c-5728-4f1f-9a0c-fcb4620e0e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793589206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.2793589206
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.4021147148
Short name T1178
Test name
Test status
Simulation time 5477406664 ps
CPU time 22.54 seconds
Started Jul 04 04:53:23 PM PDT 24
Finished Jul 04 04:53:46 PM PDT 24
Peak memory 289440 kb
Host smart-01d58a2b-f4c8-4719-87a6-580cd51530ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021147148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.4021147148
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.2449018877
Short name T1529
Test name
Test status
Simulation time 1609466717 ps
CPU time 48.47 seconds
Started Jul 04 04:53:21 PM PDT 24
Finished Jul 04 04:54:10 PM PDT 24
Peak memory 602992 kb
Host smart-cf1c03bc-9337-4a09-b1f2-afabb23c784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449018877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.2449018877
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.2128799457
Short name T812
Test name
Test status
Simulation time 6962301972 ps
CPU time 60.23 seconds
Started Jul 04 04:53:24 PM PDT 24
Finished Jul 04 04:54:24 PM PDT 24
Peak memory 638476 kb
Host smart-a81f4723-ce3b-4668-a258-0caca3d2e945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128799457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.2128799457
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.727356770
Short name T600
Test name
Test status
Simulation time 243768162 ps
CPU time 0.83 seconds
Started Jul 04 04:53:24 PM PDT 24
Finished Jul 04 04:53:25 PM PDT 24
Peak memory 204368 kb
Host smart-d18b4eeb-493e-4a6a-8f13-cf5efc2dc30f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727356770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt
.727356770
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.3317771475
Short name T1001
Test name
Test status
Simulation time 224677199 ps
CPU time 3.14 seconds
Started Jul 04 04:53:23 PM PDT 24
Finished Jul 04 04:53:26 PM PDT 24
Peak memory 204716 kb
Host smart-3b24bad5-332d-4766-b2fd-89d28daab52a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317771475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
3317771475
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1234199189
Short name T599
Test name
Test status
Simulation time 18797307803 ps
CPU time 430.02 seconds
Started Jul 04 04:53:23 PM PDT 24
Finished Jul 04 05:00:33 PM PDT 24
Peak memory 1499424 kb
Host smart-64730e18-047b-4795-be52-3f76bb05d856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234199189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1234199189
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.3917944433
Short name T253
Test name
Test status
Simulation time 1022470445 ps
CPU time 3.11 seconds
Started Jul 04 04:53:26 PM PDT 24
Finished Jul 04 04:53:29 PM PDT 24
Peak memory 204840 kb
Host smart-bac0ba16-c899-40f2-9fa3-3352976e8156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917944433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.3917944433
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2245832961
Short name T519
Test name
Test status
Simulation time 3261642510 ps
CPU time 13.83 seconds
Started Jul 04 04:53:22 PM PDT 24
Finished Jul 04 04:53:36 PM PDT 24
Peak memory 280220 kb
Host smart-c25c2dc3-b239-462d-b172-f1fd798a6855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245832961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2245832961
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.3336644768
Short name T947
Test name
Test status
Simulation time 30175406 ps
CPU time 0.71 seconds
Started Jul 04 04:53:23 PM PDT 24
Finished Jul 04 04:53:24 PM PDT 24
Peak memory 204408 kb
Host smart-c32ae0e7-2c06-4020-97b8-d7eeba83b4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336644768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.3336644768
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2244775824
Short name T697
Test name
Test status
Simulation time 70092837392 ps
CPU time 1297.84 seconds
Started Jul 04 04:53:22 PM PDT 24
Finished Jul 04 05:15:00 PM PDT 24
Peak memory 204840 kb
Host smart-19d4bf2b-49d6-4ff6-add8-d40710a78e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244775824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2244775824
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.1657744044
Short name T1379
Test name
Test status
Simulation time 100960355 ps
CPU time 4.06 seconds
Started Jul 04 04:53:22 PM PDT 24
Finished Jul 04 04:53:26 PM PDT 24
Peak memory 205112 kb
Host smart-57721155-9403-455d-b2f8-be971884e13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657744044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.1657744044
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.768419177
Short name T722
Test name
Test status
Simulation time 12137228139 ps
CPU time 21.54 seconds
Started Jul 04 04:53:25 PM PDT 24
Finished Jul 04 04:53:47 PM PDT 24
Peak memory 265520 kb
Host smart-e4b5fdce-22e6-4f08-889d-6539898de832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768419177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.768419177
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.1350453675
Short name T1188
Test name
Test status
Simulation time 12685157346 ps
CPU time 945.55 seconds
Started Jul 04 04:53:24 PM PDT 24
Finished Jul 04 05:09:10 PM PDT 24
Peak memory 1959236 kb
Host smart-0d575d9a-99a7-468a-9475-aa20496b46a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350453675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.1350453675
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.2527723212
Short name T1503
Test name
Test status
Simulation time 1100873365 ps
CPU time 26.17 seconds
Started Jul 04 04:53:22 PM PDT 24
Finished Jul 04 04:53:48 PM PDT 24
Peak memory 212820 kb
Host smart-e77a6e12-d25a-4a24-ae99-5f3215292641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527723212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2527723212
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.4272506001
Short name T1424
Test name
Test status
Simulation time 580542408 ps
CPU time 3.31 seconds
Started Jul 04 04:53:22 PM PDT 24
Finished Jul 04 04:53:25 PM PDT 24
Peak memory 204712 kb
Host smart-ed9ef926-d63d-4896-98d4-9ea515fe33fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272506001 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.4272506001
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1436603096
Short name T1500
Test name
Test status
Simulation time 542502182 ps
CPU time 1.16 seconds
Started Jul 04 04:53:23 PM PDT 24
Finished Jul 04 04:53:24 PM PDT 24
Peak memory 204700 kb
Host smart-3cbc1e0b-125b-4dee-b393-bb9984d6ab20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436603096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.1436603096
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2379140987
Short name T1000
Test name
Test status
Simulation time 379635159 ps
CPU time 1.28 seconds
Started Jul 04 04:53:21 PM PDT 24
Finished Jul 04 04:53:22 PM PDT 24
Peak memory 204652 kb
Host smart-4e9b8a2f-479f-43d3-a98d-4643e45dc19f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379140987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2379140987
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.36296561
Short name T852
Test name
Test status
Simulation time 1381393548 ps
CPU time 1.98 seconds
Started Jul 04 04:53:22 PM PDT 24
Finished Jul 04 04:53:24 PM PDT 24
Peak memory 204660 kb
Host smart-047017ed-e308-4d9c-90e6-fcdee0223420
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36296561 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.36296561
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.1876680905
Short name T1082
Test name
Test status
Simulation time 229616947 ps
CPU time 1.11 seconds
Started Jul 04 04:53:24 PM PDT 24
Finished Jul 04 04:53:25 PM PDT 24
Peak memory 204420 kb
Host smart-49856244-0435-4159-aef3-e289ab2704ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876680905 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.1876680905
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.643065298
Short name T316
Test name
Test status
Simulation time 912048762 ps
CPU time 5.32 seconds
Started Jul 04 04:53:24 PM PDT 24
Finished Jul 04 04:53:29 PM PDT 24
Peak memory 218056 kb
Host smart-f25ed94e-107d-4ed6-87bc-9adf6f338c2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643065298 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_intr_smoke.643065298
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.1505458430
Short name T425
Test name
Test status
Simulation time 11301509303 ps
CPU time 24.53 seconds
Started Jul 04 04:53:25 PM PDT 24
Finished Jul 04 04:53:49 PM PDT 24
Peak memory 595132 kb
Host smart-7b8df2ae-a9bd-486f-a662-faa5bca897a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505458430 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.1505458430
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.1696507826
Short name T176
Test name
Test status
Simulation time 1079920645 ps
CPU time 11.07 seconds
Started Jul 04 04:53:23 PM PDT 24
Finished Jul 04 04:53:34 PM PDT 24
Peak memory 204692 kb
Host smart-73a441dd-8265-41df-80fe-93b96c360010
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696507826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.1696507826
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.3919496481
Short name T634
Test name
Test status
Simulation time 600538742 ps
CPU time 24.42 seconds
Started Jul 04 04:53:22 PM PDT 24
Finished Jul 04 04:53:47 PM PDT 24
Peak memory 204808 kb
Host smart-006e164a-a9b9-4b33-a499-33170f753054
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919496481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.3919496481
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.192890187
Short name T1492
Test name
Test status
Simulation time 46447985041 ps
CPU time 108.59 seconds
Started Jul 04 04:53:28 PM PDT 24
Finished Jul 04 04:55:16 PM PDT 24
Peak memory 1481300 kb
Host smart-b08989cf-85a0-4a8c-9f36-4286852fc8f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192890187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_wr.192890187
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2064250527
Short name T1207
Test name
Test status
Simulation time 24010719004 ps
CPU time 1275.06 seconds
Started Jul 04 04:53:23 PM PDT 24
Finished Jul 04 05:14:38 PM PDT 24
Peak memory 6047408 kb
Host smart-82ad358c-52ec-42dd-b382-846f39fb2f5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064250527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2064250527
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.284454809
Short name T386
Test name
Test status
Simulation time 1306307808 ps
CPU time 6.65 seconds
Started Jul 04 04:53:25 PM PDT 24
Finished Jul 04 04:53:32 PM PDT 24
Peak memory 212924 kb
Host smart-a2ae97e9-53f9-4482-875b-b57b6134bf75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284454809 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_timeout.284454809
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.2231258986
Short name T1362
Test name
Test status
Simulation time 239823615 ps
CPU time 3.41 seconds
Started Jul 04 04:53:35 PM PDT 24
Finished Jul 04 04:53:39 PM PDT 24
Peak memory 204740 kb
Host smart-3dc91c15-ea86-48ca-802f-f58a5b84352b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231258986 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.2231258986
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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