Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

163080

1

T1

539

T2

120

T3

90

ack

14509

1

T1

13

T2

34

T3

1

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	635	1			T1	4		T2	1		T3	1
high	36342	1			T1	115		T2	28		T3	21
med	66322	1			T1	209		T2	62		T3	31
sml	73627	1			T1	221		T2	62		T3	38
all_zero	663	1			T1	3		T2	1		T36	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88548

1

T1

277

T2

73

T3

44

auto[1]

89041

1

T1

275

T2

81

T3

47

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121808

1

T1

361

T2

116

T3

63

auto[1]

55781

1

T1

191

T2

38

T3

28

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169917

1

T1

541

T2

138

T3

91

auto[1]

7672

1

T1

11

T2

16

T34

4

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167652

1

T1

540

T2

121

T3

90

auto[1]

9937

1

T1

12

T2

33

T3

1

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168620

1

T1

545

T2

122

T3

90

auto[1]

8969

1

T1

7

T2

32

T3

1

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88548

1

T1

277

T2

73

T3

44

auto[1]

89041

1

T1

275

T2

81

T3

47

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121808

1

T1

361

T2

116

T3

63

auto[1]

55781

1

T1

191

T2

38

T3

28

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169917

1

T1

541

T2

138

T3

91

auto[1]

7672

1

T1

11

T2

16

T34

4

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167652

1

T1

540

T2

121

T3

90

auto[1]

9937

1

T1

12

T2

33

T3

1

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168620

1

T1

545

T2

122

T3

90

auto[1]

8969

1

T1

7

T2

32

T3

1

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T133

2

T42

1

T245

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

7

1

T2

1

T142

1

T101

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T79

1

T246

1

T247

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

282

1

T2

1

T36

2

T54

5

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

140

1

T1

1

T54

1

T43

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

131

1

T54

2

T43

1

T48

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

520

1

T1

3

T2

3

T34

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

249

1

T2

2

T54

2

T47

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

248

1

T2

2

T54

1

T47

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

520

1

T1

1

T36

2

T44

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

264

1

T36

2

T45

1

T43

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

276

1

T2

3

T54

3

T47

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T248

1

T249

2

T250

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T251

1

T252

1

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T253

1

T254

1

T109

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	51836	1			T1	175		T2	27		T3	29
write_address_byte	9937	1			T1	12		T2	33		T3	1
read_with_ack	2212	1			T1	5		T34	2		T44	3
read_with_nack	5460	1			T1	6		T2	16		T34	2
stop_byte	8969	1			T1	7		T2	32		T3	1
write_address_byte_nak	4884	1			T1	11		T2	23		T34	4
data_byte_nack	163080	1			T1	539		T2	120		T3	90
stop_byte_nack	5348	1			T1	6		T2	23		T3	1
nakok_byte_nack	81881	1			T1	270		T2	64		T3	47
nakok_addr_byte_nack	2425	1			T1	7		T2	10		T34	1