SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
i2c_env_pkg.interrupts_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 45 | 0 | 45 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_acq_stretch | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_acq_stretch_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_acq_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_acq_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_cmd_complete | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_cmd_complete_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_fmt_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_fmt_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_host_timeout | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_host_timeout_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_nak | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_nak_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_overflow | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_overflow_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_scl_interference | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_scl_interference_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_interference | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_interference_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_unstable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_unstable_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_stretch_timeout | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_stretch_timeout_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_stretch | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_stretch_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_unexp_stop | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_unexp_stop_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 984835 | 1 | T1 | 4 | T2 | 6041 | T3 | 4 | ||||
auto[1] | 484 | 1 | T133 | 19 | T50 | 16 | T42 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 215 | 1 | T48 | 1 | T133 | 7 | T50 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 984905 | 1 | T1 | 4 | T2 | 6041 | T3 | 4 | ||||
auto[1] | 518 | 1 | T7 | 1 | T17 | 1 | T48 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 196 | 1 | T48 | 3 | T133 | 8 | T50 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 217263 | 1 | T1 | 3 | T2 | 88 | T3 | 3 | ||||
auto[1] | 768185 | 1 | T1 | 1 | T2 | 5953 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 211 | 1 | T133 | 6 | T50 | 1 | T42 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 112735 | 1 | T1 | 2 | T2 | 346 | T3 | 2 | ||||
auto[1] | 868874 | 1 | T1 | 2 | T2 | 5695 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 178 | 1 | T48 | 1 | T133 | 4 | T50 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 984865 | 1 | T1 | 4 | T2 | 6041 | T3 | 4 | ||||
auto[1] | 531 | 1 | T133 | 26 | T50 | 11 | T42 | 29 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 201 | 1 | T133 | 6 | T50 | 3 | T42 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 984924 | 1 | T1 | 4 | T2 | 6041 | T3 | 4 | ||||
auto[1] | 489 | 1 | T48 | 1 | T133 | 14 | T61 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 196 | 1 | T48 | 1 | T133 | 5 | T50 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 984927 | 1 | T1 | 4 | T2 | 6041 | T3 | 4 | ||||
auto[1] | 490 | 1 | T48 | 7 | T133 | 13 | T50 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 187 | 1 | T48 | 1 | T133 | 7 | T50 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 984414 | 1 | T1 | 4 | T2 | 6039 | T3 | 4 | ||||
auto[1] | 1019 | 1 | T2 | 2 | T36 | 15 | T43 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 208 | 1 | T133 | 6 | T50 | 2 | T42 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 981089 | 1 | T1 | 4 | T2 | 6041 | T3 | 4 | ||||
auto[1] | 592 | 1 | T133 | 12 | T50 | 7 | T42 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 197 | 1 | T48 | 3 | T133 | 8 | T50 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 981240 | 1 | T1 | 4 | T2 | 6041 | T3 | 4 | ||||
auto[1] | 497 | 1 | T133 | 15 | T50 | 3 | T42 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 183 | 1 | T48 | 1 | T133 | 5 | T50 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 981173 | 1 | T1 | 4 | T2 | 6041 | T3 | 4 | ||||
auto[1] | 488 | 1 | T48 | 5 | T133 | 7 | T50 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 192 | 1 | T48 | 2 | T133 | 8 | T50 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 952246 | 1 | T1 | 3 | T2 | 5887 | T3 | 4 | ||||
auto[1] | 29477 | 1 | T1 | 1 | T2 | 154 | T36 | 156 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 197 | 1 | T48 | 2 | T133 | 9 | T50 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 984872 | 1 | T1 | 4 | T2 | 6041 | T3 | 4 | ||||
auto[1] | 399 | 1 | T48 | 5 | T133 | 11 | T50 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 199 | 1 | T48 | 1 | T133 | 6 | T50 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 5916 | 1 | T1 | 2 | T2 | 10 | T3 | 2 | ||||
auto[1] | 975683 | 1 | T1 | 2 | T2 | 6031 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 198 | 1 | T48 | 2 | T133 | 5 | T50 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 984856 | 1 | T1 | 4 | T2 | 6041 | T3 | 4 | ||||
auto[1] | 487 | 1 | T133 | 24 | T50 | 12 | T42 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 204 | 1 | T48 | 1 | T133 | 10 | T50 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |