Group : i2c_env_pkg::i2c_scl_sda_override_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : i2c_env_pkg::i2c_scl_sda_override_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.scl_sda_override_cg 100.00 1 100 1 64 64




Group Instance : i2c_env_pkg.scl_sda_override_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.scl_sda_override_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group Instance i2c_env_pkg.scl_sda_override_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_sclval 2 0 2 100.00 100 1 1 2
cp_sdaval 2 0 2 100.00 100 1 1 2
cp_txorvden 2 0 2 100.00 100 1 1 2


Crosses for Group Instance i2c_env_pkg.scl_sda_override_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_txorvden_x_sclval 4 0 4 100.00 100 1 1 0
cp_txorvden_x_sdaval 4 0 4 100.00 100 1 1 0


Summary for Variable cp_sclval

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sclval

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 354 1 T68 5 T81 6 T82 12
auto[1] 377 1 T68 6 T81 8 T82 7



Summary for Variable cp_sdaval

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sdaval

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 369 1 T68 7 T81 7 T82 10
auto[1] 362 1 T68 4 T81 7 T82 9



Summary for Variable cp_txorvden

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_txorvden

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 383 1 T68 5 T81 6 T82 13
auto[1] 348 1 T68 6 T81 8 T82 6



Summary for Cross cp_txorvden_x_sclval

Samples crossed: cp_txorvden cp_sclval
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_txorvden_x_sclval

Bins
cp_txorvdencp_sclvalCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 181 1 T68 2 T81 2 T82 6
auto[0] auto[1] 202 1 T68 3 T81 4 T82 7
auto[1] auto[0] 173 1 T68 3 T81 4 T82 6
auto[1] auto[1] 175 1 T68 3 T81 4 T269 4



Summary for Cross cp_txorvden_x_sdaval

Samples crossed: cp_txorvden cp_sdaval
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_txorvden_x_sdaval

Bins
cp_txorvdencp_sdavalCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 187 1 T68 3 T81 3 T82 6
auto[0] auto[1] 196 1 T68 2 T81 3 T82 7
auto[1] auto[0] 182 1 T68 4 T81 4 T82 4
auto[1] auto[1] 166 1 T68 2 T81 4 T82 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%