Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40930106	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12186934

1

T1

24539

T2

1896

T3

829

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52345081	1			T1	121193		T2	12433		T3	2221
values[0x0]	385595	1			T1	312		T2	300		T3	55
values[0x1]	386364	1			T1	319		T2	260		T3	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28812210	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

24304830

1

T1

53697

T2

5386

T3

1239

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	208576	1			T1	475		T2	49		T8	133
valid_sources[0x01]	213021	1			T1	490		T2	43		T8	120
valid_sources[0x02]	189328	1			T1	426		T2	47		T8	149
valid_sources[0x03]	210561	1			T1	421		T2	57		T8	82
valid_sources[0x04]	190958	1			T1	471		T2	47		T5	4
valid_sources[0x05]	186839	1			T1	477		T2	52		T8	108
valid_sources[0x06]	223337	1			T1	474		T2	34		T7	1
valid_sources[0x07]	192067	1			T1	464		T2	63		T8	73
valid_sources[0x08]	241460	1			T1	485		T2	44		T7	1
valid_sources[0x09]	190517	1			T1	482		T2	49		T8	101
valid_sources[0x0a]	216244	1			T1	484		T2	55		T8	144
valid_sources[0x0b]	188339	1			T1	489		T2	46		T8	77
valid_sources[0x0c]	195786	1			T1	489		T2	59		T7	2
valid_sources[0x0d]	189334	1			T1	471		T2	49		T8	133
valid_sources[0x0e]	199591	1			T1	462		T2	55		T7	1
valid_sources[0x0f]	212726	1			T1	472		T2	55		T7	1
valid_sources[0x10]	191550	1			T1	490		T2	54		T7	2
valid_sources[0x11]	185251	1			T1	491		T2	57		T5	1
valid_sources[0x12]	187825	1			T1	476		T2	57		T7	1
valid_sources[0x13]	189086	1			T1	514		T2	49		T7	2
valid_sources[0x14]	221885	1			T1	467		T2	49		T5	3
valid_sources[0x15]	215203	1			T1	483		T2	50		T8	99
valid_sources[0x16]	202905	1			T1	495		T2	49		T8	108
valid_sources[0x17]	207594	1			T1	465		T2	51		T7	2
valid_sources[0x18]	203949	1			T1	430		T2	58		T7	1
valid_sources[0x19]	214522	1			T1	544		T2	43		T8	73
valid_sources[0x1a]	194444	1			T1	475		T2	52		T4	2
valid_sources[0x1b]	198649	1			T1	492		T2	56		T7	1
valid_sources[0x1c]	195844	1			T1	465		T2	54		T5	1
valid_sources[0x1d]	194140	1			T1	468		T2	53		T7	1
valid_sources[0x1e]	180074	1			T1	490		T2	41		T7	2
valid_sources[0x1f]	197577	1			T1	453		T2	63		T8	158
valid_sources[0x20]	215200	1			T1	481		T2	51		T7	2
valid_sources[0x21]	189862	1			T1	444		T2	50		T8	129
valid_sources[0x22]	199905	1			T1	473		T2	48		T5	1
valid_sources[0x23]	218469	1			T1	468		T2	56		T5	8
valid_sources[0x24]	184915	1			T1	465		T2	50		T5	3
valid_sources[0x25]	213800	1			T1	477		T2	41		T5	7
valid_sources[0x26]	197545	1			T1	442		T2	47		T8	141
valid_sources[0x27]	202530	1			T1	496		T2	64		T5	1
valid_sources[0x28]	203718	1			T1	456		T2	44		T8	152
valid_sources[0x29]	189901	1			T1	460		T2	46		T4	1
valid_sources[0x2a]	220328	1			T1	478		T2	53		T7	1
valid_sources[0x2b]	234941	1			T1	514		T2	40		T8	121
valid_sources[0x2c]	198068	1			T1	449		T2	43		T7	2
valid_sources[0x2d]	190219	1			T1	451		T2	46		T7	1
valid_sources[0x2e]	196200	1			T1	469		T2	53		T8	89
valid_sources[0x2f]	305857	1			T1	476		T2	49		T7	2
valid_sources[0x30]	185646	1			T1	486		T2	46		T7	1
valid_sources[0x31]	214694	1			T1	477		T2	42		T7	1
valid_sources[0x32]	198188	1			T1	498		T2	57		T7	2
valid_sources[0x33]	202353	1			T1	438		T2	54		T7	3
valid_sources[0x34]	231264	1			T1	480		T2	43		T7	1
valid_sources[0x35]	261780	1			T1	535		T2	61		T7	3
valid_sources[0x36]	204333	1			T1	473		T2	55		T7	1
valid_sources[0x37]	198464	1			T1	480		T2	54		T7	1
valid_sources[0x38]	204611	1			T1	486		T2	61		T7	1
valid_sources[0x39]	237523	1			T1	484		T2	44		T8	128
valid_sources[0x3a]	190897	1			T1	476		T2	53		T7	1
valid_sources[0x3b]	211332	1			T1	471		T2	61		T7	1
valid_sources[0x3c]	204116	1			T1	473		T2	64		T7	2
valid_sources[0x3d]	244690	1			T1	476		T2	51		T7	3
valid_sources[0x3e]	208364	1			T1	472		T2	65		T5	1
valid_sources[0x3f]	210637	1			T1	470		T2	54		T7	1
valid_sources[0x40]	204314	1			T1	445		T2	41		T8	85
valid_sources[0x41]	212098	1			T1	479		T2	50		T8	105
valid_sources[0x42]	235457	1			T1	489		T2	37		T8	91
valid_sources[0x43]	198889	1			T1	443		T2	55		T5	16
valid_sources[0x44]	193682	1			T1	449		T2	58		T5	6
valid_sources[0x45]	193204	1			T1	466		T2	61		T5	5
valid_sources[0x46]	188312	1			T1	522		T2	51		T7	2
valid_sources[0x47]	204916	1			T1	464		T2	46		T7	2
valid_sources[0x48]	200064	1			T1	482		T2	54		T5	1
valid_sources[0x49]	212199	1			T1	508		T2	56		T7	1
valid_sources[0x4a]	193924	1			T1	465		T2	47		T7	3
valid_sources[0x4b]	200945	1			T1	468		T2	43		T7	1
valid_sources[0x4c]	198465	1			T1	511		T2	45		T7	4
valid_sources[0x4d]	198537	1			T1	463		T2	52		T7	6
valid_sources[0x4e]	220844	1			T1	448		T2	52		T8	171
valid_sources[0x4f]	222197	1			T1	499		T2	62		T4	2
valid_sources[0x50]	262678	1			T1	454		T2	52		T7	2
valid_sources[0x51]	186989	1			T1	464		T2	56		T5	20
valid_sources[0x52]	200338	1			T1	506		T2	49		T8	121
valid_sources[0x53]	208959	1			T1	483		T2	59		T4	1
valid_sources[0x54]	236531	1			T1	519		T2	47		T8	131
valid_sources[0x55]	187086	1			T1	490		T2	53		T8	152
valid_sources[0x56]	182253	1			T1	475		T2	40		T8	126
valid_sources[0x57]	209540	1			T1	467		T2	45		T8	81
valid_sources[0x58]	195259	1			T1	469		T2	55		T7	1
valid_sources[0x59]	234681	1			T1	476		T2	56		T5	8
valid_sources[0x5a]	204557	1			T1	457		T2	67		T7	1
valid_sources[0x5b]	199037	1			T1	457		T2	43		T7	4
valid_sources[0x5c]	202631	1			T1	497		T2	51		T8	95
valid_sources[0x5d]	209391	1			T1	445		T2	38		T5	1
valid_sources[0x5e]	201468	1			T1	457		T2	46		T5	5
valid_sources[0x5f]	208552	1			T1	481		T2	52		T5	5
valid_sources[0x60]	210354	1			T1	478		T2	56		T8	114
valid_sources[0x61]	175965	1			T1	472		T2	48		T7	1
valid_sources[0x62]	204954	1			T1	507		T2	53		T7	2
valid_sources[0x63]	213646	1			T1	474		T2	55		T7	1
valid_sources[0x64]	200191	1			T1	494		T2	52		T5	4
valid_sources[0x65]	311023	1			T1	495		T2	53		T5	9
valid_sources[0x66]	196215	1			T1	441		T2	61		T7	2
valid_sources[0x67]	199343	1			T1	449		T2	57		T7	5
valid_sources[0x68]	201766	1			T1	475		T2	48		T8	75
valid_sources[0x69]	197515	1			T1	531		T2	50		T5	6
valid_sources[0x6a]	340239	1			T1	475		T2	52		T5	13
valid_sources[0x6b]	198041	1			T1	480		T2	52		T5	5
valid_sources[0x6c]	203383	1			T1	456		T2	41		T7	1
valid_sources[0x6d]	195085	1			T1	483		T2	67		T8	80
valid_sources[0x6e]	209915	1			T1	480		T2	49		T7	3
valid_sources[0x6f]	196814	1			T1	480		T2	60		T5	1
valid_sources[0x70]	204996	1			T1	452		T2	53		T5	3
valid_sources[0x71]	197166	1			T1	460		T2	44		T7	2
valid_sources[0x72]	190346	1			T1	449		T2	48		T4	1
valid_sources[0x73]	205975	1			T1	457		T2	44		T8	111
valid_sources[0x74]	209343	1			T1	462		T2	52		T8	126
valid_sources[0x75]	223561	1			T1	456		T2	60		T8	90
valid_sources[0x76]	203944	1			T1	479		T2	48		T7	1
valid_sources[0x77]	203568	1			T1	487		T2	43		T7	3
valid_sources[0x78]	227454	1			T1	453		T2	60		T7	1
valid_sources[0x79]	216819	1			T1	468		T2	62		T5	12
valid_sources[0x7a]	196854	1			T1	481		T2	49		T5	4
valid_sources[0x7b]	211862	1			T1	520		T2	60		T8	106
valid_sources[0x7c]	205807	1			T1	480		T2	36		T7	2
valid_sources[0x7d]	218011	1			T1	458		T2	57		T5	1
valid_sources[0x7e]	198290	1			T1	491		T2	62		T8	94
valid_sources[0x7f]	202201	1			T1	453		T2	49		T8	127
valid_sources[0x80]	192850	1			T1	447		T2	42		T8	114

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

11814961

1

T1

24268

T2

1516

T3

782

values[0x0]

all_enables

biggest_size

215828

1

T1

162

T2

218

T3

29

values[0x1]

all_enables

biggest_size

156145

1

T1

109

T2

162

T3

18