Group : i2c_env_pkg::i2c_fifo_level_cg
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Group : i2c_env_pkg::i2c_fifo_level_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
82.35 55.88 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.rx_fifo_level_cg 29.41 1 100 1 64 64
i2c_env_pkg.fmt_fifo_level_cg 82.35 1 100 1 64 64




Group Instance : i2c_env_pkg.rx_fifo_level_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
29.41 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.rx_fifo_level_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 4 5 55.56
Crosses 8 8 0 0.00


Variables for Group Instance i2c_env_pkg.rx_fifo_level_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_fifolvl 5 4 1 20.00 100 1 1 0
cp_irq 2 0 2 100.00 100 1 1 2
cp_rst 2 0 2 100.00 100 1 1 2


Crosses for Group Instance i2c_env_pkg.rx_fifo_level_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_fifo_threshold_cross 8 8 0 0.00 100 1 1 0



Group Instance : i2c_env_pkg.fmt_fifo_level_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
82.35 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.fmt_fifo_level_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 8 3 5 62.50


Variables for Group Instance i2c_env_pkg.fmt_fifo_level_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_fifolvl 5 0 5 100.00 100 1 1 0
cp_irq 2 0 2 100.00 100 1 1 2
cp_rst 2 0 2 100.00 100 1 1 2


Crosses for Group Instance i2c_env_pkg.fmt_fifo_level_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_fifo_threshold_cross 8 3 5 62.50 100 1 1 0


Summary for Variable cp_fifolvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 4 1 20.00


User Defined Bins for cp_fifolvl

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
lvl[1] 0 1 1
lvl[4] 0 1 1
lvl[8] 0 1 1
lvl[16] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others 3521 1 T1 1 T2 1 T3 1



Summary for Variable cp_irq

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_irq

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3488 1 T1 1 T2 1 T3 1
auto[1] 33 1 T35 1 T64 1 T213 1



Summary for Variable cp_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 981 1 T16 2 T35 1 T64 1
auto[1] 2540 1 T1 1 T2 1 T3 1



Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 8 0 0.00 8
Automatically Generated Cross Bins 8 8 0 0.00 8
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_fifo_threshold_cross

Element holes
cp_fifolvlcp_irqCOUNTAT LEASTNUMBERSTATUS
[lvl[1] , lvl[4] , lvl[8] , lvl[16]] * -- -- 8


User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
reserved_values 0 Excluded


Summary for Variable cp_fifolvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_fifolvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others 3183 1 T1 1 T2 1 T3 1
lvl[1] 232 1 T43 2 T133 1 T55 6
lvl[4] 50 1 T55 4 T214 2 T215 2
lvl[8] 48 1 T57 2 T215 2 T216 2
lvl[16] 8 1 T55 2 T217 2 T218 2



Summary for Variable cp_irq

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_irq

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3175 1 T1 1 T2 1 T3 1
auto[1] 346 1 T16 2 T64 2 T30 2



Summary for Variable cp_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 640 1 T16 2 T35 2 T64 2
auto[1] 2881 1 T1 1 T2 1 T3 1



Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 3 5 62.50 3
Automatically Generated Cross Bins 8 3 5 62.50 3
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_fifo_threshold_cross

Uncovered bins
cp_fifolvlcp_irqCOUNTAT LEASTNUMBERSTATUS
[lvl[4] , lvl[8] , lvl[16]] [auto[1]] -- -- 3


Covered bins
cp_fifolvlcp_irqCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lvl[1] auto[0] 212 1 T55 6 T56 10 T57 6
lvl[1] auto[1] 20 1 T43 2 T133 1 T219 2
lvl[4] auto[0] 50 1 T55 4 T214 2 T215 2
lvl[8] auto[0] 48 1 T57 2 T215 2 T216 2
lvl[16] auto[0] 8 1 T55 2 T217 2 T218 2


User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
reserved_values 0 Excluded

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