Module Definition
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Module Instance : tb.dut.i2c_core.intr_hw_fmt_threshold

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_rx_threshold

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_acq_threshold

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_rx_overflow

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_controller_halt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_scl_interference

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_sda_interference

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_stretch_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_sda_unstable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_cmd_complete

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_tx_stretch

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_tx_threshold

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_acq_overflow

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_unexp_stop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i2c_core.intr_hw_host_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.38 97.74 78.46 93.33 100.00 i2c_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_fmt_threshold

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_rx_threshold

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_acq_threshold

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_controller_halt

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_tx_stretch

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_tx_threshold

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_acq_overflow

Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 2 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_rx_overflow

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_scl_interference

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_sda_interference

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_stretch_timeout

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_sda_unstable

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_cmd_complete

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_unexp_stop

SCORELINE
100.00 100.00
tb.dut.i2c_core.intr_hw_host_timeout

Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_fmt_threshold

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_rx_threshold

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_acq_threshold

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_controller_halt

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_tx_stretch

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_tx_threshold

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_acq_overflow

TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T50
10CoveredT1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T50
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T7,T8
11CoveredT1,T2,T3

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_rx_overflow

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_scl_interference

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_sda_interference

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_stretch_timeout

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_sda_unstable

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_cmd_complete

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_unexp_stop

SCORECOND
100.00 100.00
tb.dut.i2c_core.intr_hw_host_timeout

TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT48,T133,T50

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT48,T133,T50

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT34,T44,T45
11CoveredT1,T2,T5

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_fmt_threshold

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_rx_threshold

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_acq_threshold

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_controller_halt

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_tx_stretch

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_tx_threshold

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_acq_overflow

Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T48,T133,T50
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_rx_overflow

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_scl_interference

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_sda_interference

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_stretch_timeout

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_sda_unstable

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_cmd_complete

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_unexp_stop

SCOREBRANCH
100.00 100.00
tb.dut.i2c_core.intr_hw_host_timeout

Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_intr_hw
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 22035 22035 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22035 22035 0 0
T1 15 15 0 0
T2 15 15 0 0
T3 15 15 0 0
T4 15 15 0 0
T5 15 15 0 0
T6 15 15 0 0
T7 15 15 0 0
T8 15 15 0 0
T9 15 15 0 0
T10 15 15 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 2 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T42
10CoveredT1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T42
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T7,T8
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T48,T133,T50
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_fmt_threshold
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 2 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT133,T50,T42
10CoveredT1,T2,T35

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT133,T50,T42
10CoveredT1,T2,T35

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT133,T50,T42
11CoveredT1,T2,T35

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T48,T133,T50
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_threshold
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_threshold
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 2 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_threshold
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T50
10CoveredT6,T7,T17

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T50
10CoveredT6,T7,T17

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT6,T7,T17

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_threshold
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T48,T133,T50
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_threshold
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T37,T83
10CoveredT48,T133,T50

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT48,T133,T50

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T37,T133
10CoveredT48,T37,T133

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT133,T50,T42
11CoveredT48,T37,T133

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_rx_overflow
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_controller_halt
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 2 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_controller_halt
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T50
10CoveredT5,T9,T34

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T50
10CoveredT5,T9,T34

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT5,T9,T34

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_controller_halt
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T48,T133,T50
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_controller_halt
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T9,T43
10CoveredT48,T133,T50

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT48,T133,T50

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T9,T43
10CoveredT5,T9,T43

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT5,T9,T43

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_scl_interference
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T9,T43
10CoveredT48,T133,T50

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT48,T133,T50

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T9,T43
10CoveredT5,T9,T43

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT5,T9,T43

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_interference
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT48,T133,T50

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT48,T133,T50

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT34,T44,T45
11CoveredT1,T2,T5

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_stretch_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T9,T43
10CoveredT48,T133,T50

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT48,T133,T50

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T9,T43
10CoveredT5,T9,T43

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT5,T9,T43

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_sda_unstable
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT133,T50,T42

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT133,T50,T42

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT133,T42,T75
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_cmd_complete
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 2 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T50
10CoveredT8,T10,T16

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T50
10CoveredT8,T10,T16

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT133,T50,T42
11CoveredT8,T10,T16

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T48,T133,T50
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_stretch
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_threshold
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 2 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_threshold
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T42
10CoveredT1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T42
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T7,T8
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_threshold
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T48,T133,T50
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_tx_threshold
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
Line No.TotalCoveredPercent
TOTAL1010100.00
ALWAYS7544100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 2 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T50
10CoveredT6,T17,T14

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T133,T50
10CoveredT6,T17,T14

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT6,T17,T14

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 75 3 3 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T48,T133,T50
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_acq_overflow
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T15
10CoveredT48,T133,T50

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT48,T133,T50

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T48,T133
10CoveredT14,T48,T133

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT14,T133,T50

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_unexp_stop
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT69,T70,T71
10CoveredT133,T50,T42

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT48,T133,T50
11CoveredT133,T50,T42

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT133,T69,T70
10CoveredT133,T69,T70

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT133,T50,T42
11CoveredT133,T69,T70

Branch Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.i2c_core.intr_hw_host_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1469 1469 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1469 1469 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%