Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	361477363	0	0	0
ctrl_rd_A	361477363	2723	0	0
host_fifo_config_rd_A	361477363	4662	0	0
host_nack_handler_timeout_rd_A	361477363	1557	0	0
host_timeout_ctrl_rd_A	361477363	1335	0	0
intr_enable_rd_A	361477363	5420	0	0
ovrd_rd_A	361477363	2536	0	0
target_fifo_config_rd_A	361477363	1757	0	0
target_id_rd_A	361477363	2045	0	0
target_timeout_ctrl_rd_A	361477363	1490	0	0
timeout_ctrl_rd_A	361477363	1883	0	0
timing0_rd_A	361477363	1484	0	0
timing1_rd_A	361477363	1712	0	0
timing2_rd_A	361477363	1577	0	0
timing3_rd_A	361477363	1568	0	0
timing4_rd_A	361477363	1558	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	2723	0	0
T85	2708	18	0	0
T86	5835	23	0	0
T87	8040	219	0	0
T88	7211	145	0	0
T89	7373	178	0	0
T90	45637	314	0	0
T91	23252	143	0	0
T92	2821	35	0	0
T93	3078	17	0	0
T94	3110	31	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	4662	0	0
T11	194112	0	0	0
T32	8616	0	0	0
T37	184835	0	0	0
T40	253303	0	0	0
T41	94746	0	0	0
T43	717795	172	0	0
T48	159400	0	0	0
T68	2771	0	0	0
T95	0	204	0	0
T96	0	158	0	0
T97	0	68	0	0
T98	0	140	0	0
T99	0	223	0	0
T100	0	178	0	0
T101	0	160	0	0
T102	0	85	0	0
T103	0	109	0	0
T104	878	0	0	0
T105	39508	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	1557	0	0
T85	2708	12	0	0
T86	5835	30	0	0
T87	8040	36	0	0
T88	7211	38	0	0
T89	7373	67	0	0
T90	45637	285	0	0
T91	23252	104	0	0
T92	2821	12	0	0
T94	3110	23	0	0
T106	27207	239	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	1335	0	0
T86	5835	30	0	0
T87	8040	42	0	0
T88	7211	45	0	0
T89	7373	40	0	0
T90	45637	217	0	0
T91	23252	136	0	0
T92	2821	10	0	0
T93	3078	4	0	0
T94	3110	21	0	0
T106	27207	228	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	5420	0	0
T79	678758	8	0	0
T85	0	8	0	0
T86	0	27	0	0
T102	0	28	0	0
T103	0	15	0	0
T107	108006	6	0	0
T108	0	19	0	0
T109	0	29	0	0
T110	0	16	0	0
T111	0	35	0	0
T112	2110	0	0	0
T113	14412	0	0	0
T114	44358	0	0	0
T115	110936	0	0	0
T116	710548	0	0	0
T117	33873	0	0	0
T118	110498	0	0	0
T119	26949	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	2536	0	0
T11	194112	0	0	0
T12	14597	0	0	0
T32	8616	0	0	0
T37	184835	0	0	0
T41	94746	0	0	0
T68	2771	39	0	0
T82	0	77	0	0
T104	878	0	0	0
T105	39508	0	0	0
T120	0	42	0	0
T121	0	36	0	0
T122	0	19	0	0
T123	0	35	0	0
T124	0	79	0	0
T125	0	31	0	0
T126	0	55	0	0
T127	0	63	0	0
T128	1108	0	0	0
T129	8353	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	1757	0	0
T85	2708	6	0	0
T86	5835	48	0	0
T87	8040	59	0	0
T88	7211	57	0	0
T89	7373	50	0	0
T90	45637	315	0	0
T91	23252	107	0	0
T92	2821	16	0	0
T93	3078	6	0	0
T94	3110	11	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	2045	0	0
T85	2708	2	0	0
T86	5835	15	0	0
T87	8040	119	0	0
T88	7211	84	0	0
T89	7373	84	0	0
T90	45637	222	0	0
T91	23252	140	0	0
T92	2821	22	0	0
T93	3078	17	0	0
T94	3110	15	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	1490	0	0
T85	2708	9	0	0
T86	5835	31	0	0
T87	8040	39	0	0
T88	7211	52	0	0
T89	7373	40	0	0
T90	45637	257	0	0
T91	23252	114	0	0
T92	2821	6	0	0
T93	3078	3	0	0
T94	3110	22	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	1883	0	0
T85	2708	12	0	0
T86	5835	26	0	0
T87	8040	54	0	0
T88	7211	86	0	0
T89	7373	61	0	0
T90	45637	321	0	0
T91	23252	147	0	0
T92	2821	21	0	0
T93	3078	2	0	0
T94	3110	4	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	1484	0	0
T85	2708	1	0	0
T86	5835	16	0	0
T87	8040	55	0	0
T88	7211	53	0	0
T89	7373	45	0	0
T90	45637	252	0	0
T91	23252	109	0	0
T92	2821	4	0	0
T93	3078	14	0	0
T94	3110	6	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	1712	0	0
T85	2708	4	0	0
T86	5835	8	0	0
T87	8040	51	0	0
T88	7211	64	0	0
T89	7373	36	0	0
T90	45637	233	0	0
T91	23252	129	0	0
T92	2821	20	0	0
T93	3078	2	0	0
T94	3110	27	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	1577	0	0
T85	2708	7	0	0
T86	5835	18	0	0
T87	8040	88	0	0
T88	7211	25	0	0
T89	7373	49	0	0
T90	45637	251	0	0
T91	23252	111	0	0
T92	2821	6	0	0
T93	3078	11	0	0
T94	3110	1	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	1568	0	0
T85	2708	8	0	0
T86	5835	15	0	0
T87	8040	51	0	0
T88	7211	57	0	0
T89	7373	61	0	0
T90	45637	265	0	0
T91	23252	127	0	0
T92	2821	3	0	0
T94	3110	34	0	0
T130	2618	1	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361477363	1558	0	0
T85	2708	11	0	0
T86	5835	47	0	0
T87	8040	59	0	0
T88	7211	48	0	0
T89	7373	52	0	0
T90	45637	282	0	0
T91	23252	118	0	0
T92	2821	7	0	0
T93	3078	2	0	0
T94	3110	10	0	0