Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1016333	1			T1	8		T2	3		T3	3
all_values[1]	1016333	1			T1	8		T2	3		T3	3
all_values[2]	1016333	1			T1	8		T2	3		T3	3
all_values[3]	1016333	1			T1	8		T2	3		T3	3
all_values[4]	1016333	1			T1	8		T2	3		T3	3
all_values[5]	1016333	1			T1	8		T2	3		T3	3
all_values[6]	1016333	1			T1	8		T2	3		T3	3
all_values[7]	1016333	1			T1	8		T2	3		T3	3
all_values[8]	1016333	1			T1	8		T2	3		T3	3
all_values[9]	1016333	1			T1	8		T2	3		T3	3
all_values[10]	1016333	1			T1	8		T2	3		T3	3
all_values[11]	1016333	1			T1	8		T2	3		T3	3
all_values[12]	1016333	1			T1	8		T2	3		T3	3
all_values[13]	1016333	1			T1	8		T2	3		T3	3
all_values[14]	1016333	1			T1	8		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12441744

1

T1

120

T2

39

T3

40

auto[1]

2803251

1

T2

6

T3

5

T4

2951

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13390405

1

T1

120

T2

45

T3

45

auto[1]

1854590

1

T42

3917

T52

48832

T81

9643

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	94942	1			T1	8		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	13376	1			T52	362		T81	9		T237	1897
all_values[0]	auto[1]	auto[0]	792847	1			T2	2		T3	2		T4	1296
all_values[0]	auto[1]	auto[1]	115168	1			T52	2893		T81	635		T237	7291
all_values[1]	auto[0]	auto[0]	887284	1			T1	8		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	128149	1			T42	297		T52	3219		T81	641
all_values[1]	auto[1]	auto[0]	618	1			T34	2		T38	1		T251	1
all_values[1]	auto[1]	auto[1]	282	1			T42	4		T52	36		T81	3
all_values[2]	auto[0]	auto[0]	887743	1			T1	8		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	128308	1			T52	3251		T81	642		T237	9187
all_values[2]	auto[1]	auto[0]	50	1			T261	1		T262	1		T258	1
all_values[2]	auto[1]	auto[1]	232	1			T52	4		T81	1		T237	2
all_values[3]	auto[0]	auto[0]	887483	1			T1	8		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	128590	1			T42	298		T52	3252		T81	637
all_values[3]	auto[1]	auto[1]	260	1			T42	3		T52	4		T81	4
all_values[4]	auto[0]	auto[0]	887465	1			T1	8		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	128618	1			T42	299		T52	3254		T81	640
all_values[4]	auto[1]	auto[0]	17	1			T33	1		T251	1		T252	1
all_values[4]	auto[1]	auto[1]	233	1			T42	2		T52	2		T81	4
all_values[5]	auto[0]	auto[0]	910635	1			T1	8		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	105455	1			T42	302		T52	3250		T81	637
all_values[5]	auto[1]	auto[1]	243	1			T52	5		T81	3		T235	4
all_values[6]	auto[0]	auto[0]	890353	1			T1	8		T2	3		T3	3
all_values[6]	auto[0]	auto[1]	125720	1			T42	302		T52	3251		T81	641
all_values[6]	auto[1]	auto[1]	260	1			T52	4		T81	1		T235	10
all_values[7]	auto[0]	auto[0]	858391	1			T1	8		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	123983	1			T42	221		T52	3105		T81	637
all_values[7]	auto[1]	auto[0]	29111	1			T2	1		T4	274		T7	9
all_values[7]	auto[1]	auto[1]	4848	1			T42	81		T52	151		T81	6
all_values[8]	auto[0]	auto[0]	887495	1			T1	8		T2	3		T3	3
all_values[8]	auto[0]	auto[1]	128575	1			T42	299		T52	3251		T81	639
all_values[8]	auto[1]	auto[1]	263	1			T42	3		T52	5		T81	5
all_values[9]	auto[0]	auto[0]	148043	1			T1	8		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	23469	1			T42	278		T52	83		T81	634
all_values[9]	auto[1]	auto[0]	739850	1			T2	1		T3	1		T4	3
all_values[9]	auto[1]	auto[1]	104971	1			T42	23		T52	3172		T81	8
all_values[10]	auto[0]	auto[0]	903519	1			T1	8		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	112575	1			T42	299		T52	3252		T81	640
all_values[10]	auto[1]	auto[1]	239	1			T42	1		T52	4		T81	3
all_values[11]	auto[0]	auto[0]	2760	1			T1	8		T2	1		T3	1
all_values[11]	auto[0]	auto[1]	583	1			T42	18		T52	26		T81	1
all_values[11]	auto[1]	auto[0]	893913	1			T2	2		T3	2		T4	1378
all_values[11]	auto[1]	auto[1]	119077	1			T42	284		T52	3230		T81	643
all_values[12]	auto[0]	auto[0]	892108	1			T1	8		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	123985	1			T42	299		T52	3253		T81	642
all_values[12]	auto[1]	auto[0]	15	1			T261	1		T262	1		T263	1
all_values[12]	auto[1]	auto[1]	225	1			T42	2		T52	2		T81	1
all_values[13]	auto[0]	auto[0]	894308	1			T1	8		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	121765	1			T42	298		T52	3248		T81	639
all_values[13]	auto[1]	auto[1]	260	1			T42	3		T52	7		T81	3
all_values[14]	auto[0]	auto[0]	901455	1			T1	8		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	114609	1			T42	298		T52	3253		T81	638
all_values[14]	auto[1]	auto[1]	269	1			T42	3		T52	3		T81	6