Group : i2c_env_pkg::i2c_scl_stretch_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : i2c_env_pkg::i2c_scl_stretch_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv


Summary for Group i2c_env_pkg::i2c_scl_stretch_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group i2c_env_pkg::i2c_scl_stretch_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acq_fifo_size 2 0 2 100.00 100 1 1 0
cp_host_mode_stretch 1 0 1 100.00 100 1 1 0
cp_target_scl_stretch_addr_write 1 0 1 100.00 100 1 1 0
cp_tx_fifo_size 2 0 2 100.00 100 1 1 0


Crosses for Group i2c_env_pkg::i2c_scl_stretch_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_target_scl_stretch_read 4 0 4 100.00 100 1 1 0


Summary for Variable cp_acq_fifo_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_acq_fifo_size

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_empty 57312640 1 T6 94115 T11 1196 T12 35409
empty 96309608 1 T1 729 T2 222936 T4 601083


Summary for Variable cp_host_mode_stretch

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_host_mode_stretch

Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
stretch 61019110 1 T1 729 T2 134100 T4 601083


Summary for Variable cp_target_scl_stretch_addr_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_target_scl_stretch_addr_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
addr_write_byte_stretch 302822 1 T18 1094 T19 14183 T20 8684


Summary for Variable cp_tx_fifo_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_tx_fifo_size

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_empty 5539747 1 T11 934 T12 35393 T16 121
empty 148082533 1 T1 729 T2 222936 T4 601083


Summary for Cross cp_target_scl_stretch_read

Samples crossed: cp_acq_fifo_size cp_tx_fifo_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for cp_target_scl_stretch_read

Bins
cp_acq_fifo_sizecp_tx_fifo_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
empty not_empty 2038 1 T16 79 T17 26 T22 72
empty empty 317871 1 T11 2532 T21 4712 T23 193


User Defined Cross Bins for cp_target_scl_stretch_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read_byte_stretch 144722 1 T11 262 T12 16 T21 256
scl_stretch_read_request 5679672 1 T11 1170 T12 35409 T16 42

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%