Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1016333	1			T1	8		T2	3		T3	3
all_pins[1]	1016333	1			T1	8		T2	3		T3	3
all_pins[2]	1016333	1			T1	8		T2	3		T3	3
all_pins[3]	1016333	1			T1	8		T2	3		T3	3
all_pins[4]	1016333	1			T1	8		T2	3		T3	3
all_pins[5]	1016333	1			T1	8		T2	3		T3	3
all_pins[6]	1016333	1			T1	8		T2	3		T3	3
all_pins[7]	1016333	1			T1	8		T2	3		T3	3
all_pins[8]	1016333	1			T1	8		T2	3		T3	3
all_pins[9]	1016333	1			T1	8		T2	3		T3	3
all_pins[10]	1016333	1			T1	8		T2	3		T3	3
all_pins[11]	1016333	1			T1	8		T2	3		T3	3
all_pins[12]	1016333	1			T1	8		T2	3		T3	3
all_pins[13]	1016333	1			T1	8		T2	3		T3	3
all_pins[14]	1016333	1			T1	8		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	12446677	1			T1	120		T2	39		T3	40
values[0x1]	2798318	1			T2	6		T3	5		T4	2960
transitions[0x0=>0x1]	2797065	1			T2	6		T3	5		T4	2960
transitions[0x1=>0x0]	2795869	1			T2	5		T3	4		T4	2959

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	111648	1			T1	8		T2	1		T3	1
all_pins[0]	values[0x1]	904685	1			T2	2		T3	2		T4	1296
all_pins[0]	transitions[0x0=>0x1]	903879	1			T2	2		T3	2		T4	1296
all_pins[0]	transitions[0x1=>0x0]	97	1			T251	1		T42	1		T52	1
all_pins[1]	values[0x0]	1015430	1			T1	8		T2	3		T3	3
all_pins[1]	values[0x1]	903	1			T34	2		T38	1		T251	1
all_pins[1]	transitions[0x0=>0x1]	876	1			T34	2		T38	1		T251	1
all_pins[1]	transitions[0x1=>0x0]	147	1			T261	1		T262	1		T52	1
all_pins[2]	values[0x0]	1016159	1			T1	8		T2	3		T3	3
all_pins[2]	values[0x1]	174	1			T261	1		T262	1		T52	1
all_pins[2]	transitions[0x0=>0x1]	146	1			T261	1		T262	1		T52	1
all_pins[2]	transitions[0x1=>0x0]	106	1			T52	2		T81	3		T235	2
all_pins[3]	values[0x0]	1016199	1			T1	8		T2	3		T3	3
all_pins[3]	values[0x1]	134	1			T52	2		T81	3		T235	3
all_pins[3]	transitions[0x0=>0x1]	103	1			T52	1		T81	3		T235	3
all_pins[3]	transitions[0x1=>0x0]	116	1			T33	1		T251	1		T81	3
all_pins[4]	values[0x0]	1016186	1			T1	8		T2	3		T3	3
all_pins[4]	values[0x1]	147	1			T33	1		T251	1		T52	1
all_pins[4]	transitions[0x0=>0x1]	116	1			T33	1		T251	1		T52	1
all_pins[4]	transitions[0x1=>0x0]	97	1			T52	3		T81	2		T235	3
all_pins[5]	values[0x0]	1016205	1			T1	8		T2	3		T3	3
all_pins[5]	values[0x1]	128	1			T52	3		T81	2		T235	3
all_pins[5]	transitions[0x0=>0x1]	100	1			T81	2		T235	1		T236	2
all_pins[5]	transitions[0x1=>0x0]	92	1			T235	5		T236	3		T286	4
all_pins[6]	values[0x0]	1016213	1			T1	8		T2	3		T3	3
all_pins[6]	values[0x1]	120	1			T52	3		T235	7		T236	3
all_pins[6]	transitions[0x0=>0x1]	99	1			T52	3		T235	4		T236	3
all_pins[6]	transitions[0x1=>0x0]	37229	1			T2	1		T4	283		T7	9
all_pins[7]	values[0x0]	979083	1			T1	8		T2	2		T3	3
all_pins[7]	values[0x1]	37250	1			T2	1		T4	283		T7	9
all_pins[7]	transitions[0x0=>0x1]	37209	1			T2	1		T4	283		T7	9
all_pins[7]	transitions[0x1=>0x0]	84	1			T42	1		T52	1		T81	2
all_pins[8]	values[0x0]	1016208	1			T1	8		T2	3		T3	3
all_pins[8]	values[0x1]	125	1			T42	3		T52	2		T81	3
all_pins[8]	transitions[0x0=>0x1]	99	1			T42	3		T52	2		T81	3
all_pins[8]	transitions[0x1=>0x0]	844706	1			T2	1		T3	1		T4	3
all_pins[9]	values[0x0]	171601	1			T1	8		T2	2		T3	2
all_pins[9]	values[0x1]	844732	1			T2	1		T3	1		T4	3
all_pins[9]	transitions[0x0=>0x1]	844702	1			T2	1		T3	1		T4	3
all_pins[9]	transitions[0x1=>0x0]	98	1			T52	2		T81	2		T235	3
all_pins[10]	values[0x0]	1016205	1			T1	8		T2	3		T3	3
all_pins[10]	values[0x1]	128	1			T52	2		T81	2		T235	3
all_pins[10]	transitions[0x0=>0x1]	83	1			T52	2		T81	2		T235	1
all_pins[10]	transitions[0x1=>0x0]	1009373	1			T2	2		T3	2		T4	1378
all_pins[11]	values[0x0]	6915	1			T1	8		T2	1		T3	1
all_pins[11]	values[0x1]	1009418	1			T2	2		T3	2		T4	1378
all_pins[11]	transitions[0x0=>0x1]	1009370	1			T2	2		T3	2		T4	1378
all_pins[11]	transitions[0x1=>0x0]	83	1			T42	1		T52	1		T235	1
all_pins[12]	values[0x0]	1016202	1			T1	8		T2	3		T3	3
all_pins[12]	values[0x1]	131	1			T42	2		T261	1		T262	1
all_pins[12]	transitions[0x0=>0x1]	112	1			T42	1		T261	1		T262	1
all_pins[12]	transitions[0x1=>0x0]	99	1			T52	4		T81	1		T237	1
all_pins[13]	values[0x0]	1016215	1			T1	8		T2	3		T3	3
all_pins[13]	values[0x1]	118	1			T42	1		T52	5		T81	1
all_pins[13]	transitions[0x0=>0x1]	91	1			T42	1		T52	5		T237	1
all_pins[13]	transitions[0x1=>0x0]	98	1			T42	2		T52	1		T81	5
all_pins[14]	values[0x0]	1016208	1			T1	8		T2	3		T3	3
all_pins[14]	values[0x1]	125	1			T42	2		T52	1		T81	6
all_pins[14]	transitions[0x0=>0x1]	80	1			T42	2		T52	1		T81	1
all_pins[14]	transitions[0x1=>0x0]	903444	1			T2	1		T3	1		T4	1295