Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	546	1			T42	4		T52	8		T81	7
all_values[1]	546	1			T42	4		T52	8		T81	7
all_values[2]	546	1			T42	4		T52	8		T81	7
all_values[3]	546	1			T42	4		T52	8		T81	7
all_values[4]	546	1			T42	4		T52	8		T81	7
all_values[5]	546	1			T42	4		T52	8		T81	7
all_values[6]	546	1			T42	4		T52	8		T81	7
all_values[7]	546	1			T42	4		T52	8		T81	7
all_values[8]	546	1			T42	4		T52	8		T81	7
all_values[9]	546	1			T42	4		T52	8		T81	7
all_values[10]	546	1			T42	4		T52	8		T81	7
all_values[11]	546	1			T42	4		T52	8		T81	7
all_values[12]	546	1			T42	4		T52	8		T81	7
all_values[13]	546	1			T42	4		T52	8		T81	7
all_values[14]	546	1			T42	4		T52	8		T81	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4291

1

T42

28

T52

53

T81

34

auto[1]

3899

1

T42

32

T52

67

T81

71

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1196

1

T42

17

T52

8

T81

17

auto[1]

6994

1

T42

43

T52

112

T81

88

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4763

1

T42

35

T52

70

T81

64

auto[1]

3427

1

T42

25

T52

50

T81

41

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	53	1			T42	4		T52	1		T236	2
all_values[0]	auto[0]	auto[0]	auto[1]	125	1			T237	1		T235	2		T236	2
all_values[0]	auto[0]	auto[1]	auto[0]	27	1			T237	1		T108	1		T287	1
all_values[0]	auto[0]	auto[1]	auto[1]	114	1			T52	4		T81	3		T237	1
all_values[0]	auto[1]	auto[0]	auto[1]	122	1			T52	1		T81	1		T235	3
all_values[0]	auto[1]	auto[1]	auto[1]	105	1			T52	2		T81	3		T237	1
all_values[1]	auto[0]	auto[0]	auto[0]	50	1			T42	1		T52	1		T236	1
all_values[1]	auto[0]	auto[0]	auto[1]	115	1			T52	3		T81	2		T235	1
all_values[1]	auto[0]	auto[1]	auto[0]	38	1			T237	1		T288	2		T276	4
all_values[1]	auto[0]	auto[1]	auto[1]	119	1			T42	2		T52	1		T81	2
all_values[1]	auto[1]	auto[0]	auto[1]	118	1			T42	1		T52	1		T237	1
all_values[1]	auto[1]	auto[1]	auto[1]	106	1			T52	2		T81	3		T237	1
all_values[2]	auto[0]	auto[0]	auto[0]	52	1			T42	2		T52	1		T236	1
all_values[2]	auto[0]	auto[0]	auto[1]	112	1			T52	2		T81	4		T237	2
all_values[2]	auto[0]	auto[1]	auto[0]	24	1			T42	2		T81	1		T289	1
all_values[2]	auto[0]	auto[1]	auto[1]	126	1			T52	1		T81	1		T235	4
all_values[2]	auto[1]	auto[0]	auto[1]	113	1			T52	2		T81	1		T235	6
all_values[2]	auto[1]	auto[1]	auto[1]	119	1			T52	2		T237	2		T235	2
all_values[3]	auto[0]	auto[0]	auto[0]	40	1			T42	1		T81	1		T235	4
all_values[3]	auto[0]	auto[0]	auto[1]	129	1			T42	1		T52	3		T237	1
all_values[3]	auto[0]	auto[1]	auto[0]	32	1			T81	2		T289	1		T275	1
all_values[3]	auto[0]	auto[1]	auto[1]	125	1			T52	2		T81	3		T235	1
all_values[3]	auto[1]	auto[0]	auto[1]	125	1			T42	2		T52	2		T81	1
all_values[3]	auto[1]	auto[1]	auto[1]	95	1			T52	1		T237	1		T235	3
all_values[4]	auto[0]	auto[0]	auto[0]	33	1			T288	1		T116	1		T290	1
all_values[4]	auto[0]	auto[0]	auto[1]	122	1			T42	1		T52	1		T81	1
all_values[4]	auto[0]	auto[1]	auto[0]	28	1			T42	1		T288	3		T116	1
all_values[4]	auto[0]	auto[1]	auto[1]	130	1			T52	5		T81	2		T237	2
all_values[4]	auto[1]	auto[0]	auto[1]	121	1			T42	1		T52	2		T237	1
all_values[4]	auto[1]	auto[1]	auto[1]	112	1			T42	1		T81	4		T237	1
all_values[5]	auto[0]	auto[0]	auto[0]	60	1			T52	1		T81	1		T237	1
all_values[5]	auto[0]	auto[0]	auto[1]	113	1			T235	3		T286	5		T289	5
all_values[5]	auto[0]	auto[1]	auto[0]	40	1			T81	3		T237	1		T236	1
all_values[5]	auto[0]	auto[1]	auto[1]	126	1			T42	2		T52	4		T81	2
all_values[5]	auto[1]	auto[0]	auto[1]	105	1			T42	2		T52	2		T81	1
all_values[5]	auto[1]	auto[1]	auto[1]	102	1			T52	1		T237	1		T235	2
all_values[6]	auto[0]	auto[0]	auto[0]	35	1			T52	1		T286	1		T108	2
all_values[6]	auto[0]	auto[0]	auto[1]	127	1			T42	2		T52	1		T237	1
all_values[6]	auto[0]	auto[1]	auto[0]	41	1			T81	2		T237	2		T108	1
all_values[6]	auto[0]	auto[1]	auto[1]	102	1			T52	2		T81	1		T235	3
all_values[6]	auto[1]	auto[0]	auto[1]	137	1			T52	2		T81	3		T237	1
all_values[6]	auto[1]	auto[1]	auto[1]	104	1			T42	2		T52	2		T81	1
all_values[7]	auto[0]	auto[0]	auto[0]	39	1			T235	3		T275	1		T283	1
all_values[7]	auto[0]	auto[0]	auto[1]	115	1			T52	1		T235	1		T236	2
all_values[7]	auto[0]	auto[1]	auto[0]	45	1			T81	1		T237	1		T235	1
all_values[7]	auto[0]	auto[1]	auto[1]	123	1			T42	1		T52	2		T81	3
all_values[7]	auto[1]	auto[0]	auto[1]	122	1			T42	2		T52	2		T81	2
all_values[7]	auto[1]	auto[1]	auto[1]	102	1			T42	1		T52	3		T81	1
all_values[8]	auto[0]	auto[0]	auto[0]	50	1			T286	1		T275	1		T283	5
all_values[8]	auto[0]	auto[0]	auto[1]	115	1			T52	1		T81	2		T237	1
all_values[8]	auto[0]	auto[1]	auto[0]	34	1			T237	1		T235	1		T289	1
all_values[8]	auto[0]	auto[1]	auto[1]	115	1			T42	2		T52	3		T81	2
all_values[8]	auto[1]	auto[0]	auto[1]	118	1			T52	2		T81	1		T237	2
all_values[8]	auto[1]	auto[1]	auto[1]	114	1			T42	2		T52	2		T81	2
all_values[9]	auto[0]	auto[0]	auto[0]	56	1			T42	1		T52	1		T235	1
all_values[9]	auto[0]	auto[0]	auto[1]	113	1			T52	2		T237	1		T235	5
all_values[9]	auto[0]	auto[1]	auto[0]	29	1			T81	2		T237	1		T235	1
all_values[9]	auto[0]	auto[1]	auto[1]	125	1			T42	2		T52	2		T81	2
all_values[9]	auto[1]	auto[0]	auto[1]	128	1			T42	1		T52	2		T81	3
all_values[9]	auto[1]	auto[1]	auto[1]	95	1			T52	1		T237	1		T235	1
all_values[10]	auto[0]	auto[0]	auto[0]	37	1			T237	3		T235	1		T236	1
all_values[10]	auto[0]	auto[0]	auto[1]	101	1			T42	1		T52	1		T81	2
all_values[10]	auto[0]	auto[1]	auto[0]	44	1			T42	2		T81	1		T237	1
all_values[10]	auto[0]	auto[1]	auto[1]	125	1			T52	3		T81	1		T235	6
all_values[10]	auto[1]	auto[0]	auto[1]	128	1			T42	1		T52	1		T81	1
all_values[10]	auto[1]	auto[1]	auto[1]	111	1			T52	3		T81	2		T235	2
all_values[11]	auto[0]	auto[0]	auto[0]	48	1			T237	2		T236	1		T286	2
all_values[11]	auto[0]	auto[0]	auto[1]	117	1			T52	1		T81	2		T235	4
all_values[11]	auto[0]	auto[1]	auto[0]	33	1			T237	2		T286	2		T287	1
all_values[11]	auto[0]	auto[1]	auto[1]	116	1			T42	1		T52	4		T81	1
all_values[11]	auto[1]	auto[0]	auto[1]	117	1			T52	2		T81	1		T235	3
all_values[11]	auto[1]	auto[1]	auto[1]	115	1			T42	3		T52	1		T81	3
all_values[12]	auto[0]	auto[0]	auto[0]	49	1			T52	1		T283	2		T290	1
all_values[12]	auto[0]	auto[0]	auto[1]	120	1			T52	2		T81	1		T237	1
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T42	1		T81	1		T237	2
all_values[12]	auto[0]	auto[1]	auto[1]	123	1			T42	1		T52	3		T81	4
all_values[12]	auto[1]	auto[0]	auto[1]	119	1			T52	2		T81	1		T237	1
all_values[12]	auto[1]	auto[1]	auto[1]	106	1			T42	2		T235	3		T236	1
all_values[13]	auto[0]	auto[0]	auto[0]	40	1			T52	1		T236	1		T286	1
all_values[13]	auto[0]	auto[0]	auto[1]	136	1			T42	1		T52	1		T237	1
all_values[13]	auto[0]	auto[1]	auto[0]	18	1			T42	1		T81	2		T291	1
all_values[13]	auto[0]	auto[1]	auto[1]	120	1			T52	2		T81	2		T235	1
all_values[13]	auto[1]	auto[0]	auto[1]	123	1			T42	1		T52	1		T81	2
all_values[13]	auto[1]	auto[1]	auto[1]	109	1			T42	1		T52	3		T81	1
all_values[14]	auto[0]	auto[0]	auto[0]	54	1			T42	1		T237	2		T235	1
all_values[14]	auto[0]	auto[0]	auto[1]	109	1			T52	1		T235	2		T236	1
all_values[14]	auto[0]	auto[1]	auto[0]	38	1			T237	2		T117	1		T287	1
all_values[14]	auto[0]	auto[1]	auto[1]	109	1			T42	1		T52	4		T81	4
all_values[14]	auto[1]	auto[0]	auto[1]	130	1			T42	1		T52	1		T235	1
all_values[14]	auto[1]	auto[1]	auto[1]	106	1			T42	1		T52	2		T81	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal