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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.85 96.60 90.03 97.22 69.64 93.62 98.44 90.42


Total test records in report: 1639
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T98 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3039089261 Jul 07 05:12:23 PM PDT 24 Jul 07 05:12:26 PM PDT 24 161608440 ps
T1537 /workspace/coverage/cover_reg_top/34.i2c_intr_test.4184780240 Jul 07 05:12:35 PM PDT 24 Jul 07 05:12:37 PM PDT 24 20348211 ps
T99 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.4061927714 Jul 07 05:12:08 PM PDT 24 Jul 07 05:12:14 PM PDT 24 2984071796 ps
T1538 /workspace/coverage/cover_reg_top/10.i2c_intr_test.3158727712 Jul 07 05:12:15 PM PDT 24 Jul 07 05:12:17 PM PDT 24 41006294 ps
T232 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3457006601 Jul 07 05:12:22 PM PDT 24 Jul 07 05:12:24 PM PDT 24 26294272 ps
T233 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.905671389 Jul 07 05:12:06 PM PDT 24 Jul 07 05:12:08 PM PDT 24 19289855 ps
T234 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.284870918 Jul 07 05:12:11 PM PDT 24 Jul 07 05:12:13 PM PDT 24 185477262 ps
T1539 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1525619489 Jul 07 05:12:12 PM PDT 24 Jul 07 05:12:16 PM PDT 24 214862619 ps
T1540 /workspace/coverage/cover_reg_top/47.i2c_intr_test.2525409577 Jul 07 05:12:32 PM PDT 24 Jul 07 05:12:33 PM PDT 24 17732791 ps
T100 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2859808163 Jul 07 05:12:19 PM PDT 24 Jul 07 05:12:21 PM PDT 24 38365816 ps
T101 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3683586807 Jul 07 05:12:14 PM PDT 24 Jul 07 05:12:16 PM PDT 24 37560326 ps
T216 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1432920711 Jul 07 05:12:11 PM PDT 24 Jul 07 05:12:12 PM PDT 24 15694717 ps
T1541 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3484427919 Jul 07 05:12:18 PM PDT 24 Jul 07 05:12:20 PM PDT 24 58802797 ps
T115 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4286829795 Jul 07 05:12:25 PM PDT 24 Jul 07 05:12:27 PM PDT 24 19576845 ps
T1542 /workspace/coverage/cover_reg_top/37.i2c_intr_test.2916319274 Jul 07 05:12:33 PM PDT 24 Jul 07 05:12:34 PM PDT 24 27507055 ps
T1543 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3480122036 Jul 07 05:12:22 PM PDT 24 Jul 07 05:12:24 PM PDT 24 34270693 ps
T148 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3127327498 Jul 07 05:12:08 PM PDT 24 Jul 07 05:12:11 PM PDT 24 396068744 ps
T1544 /workspace/coverage/cover_reg_top/23.i2c_intr_test.1703155247 Jul 07 05:12:31 PM PDT 24 Jul 07 05:12:32 PM PDT 24 22768803 ps
T149 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2092767862 Jul 07 05:12:18 PM PDT 24 Jul 07 05:12:20 PM PDT 24 398255921 ps
T1545 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2969385817 Jul 07 05:12:23 PM PDT 24 Jul 07 05:12:24 PM PDT 24 100725703 ps
T217 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3683791904 Jul 07 05:12:12 PM PDT 24 Jul 07 05:12:14 PM PDT 24 17987416 ps
T206 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3681968807 Jul 07 05:12:28 PM PDT 24 Jul 07 05:12:30 PM PDT 24 70232081 ps
T1546 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2007473703 Jul 07 05:12:15 PM PDT 24 Jul 07 05:12:17 PM PDT 24 77166514 ps
T210 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3493190705 Jul 07 05:12:14 PM PDT 24 Jul 07 05:12:18 PM PDT 24 376609802 ps
T1547 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2527238315 Jul 07 05:12:24 PM PDT 24 Jul 07 05:12:27 PM PDT 24 123023713 ps
T1548 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3711981284 Jul 07 05:12:09 PM PDT 24 Jul 07 05:12:11 PM PDT 24 35650539 ps
T1549 /workspace/coverage/cover_reg_top/7.i2c_intr_test.2244932887 Jul 07 05:12:14 PM PDT 24 Jul 07 05:12:16 PM PDT 24 24378452 ps
T1550 /workspace/coverage/cover_reg_top/24.i2c_intr_test.2580915967 Jul 07 05:12:29 PM PDT 24 Jul 07 05:12:30 PM PDT 24 18332604 ps
T1551 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2430949966 Jul 07 05:12:23 PM PDT 24 Jul 07 05:12:26 PM PDT 24 199399509 ps
T1552 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.519132573 Jul 07 05:12:14 PM PDT 24 Jul 07 05:12:16 PM PDT 24 96083281 ps
T218 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1724082964 Jul 07 05:12:18 PM PDT 24 Jul 07 05:12:19 PM PDT 24 49184089 ps
T1553 /workspace/coverage/cover_reg_top/19.i2c_intr_test.3555070102 Jul 07 05:12:23 PM PDT 24 Jul 07 05:12:24 PM PDT 24 17012338 ps
T1554 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3244846684 Jul 07 05:12:36 PM PDT 24 Jul 07 05:12:37 PM PDT 24 50977338 ps
T1555 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1511187909 Jul 07 05:12:16 PM PDT 24 Jul 07 05:12:18 PM PDT 24 26352343 ps
T1556 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1680033723 Jul 07 05:12:22 PM PDT 24 Jul 07 05:12:24 PM PDT 24 247016094 ps
T1557 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.361194482 Jul 07 05:12:21 PM PDT 24 Jul 07 05:12:23 PM PDT 24 41829695 ps
T219 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1890269030 Jul 07 05:12:19 PM PDT 24 Jul 07 05:12:21 PM PDT 24 42054056 ps
T1558 /workspace/coverage/cover_reg_top/44.i2c_intr_test.2055606694 Jul 07 05:12:32 PM PDT 24 Jul 07 05:12:33 PM PDT 24 17025074 ps
T1559 /workspace/coverage/cover_reg_top/49.i2c_intr_test.4021145594 Jul 07 05:12:32 PM PDT 24 Jul 07 05:12:33 PM PDT 24 18440706 ps
T220 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2054236271 Jul 07 05:12:13 PM PDT 24 Jul 07 05:12:15 PM PDT 24 30722940 ps
T1560 /workspace/coverage/cover_reg_top/20.i2c_intr_test.4279701863 Jul 07 05:12:23 PM PDT 24 Jul 07 05:12:24 PM PDT 24 34279997 ps
T221 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.62163619 Jul 07 05:12:25 PM PDT 24 Jul 07 05:12:26 PM PDT 24 15298677 ps
T1561 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.322026316 Jul 07 05:12:25 PM PDT 24 Jul 07 05:12:28 PM PDT 24 293757866 ps
T1562 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.894070069 Jul 07 05:12:06 PM PDT 24 Jul 07 05:12:10 PM PDT 24 67619641 ps
T1563 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2162558070 Jul 07 05:12:19 PM PDT 24 Jul 07 05:12:21 PM PDT 24 163353881 ps
T1564 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1868454422 Jul 07 05:12:27 PM PDT 24 Jul 07 05:12:29 PM PDT 24 30562436 ps
T204 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.4158099199 Jul 07 05:12:19 PM PDT 24 Jul 07 05:12:23 PM PDT 24 909155788 ps
T1565 /workspace/coverage/cover_reg_top/29.i2c_intr_test.2133171732 Jul 07 05:12:27 PM PDT 24 Jul 07 05:12:28 PM PDT 24 18129045 ps
T1566 /workspace/coverage/cover_reg_top/18.i2c_intr_test.3899094591 Jul 07 05:12:25 PM PDT 24 Jul 07 05:12:27 PM PDT 24 15841117 ps
T1567 /workspace/coverage/cover_reg_top/40.i2c_intr_test.2894729626 Jul 07 05:12:36 PM PDT 24 Jul 07 05:12:38 PM PDT 24 37637965 ps
T222 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3625332002 Jul 07 05:12:13 PM PDT 24 Jul 07 05:12:14 PM PDT 24 40977137 ps
T1568 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2400053766 Jul 07 05:12:16 PM PDT 24 Jul 07 05:12:18 PM PDT 24 34303655 ps
T1569 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3650077416 Jul 07 05:12:09 PM PDT 24 Jul 07 05:12:11 PM PDT 24 148122278 ps
T1570 /workspace/coverage/cover_reg_top/48.i2c_intr_test.257275432 Jul 07 05:12:37 PM PDT 24 Jul 07 05:12:38 PM PDT 24 24242032 ps
T1571 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3235269248 Jul 07 05:12:13 PM PDT 24 Jul 07 05:12:14 PM PDT 24 43777010 ps
T1572 /workspace/coverage/cover_reg_top/43.i2c_intr_test.2179448009 Jul 07 05:12:34 PM PDT 24 Jul 07 05:12:35 PM PDT 24 32478766 ps
T202 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3055387588 Jul 07 05:12:21 PM PDT 24 Jul 07 05:12:24 PM PDT 24 134939557 ps
T1573 /workspace/coverage/cover_reg_top/22.i2c_intr_test.4046277083 Jul 07 05:12:29 PM PDT 24 Jul 07 05:12:30 PM PDT 24 17404352 ps
T1574 /workspace/coverage/cover_reg_top/9.i2c_intr_test.3680779566 Jul 07 05:12:16 PM PDT 24 Jul 07 05:12:17 PM PDT 24 30656948 ps
T1575 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1203841157 Jul 07 05:12:17 PM PDT 24 Jul 07 05:12:19 PM PDT 24 141280492 ps
T1576 /workspace/coverage/cover_reg_top/2.i2c_intr_test.2866672458 Jul 07 05:12:15 PM PDT 24 Jul 07 05:12:16 PM PDT 24 18675053 ps
T1577 /workspace/coverage/cover_reg_top/35.i2c_intr_test.1066889810 Jul 07 05:12:32 PM PDT 24 Jul 07 05:12:33 PM PDT 24 80107560 ps
T1578 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1775818345 Jul 07 05:12:36 PM PDT 24 Jul 07 05:12:37 PM PDT 24 31620122 ps
T208 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2732485721 Jul 07 05:12:16 PM PDT 24 Jul 07 05:12:19 PM PDT 24 1915163334 ps
T1579 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2122717447 Jul 07 05:12:13 PM PDT 24 Jul 07 05:12:15 PM PDT 24 132884491 ps
T1580 /workspace/coverage/cover_reg_top/17.i2c_intr_test.3935510658 Jul 07 05:12:25 PM PDT 24 Jul 07 05:12:27 PM PDT 24 20373634 ps
T1581 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3888298065 Jul 07 05:12:08 PM PDT 24 Jul 07 05:12:10 PM PDT 24 49865379 ps
T1582 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3580759232 Jul 07 05:12:12 PM PDT 24 Jul 07 05:12:14 PM PDT 24 103748313 ps
T266 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.579282367 Jul 07 05:12:19 PM PDT 24 Jul 07 05:12:22 PM PDT 24 82446039 ps
T1583 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3041860992 Jul 07 05:12:13 PM PDT 24 Jul 07 05:12:15 PM PDT 24 56459879 ps
T1584 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.274584567 Jul 07 05:12:12 PM PDT 24 Jul 07 05:12:13 PM PDT 24 57833770 ps
T1585 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2027691334 Jul 07 05:12:34 PM PDT 24 Jul 07 05:12:36 PM PDT 24 27325588 ps
T1586 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.292332693 Jul 07 05:12:07 PM PDT 24 Jul 07 05:12:10 PM PDT 24 287912941 ps
T1587 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2439682767 Jul 07 05:12:20 PM PDT 24 Jul 07 05:12:22 PM PDT 24 19563569 ps
T1588 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3910783568 Jul 07 05:12:08 PM PDT 24 Jul 07 05:12:10 PM PDT 24 150300508 ps
T223 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2790997498 Jul 07 05:12:25 PM PDT 24 Jul 07 05:12:27 PM PDT 24 22009040 ps
T224 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.404592665 Jul 07 05:12:16 PM PDT 24 Jul 07 05:12:18 PM PDT 24 238324975 ps
T1589 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.405375652 Jul 07 05:12:11 PM PDT 24 Jul 07 05:12:14 PM PDT 24 758898936 ps
T1590 /workspace/coverage/cover_reg_top/26.i2c_intr_test.2817502925 Jul 07 05:12:28 PM PDT 24 Jul 07 05:12:29 PM PDT 24 45434415 ps
T1591 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.609266064 Jul 07 05:12:07 PM PDT 24 Jul 07 05:12:09 PM PDT 24 54200740 ps
T225 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.4139192636 Jul 07 05:12:09 PM PDT 24 Jul 07 05:12:11 PM PDT 24 84079946 ps
T226 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1908963290 Jul 07 05:12:12 PM PDT 24 Jul 07 05:12:14 PM PDT 24 93964536 ps
T1592 /workspace/coverage/cover_reg_top/33.i2c_intr_test.662448181 Jul 07 05:12:29 PM PDT 24 Jul 07 05:12:30 PM PDT 24 27401190 ps
T227 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.818122184 Jul 07 05:12:19 PM PDT 24 Jul 07 05:12:20 PM PDT 24 15776561 ps
T1593 /workspace/coverage/cover_reg_top/14.i2c_intr_test.2109600994 Jul 07 05:12:21 PM PDT 24 Jul 07 05:12:23 PM PDT 24 18306318 ps
T1594 /workspace/coverage/cover_reg_top/13.i2c_intr_test.2902155328 Jul 07 05:12:21 PM PDT 24 Jul 07 05:12:23 PM PDT 24 18018293 ps
T1595 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1888186818 Jul 07 05:12:13 PM PDT 24 Jul 07 05:12:14 PM PDT 24 43137858 ps
T1596 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.4178575713 Jul 07 05:12:11 PM PDT 24 Jul 07 05:12:14 PM PDT 24 175986840 ps
T1597 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.4250603880 Jul 07 05:12:05 PM PDT 24 Jul 07 05:12:09 PM PDT 24 75417467 ps
T203 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.4248856996 Jul 07 05:12:22 PM PDT 24 Jul 07 05:12:25 PM PDT 24 95856623 ps
T200 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3924589975 Jul 07 05:12:20 PM PDT 24 Jul 07 05:12:24 PM PDT 24 589190443 ps
T1598 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1738317463 Jul 07 05:12:16 PM PDT 24 Jul 07 05:12:19 PM PDT 24 2204502504 ps
T1599 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2213435043 Jul 07 05:12:23 PM PDT 24 Jul 07 05:12:26 PM PDT 24 141715511 ps
T1600 /workspace/coverage/cover_reg_top/11.i2c_intr_test.70304517 Jul 07 05:12:17 PM PDT 24 Jul 07 05:12:19 PM PDT 24 18730006 ps
T1601 /workspace/coverage/cover_reg_top/16.i2c_intr_test.2701345421 Jul 07 05:12:24 PM PDT 24 Jul 07 05:12:25 PM PDT 24 17212654 ps
T1602 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3729008926 Jul 07 05:12:22 PM PDT 24 Jul 07 05:12:23 PM PDT 24 112262867 ps
T1603 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1881494357 Jul 07 05:12:12 PM PDT 24 Jul 07 05:12:13 PM PDT 24 62571395 ps
T1604 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3739002613 Jul 07 05:12:16 PM PDT 24 Jul 07 05:12:17 PM PDT 24 55110231 ps
T1605 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.945159836 Jul 07 05:12:12 PM PDT 24 Jul 07 05:12:14 PM PDT 24 17936200 ps
T1606 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1121420620 Jul 07 05:12:26 PM PDT 24 Jul 07 05:12:28 PM PDT 24 24267396 ps
T1607 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4060776243 Jul 07 05:12:19 PM PDT 24 Jul 07 05:12:22 PM PDT 24 119539057 ps
T1608 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4136340580 Jul 07 05:12:20 PM PDT 24 Jul 07 05:12:22 PM PDT 24 153975838 ps
T1609 /workspace/coverage/cover_reg_top/32.i2c_intr_test.1649785474 Jul 07 05:12:29 PM PDT 24 Jul 07 05:12:30 PM PDT 24 50971169 ps
T1610 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1276313415 Jul 07 05:12:20 PM PDT 24 Jul 07 05:12:23 PM PDT 24 26022434 ps
T1611 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.182974550 Jul 07 05:12:09 PM PDT 24 Jul 07 05:12:12 PM PDT 24 41539807 ps
T1612 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.718705229 Jul 07 05:12:14 PM PDT 24 Jul 07 05:12:18 PM PDT 24 65972728 ps
T1613 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1933232535 Jul 07 05:12:11 PM PDT 24 Jul 07 05:12:12 PM PDT 24 149353437 ps
T1614 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3785126550 Jul 07 05:12:13 PM PDT 24 Jul 07 05:12:16 PM PDT 24 138851142 ps
T1615 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.92276823 Jul 07 05:12:07 PM PDT 24 Jul 07 05:12:08 PM PDT 24 64978178 ps
T1616 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4091843738 Jul 07 05:12:13 PM PDT 24 Jul 07 05:12:15 PM PDT 24 42478114 ps
T1617 /workspace/coverage/cover_reg_top/27.i2c_intr_test.323698385 Jul 07 05:12:29 PM PDT 24 Jul 07 05:12:30 PM PDT 24 14553634 ps
T228 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1746798305 Jul 07 05:12:09 PM PDT 24 Jul 07 05:12:11 PM PDT 24 31166992 ps
T1618 /workspace/coverage/cover_reg_top/21.i2c_intr_test.1104921870 Jul 07 05:12:28 PM PDT 24 Jul 07 05:12:29 PM PDT 24 29172569 ps
T1619 /workspace/coverage/cover_reg_top/5.i2c_intr_test.3374388976 Jul 07 05:12:13 PM PDT 24 Jul 07 05:12:15 PM PDT 24 41386894 ps
T1620 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.859870494 Jul 07 05:12:21 PM PDT 24 Jul 07 05:12:23 PM PDT 24 42384315 ps
T1621 /workspace/coverage/cover_reg_top/0.i2c_intr_test.942506642 Jul 07 05:12:08 PM PDT 24 Jul 07 05:12:09 PM PDT 24 89917128 ps
T1622 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1004175474 Jul 07 05:12:20 PM PDT 24 Jul 07 05:12:22 PM PDT 24 124968958 ps
T1623 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.445550873 Jul 07 05:12:14 PM PDT 24 Jul 07 05:12:20 PM PDT 24 1400347420 ps
T1624 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1456395442 Jul 07 05:12:19 PM PDT 24 Jul 07 05:12:22 PM PDT 24 241549571 ps
T1625 /workspace/coverage/cover_reg_top/12.i2c_intr_test.2334819872 Jul 07 05:12:20 PM PDT 24 Jul 07 05:12:22 PM PDT 24 27608783 ps
T1626 /workspace/coverage/cover_reg_top/42.i2c_intr_test.3902968794 Jul 07 05:12:34 PM PDT 24 Jul 07 05:12:36 PM PDT 24 60320137 ps
T1627 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3226889512 Jul 07 05:12:17 PM PDT 24 Jul 07 05:12:18 PM PDT 24 524895290 ps
T1628 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.650810227 Jul 07 05:12:25 PM PDT 24 Jul 07 05:12:27 PM PDT 24 23574383 ps
T205 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.83514669 Jul 07 05:12:20 PM PDT 24 Jul 07 05:12:22 PM PDT 24 89238566 ps
T1629 /workspace/coverage/cover_reg_top/38.i2c_intr_test.2886056797 Jul 07 05:12:32 PM PDT 24 Jul 07 05:12:33 PM PDT 24 18623660 ps
T1630 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3291434655 Jul 07 05:12:20 PM PDT 24 Jul 07 05:12:23 PM PDT 24 30986037 ps
T1631 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1568812908 Jul 07 05:12:19 PM PDT 24 Jul 07 05:12:21 PM PDT 24 75509930 ps
T264 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3987967977 Jul 07 05:12:12 PM PDT 24 Jul 07 05:12:14 PM PDT 24 103887361 ps
T1632 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2989745279 Jul 07 05:12:17 PM PDT 24 Jul 07 05:12:19 PM PDT 24 52202528 ps
T209 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3106377070 Jul 07 05:12:15 PM PDT 24 Jul 07 05:12:17 PM PDT 24 134714952 ps
T1633 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2337678753 Jul 07 05:12:05 PM PDT 24 Jul 07 05:12:07 PM PDT 24 289355141 ps
T1634 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.4218573642 Jul 07 05:12:24 PM PDT 24 Jul 07 05:12:26 PM PDT 24 179177891 ps
T1635 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.627437204 Jul 07 05:12:14 PM PDT 24 Jul 07 05:12:16 PM PDT 24 60089982 ps
T1636 /workspace/coverage/cover_reg_top/46.i2c_intr_test.300554056 Jul 07 05:12:33 PM PDT 24 Jul 07 05:12:34 PM PDT 24 58198045 ps
T1637 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2640027478 Jul 07 05:12:27 PM PDT 24 Jul 07 05:12:28 PM PDT 24 27246774 ps
T201 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3045761126 Jul 07 05:12:25 PM PDT 24 Jul 07 05:12:27 PM PDT 24 228120391 ps
T1638 /workspace/coverage/cover_reg_top/3.i2c_intr_test.539611993 Jul 07 05:12:14 PM PDT 24 Jul 07 05:12:16 PM PDT 24 36800822 ps
T265 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.4004992983 Jul 07 05:12:10 PM PDT 24 Jul 07 05:12:12 PM PDT 24 48348972 ps
T1639 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.637658000 Jul 07 05:12:19 PM PDT 24 Jul 07 05:12:21 PM PDT 24 47013644 ps

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.2551411426
Short name T2
Test name
Test status
Simulation time 12203111540 ps
CPU time 68.84 seconds
Started Jul 07 05:37:27 PM PDT 24
Finished Jul 07 05:38:36 PM PDT 24
Peak memory 763720 kb
Host smart-40191e54-3bc8-429f-95c6-6f300951af49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551411426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2551411426
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2466812068
Short name T11
Test name
Test status
Simulation time 466357527 ps
CPU time 1.59 seconds
Started Jul 07 05:35:06 PM PDT 24
Finished Jul 07 05:35:07 PM PDT 24
Peak memory 205336 kb
Host smart-5a1baa41-62dd-49b8-86f1-8019880d8dc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466812068 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2466812068
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.4208422614
Short name T52
Test name
Test status
Simulation time 45833877206 ps
CPU time 762.91 seconds
Started Jul 07 05:34:26 PM PDT 24
Finished Jul 07 05:47:10 PM PDT 24
Peak memory 1910416 kb
Host smart-72bd7208-d166-4392-a1ac-a93658102cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208422614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.4208422614
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.77752813
Short name T14
Test name
Test status
Simulation time 4566827822 ps
CPU time 10.73 seconds
Started Jul 07 05:32:58 PM PDT 24
Finished Jul 07 05:33:09 PM PDT 24
Peak memory 213708 kb
Host smart-94183d3d-96fa-4f3a-beed-fd2846c1ebe3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77752813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.77752813
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3782814570
Short name T94
Test name
Test status
Simulation time 112533105 ps
CPU time 0.94 seconds
Started Jul 07 05:12:07 PM PDT 24
Finished Jul 07 05:12:08 PM PDT 24
Peak memory 204372 kb
Host smart-ae27189f-04a6-4af8-aea4-660384088e12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782814570 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3782814570
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.3671687891
Short name T18
Test name
Test status
Simulation time 29295491481 ps
CPU time 26 seconds
Started Jul 07 05:33:21 PM PDT 24
Finished Jul 07 05:33:47 PM PDT 24
Peak memory 600128 kb
Host smart-c95fc79d-a4c7-45ff-a872-3665f737d5be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671687891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.3671687891
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.3531645129
Short name T33
Test name
Test status
Simulation time 294553900 ps
CPU time 3.9 seconds
Started Jul 07 05:35:13 PM PDT 24
Finished Jul 07 05:35:18 PM PDT 24
Peak memory 205084 kb
Host smart-6cae6bd1-65ee-4043-b0e3-6c8b7107c760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531645129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.3531645129
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_override.3014767482
Short name T131
Test name
Test status
Simulation time 21348095 ps
CPU time 0.69 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:33:03 PM PDT 24
Peak memory 204712 kb
Host smart-410eacd6-1bf0-4b73-ac8c-d57ea3417f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014767482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3014767482
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.2662878835
Short name T16
Test name
Test status
Simulation time 492036584 ps
CPU time 6.64 seconds
Started Jul 07 05:36:16 PM PDT 24
Finished Jul 07 05:36:23 PM PDT 24
Peak memory 205000 kb
Host smart-4b99520e-4f3f-4433-a799-3c6f14f70d26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662878835 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.2662878835
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.3596251196
Short name T42
Test name
Test status
Simulation time 39395754347 ps
CPU time 1004.17 seconds
Started Jul 07 05:35:25 PM PDT 24
Finished Jul 07 05:52:10 PM PDT 24
Peak memory 3192688 kb
Host smart-f04316ad-b732-4cf3-9a05-c8f17c34cbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596251196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.3596251196
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3039089261
Short name T98
Test name
Test status
Simulation time 161608440 ps
CPU time 2.41 seconds
Started Jul 07 05:12:23 PM PDT 24
Finished Jul 07 05:12:26 PM PDT 24
Peak memory 204556 kb
Host smart-56f56db3-cd18-4c69-a665-ac66df5ac002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039089261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3039089261
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/26.i2c_alert_test.1478416371
Short name T5
Test name
Test status
Simulation time 16530036 ps
CPU time 0.65 seconds
Started Jul 07 05:35:18 PM PDT 24
Finished Jul 07 05:35:19 PM PDT 24
Peak memory 204568 kb
Host smart-c9a6dfa2-8729-44e1-b7a9-4bdd14ee79ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478416371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.1478416371
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.1167609956
Short name T55
Test name
Test status
Simulation time 63932125045 ps
CPU time 923.63 seconds
Started Jul 07 05:37:00 PM PDT 24
Finished Jul 07 05:52:24 PM PDT 24
Peak memory 2725432 kb
Host smart-9f672de7-6c7e-476f-b133-572d7a07aeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167609956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.1167609956
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.2348468609
Short name T30
Test name
Test status
Simulation time 1648190436 ps
CPU time 7.71 seconds
Started Jul 07 05:33:02 PM PDT 24
Finished Jul 07 05:33:10 PM PDT 24
Peak memory 213216 kb
Host smart-b72a12d6-2448-42c9-96dd-543c764408e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348468609 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.2348468609
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.2225050925
Short name T51
Test name
Test status
Simulation time 33717905592 ps
CPU time 411.04 seconds
Started Jul 07 05:37:37 PM PDT 24
Finished Jul 07 05:44:29 PM PDT 24
Peak memory 504452 kb
Host smart-1fbc6957-46b7-4e6d-8fb4-59e0954604b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225050925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2225050925
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.4061927714
Short name T99
Test name
Test status
Simulation time 2984071796 ps
CPU time 4.99 seconds
Started Jul 07 05:12:08 PM PDT 24
Finished Jul 07 05:12:14 PM PDT 24
Peak memory 204456 kb
Host smart-7c980b04-0084-4e92-a674-25484ba495b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061927714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.4061927714
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.1769182295
Short name T81
Test name
Test status
Simulation time 32814603386 ps
CPU time 784.73 seconds
Started Jul 07 05:35:41 PM PDT 24
Finished Jul 07 05:48:47 PM PDT 24
Peak memory 3401904 kb
Host smart-8ca0cbc2-9248-4752-bd86-36bc453d437c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769182295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.1769182295
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.2625465438
Short name T24
Test name
Test status
Simulation time 1200112133 ps
CPU time 5.59 seconds
Started Jul 07 05:33:49 PM PDT 24
Finished Jul 07 05:33:55 PM PDT 24
Peak memory 205060 kb
Host smart-028f0925-3b5e-464d-9f5c-20e2acb81719
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625465438 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.2625465438
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1370847332
Short name T183
Test name
Test status
Simulation time 37081647 ps
CPU time 0.89 seconds
Started Jul 07 05:32:56 PM PDT 24
Finished Jul 07 05:32:57 PM PDT 24
Peak memory 222160 kb
Host smart-a055a86c-a97e-4445-8707-b902039a9ec6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370847332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1370847332
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3382737093
Short name T59
Test name
Test status
Simulation time 103818387 ps
CPU time 0.94 seconds
Started Jul 07 05:36:12 PM PDT 24
Finished Jul 07 05:36:14 PM PDT 24
Peak memory 204752 kb
Host smart-6be11450-ad50-4cd2-aed2-72d6cb2e734c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382737093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3382737093
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.355772088
Short name T174
Test name
Test status
Simulation time 3950335746 ps
CPU time 36.18 seconds
Started Jul 07 05:33:18 PM PDT 24
Finished Jul 07 05:33:54 PM PDT 24
Peak memory 205092 kb
Host smart-caee6723-3e8f-49c3-aac2-73dbef2b2bd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355772088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_targ
et_smoke.355772088
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2527238315
Short name T1547
Test name
Test status
Simulation time 123023713 ps
CPU time 2.24 seconds
Started Jul 07 05:12:24 PM PDT 24
Finished Jul 07 05:12:27 PM PDT 24
Peak memory 204564 kb
Host smart-99be6aa8-e2c3-49bd-9134-a6d23e8562a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527238315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2527238315
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.4212352781
Short name T283
Test name
Test status
Simulation time 39585145758 ps
CPU time 1426.4 seconds
Started Jul 07 05:34:00 PM PDT 24
Finished Jul 07 05:57:47 PM PDT 24
Peak memory 2258392 kb
Host smart-293223f2-7d3b-4525-9c98-971fe746247f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212352781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.4212352781
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.3243497907
Short name T74
Test name
Test status
Simulation time 203003953 ps
CPU time 4.65 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:35:56 PM PDT 24
Peak memory 238096 kb
Host smart-d946f289-212e-4dd6-ab59-a4610e0ceabc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243497907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.3243497907
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.2932639946
Short name T248
Test name
Test status
Simulation time 2362834626 ps
CPU time 43.04 seconds
Started Jul 07 05:33:18 PM PDT 24
Finished Jul 07 05:34:01 PM PDT 24
Peak memory 415512 kb
Host smart-39e9a6ea-cb62-473d-a4ed-4e17836525ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932639946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.2932639946
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.4135992814
Short name T511
Test name
Test status
Simulation time 689303334 ps
CPU time 8.63 seconds
Started Jul 07 05:32:56 PM PDT 24
Finished Jul 07 05:33:05 PM PDT 24
Peak memory 232988 kb
Host smart-fe0fb6d6-4ca5-4c87-a6ae-0574d16df4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135992814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.4135992814
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.3119069239
Short name T156
Test name
Test status
Simulation time 24746559546 ps
CPU time 15.93 seconds
Started Jul 07 05:35:48 PM PDT 24
Finished Jul 07 05:36:04 PM PDT 24
Peak memory 338512 kb
Host smart-a0d577e1-caf9-44ad-8110-38157a0addfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119069239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.3119069239
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.3386373087
Short name T457
Test name
Test status
Simulation time 2055662349 ps
CPU time 49.26 seconds
Started Jul 07 05:33:05 PM PDT 24
Finished Jul 07 05:33:54 PM PDT 24
Peak memory 204992 kb
Host smart-a6865dc2-0e90-476b-8e00-3fda929a04f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386373087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.3386373087
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2003630732
Short name T96
Test name
Test status
Simulation time 301822475 ps
CPU time 0.94 seconds
Started Jul 07 05:12:19 PM PDT 24
Finished Jul 07 05:12:21 PM PDT 24
Peak memory 204204 kb
Host smart-95195abd-3878-45bf-8b78-93834d4294be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003630732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.2003630732
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.1604180885
Short name T240
Test name
Test status
Simulation time 585421555 ps
CPU time 1.18 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:33:02 PM PDT 24
Peak memory 204720 kb
Host smart-a5c00b89-b9a1-4fc5-94d3-5c95e2f3c4ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604180885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.1604180885
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.1327155154
Short name T251
Test name
Test status
Simulation time 9262139989 ps
CPU time 7.44 seconds
Started Jul 07 05:33:04 PM PDT 24
Finished Jul 07 05:33:11 PM PDT 24
Peak memory 205036 kb
Host smart-d84b234e-c8d4-45b9-b888-97c9b8cc2dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327155154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.1327155154
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.2576337481
Short name T277
Test name
Test status
Simulation time 14496815963 ps
CPU time 1061.62 seconds
Started Jul 07 05:33:46 PM PDT 24
Finished Jul 07 05:51:28 PM PDT 24
Peak memory 1377688 kb
Host smart-91ecc103-50ec-4700-85d4-1460dde1cae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576337481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.2576337481
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_override.2555060804
Short name T250
Test name
Test status
Simulation time 31062948 ps
CPU time 0.69 seconds
Started Jul 07 05:35:12 PM PDT 24
Finished Jul 07 05:35:13 PM PDT 24
Peak memory 204732 kb
Host smart-c343ef3a-4995-4f63-bc26-61ba1bffa636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555060804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2555060804
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.3895120803
Short name T263
Test name
Test status
Simulation time 2315010913 ps
CPU time 3.09 seconds
Started Jul 07 05:35:34 PM PDT 24
Finished Jul 07 05:35:37 PM PDT 24
Peak memory 205108 kb
Host smart-b433f280-b67b-4ce5-bc25-d3f130e548c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895120803 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.3895120803
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.518377342
Short name T244
Test name
Test status
Simulation time 77934282 ps
CPU time 0.97 seconds
Started Jul 07 05:37:34 PM PDT 24
Finished Jul 07 05:37:36 PM PDT 24
Peak memory 204764 kb
Host smart-1146346b-5c39-4cab-8593-8d8f7e8dc976
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518377342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fm
t.518377342
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.2550324563
Short name T67
Test name
Test status
Simulation time 1358821897 ps
CPU time 21.99 seconds
Started Jul 07 05:32:55 PM PDT 24
Finished Jul 07 05:33:17 PM PDT 24
Peak memory 311756 kb
Host smart-b6c15091-d1a5-4c4b-9244-023c264beeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550324563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.2550324563
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.4248856996
Short name T203
Test name
Test status
Simulation time 95856623 ps
CPU time 2.28 seconds
Started Jul 07 05:12:22 PM PDT 24
Finished Jul 07 05:12:25 PM PDT 24
Peak memory 204528 kb
Host smart-5f6e5d7e-f181-4205-b213-6d7f4d13dfd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248856996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.4248856996
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.2724079655
Short name T68
Test name
Test status
Simulation time 3872586448 ps
CPU time 31.62 seconds
Started Jul 07 05:35:53 PM PDT 24
Finished Jul 07 05:36:25 PM PDT 24
Peak memory 358548 kb
Host smart-72b604b0-0b98-404d-b60c-7de5b3d9a606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724079655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.2724079655
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_perf.410593646
Short name T4
Test name
Test status
Simulation time 7091012087 ps
CPU time 618.2 seconds
Started Jul 07 05:33:05 PM PDT 24
Finished Jul 07 05:43:23 PM PDT 24
Peak memory 1739688 kb
Host smart-da8ecd8c-9172-4f8f-bf19-24e9ea07f9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410593646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.410593646
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3639967583
Short name T1536
Test name
Test status
Simulation time 27847661 ps
CPU time 0.68 seconds
Started Jul 07 05:12:29 PM PDT 24
Finished Jul 07 05:12:30 PM PDT 24
Peak memory 204196 kb
Host smart-e073991d-f148-47ba-9127-cf58ff5b54e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639967583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3639967583
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.3822142199
Short name T253
Test name
Test status
Simulation time 32514217396 ps
CPU time 81.15 seconds
Started Jul 07 05:32:55 PM PDT 24
Finished Jul 07 05:34:17 PM PDT 24
Peak memory 214272 kb
Host smart-768cface-701e-437b-a741-6b64aec02b1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822142199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.3822142199
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.584131242
Short name T284
Test name
Test status
Simulation time 11703052677 ps
CPU time 169.58 seconds
Started Jul 07 05:32:54 PM PDT 24
Finished Jul 07 05:35:44 PM PDT 24
Peak memory 784688 kb
Host smart-9fa9b9a7-bf7f-4173-821c-4f450f66e1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584131242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.584131242
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.2586504088
Short name T688
Test name
Test status
Simulation time 139373900 ps
CPU time 1.28 seconds
Started Jul 07 05:34:02 PM PDT 24
Finished Jul 07 05:34:03 PM PDT 24
Peak memory 204804 kb
Host smart-2e2429cf-8d5c-4e2c-817a-14b86574b575
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586504088 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.2586504088
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.2322823829
Short name T395
Test name
Test status
Simulation time 257955105 ps
CPU time 1.42 seconds
Started Jul 07 05:34:05 PM PDT 24
Finished Jul 07 05:34:07 PM PDT 24
Peak memory 204920 kb
Host smart-e41d4b33-b977-481b-9331-e0829894445c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322823829 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.2322823829
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.3848827645
Short name T480
Test name
Test status
Simulation time 1403185740 ps
CPU time 5.1 seconds
Started Jul 07 05:34:14 PM PDT 24
Finished Jul 07 05:34:20 PM PDT 24
Peak memory 256700 kb
Host smart-3f82da9f-a0a8-4a6d-93c1-5577fe1628dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848827645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.3848827645
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.714417576
Short name T272
Test name
Test status
Simulation time 741513810 ps
CPU time 29.97 seconds
Started Jul 07 05:34:55 PM PDT 24
Finished Jul 07 05:35:26 PM PDT 24
Peak memory 204972 kb
Host smart-3083f73b-80eb-4773-bc1a-9a3c111e0303
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714417576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.714417576
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.1777800672
Short name T294
Test name
Test status
Simulation time 1756472793 ps
CPU time 3.51 seconds
Started Jul 07 05:35:35 PM PDT 24
Finished Jul 07 05:35:39 PM PDT 24
Peak memory 205112 kb
Host smart-1c691d7d-a3ea-41fe-baf2-abbf07485210
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777800672 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.1777800672
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2640695752
Short name T373
Test name
Test status
Simulation time 32094211015 ps
CPU time 226.02 seconds
Started Jul 07 05:33:58 PM PDT 24
Finished Jul 07 05:37:45 PM PDT 24
Peak memory 2993120 kb
Host smart-4ad32c9d-3028-45ea-807c-db6486b152ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640695752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2640695752
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.408467922
Short name T92
Test name
Test status
Simulation time 72562763 ps
CPU time 1.54 seconds
Started Jul 07 05:12:14 PM PDT 24
Finished Jul 07 05:12:17 PM PDT 24
Peak memory 204492 kb
Host smart-3aa04a3d-97d1-42bf-855e-148fe08eeabe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408467922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.408467922
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3045761126
Short name T201
Test name
Test status
Simulation time 228120391 ps
CPU time 2.35 seconds
Started Jul 07 05:12:25 PM PDT 24
Finished Jul 07 05:12:27 PM PDT 24
Peak memory 204532 kb
Host smart-719cab87-5e3a-4e17-a658-11f30cf170c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045761126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3045761126
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3435248273
Short name T197
Test name
Test status
Simulation time 238451442 ps
CPU time 2.31 seconds
Started Jul 07 05:12:12 PM PDT 24
Finished Jul 07 05:12:15 PM PDT 24
Peak memory 204472 kb
Host smart-61a0bb98-8701-4660-8fc6-9910cec34d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435248273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3435248273
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3106377070
Short name T209
Test name
Test status
Simulation time 134714952 ps
CPU time 1.36 seconds
Started Jul 07 05:12:15 PM PDT 24
Finished Jul 07 05:12:17 PM PDT 24
Peak memory 204556 kb
Host smart-a83eff5c-64f2-4250-ad52-c414b744a759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106377070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3106377070
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.182974550
Short name T1611
Test name
Test status
Simulation time 41539807 ps
CPU time 1.85 seconds
Started Jul 07 05:12:09 PM PDT 24
Finished Jul 07 05:12:12 PM PDT 24
Peak memory 204408 kb
Host smart-db7aca71-9612-4bc6-b8f3-c00d11b7b760
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182974550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.182974550
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.718705229
Short name T1612
Test name
Test status
Simulation time 65972728 ps
CPU time 2.62 seconds
Started Jul 07 05:12:14 PM PDT 24
Finished Jul 07 05:12:18 PM PDT 24
Peak memory 203132 kb
Host smart-a35f020a-e78f-4394-b71f-0417cc1e7398
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718705229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.718705229
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.609266064
Short name T1591
Test name
Test status
Simulation time 54200740 ps
CPU time 0.7 seconds
Started Jul 07 05:12:07 PM PDT 24
Finished Jul 07 05:12:09 PM PDT 24
Peak memory 204224 kb
Host smart-887d1fdc-8522-4c33-86e6-e6199c5f1364
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609266064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.609266064
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3650077416
Short name T1569
Test name
Test status
Simulation time 148122278 ps
CPU time 0.97 seconds
Started Jul 07 05:12:09 PM PDT 24
Finished Jul 07 05:12:11 PM PDT 24
Peak memory 204380 kb
Host smart-918ff859-5ca3-4673-9686-ee9569d009c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650077416 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.3650077416
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2337678753
Short name T1633
Test name
Test status
Simulation time 289355141 ps
CPU time 1.17 seconds
Started Jul 07 05:12:05 PM PDT 24
Finished Jul 07 05:12:07 PM PDT 24
Peak memory 204236 kb
Host smart-3176696c-49bc-4479-a112-166a5d7dc426
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337678753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2337678753
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.942506642
Short name T1621
Test name
Test status
Simulation time 89917128 ps
CPU time 0.69 seconds
Started Jul 07 05:12:08 PM PDT 24
Finished Jul 07 05:12:09 PM PDT 24
Peak memory 204196 kb
Host smart-e7b6feaf-a3c6-4143-aac6-ba88477deb2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942506642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.942506642
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2122717447
Short name T1579
Test name
Test status
Simulation time 132884491 ps
CPU time 1.14 seconds
Started Jul 07 05:12:13 PM PDT 24
Finished Jul 07 05:12:15 PM PDT 24
Peak memory 204496 kb
Host smart-50deefc8-4643-413d-9f42-b99f53d10223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122717447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2122717447
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.4250603880
Short name T1597
Test name
Test status
Simulation time 75417467 ps
CPU time 2.25 seconds
Started Jul 07 05:12:05 PM PDT 24
Finished Jul 07 05:12:09 PM PDT 24
Peak memory 204528 kb
Host smart-1b989af4-eb16-44ad-b167-5ce2fe646c34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250603880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.4250603880
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.4004992983
Short name T265
Test name
Test status
Simulation time 48348972 ps
CPU time 1.42 seconds
Started Jul 07 05:12:10 PM PDT 24
Finished Jul 07 05:12:12 PM PDT 24
Peak memory 204520 kb
Host smart-b6f30877-2c3d-4ec6-bc54-281bfd54f29d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004992983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.4004992983
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.445550873
Short name T1623
Test name
Test status
Simulation time 1400347420 ps
CPU time 4.9 seconds
Started Jul 07 05:12:14 PM PDT 24
Finished Jul 07 05:12:20 PM PDT 24
Peak memory 202864 kb
Host smart-3f85bbc7-7e0b-44e8-b2bc-d7ddd1bfc8af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445550873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.445550873
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3570361406
Short name T215
Test name
Test status
Simulation time 32021899 ps
CPU time 0.8 seconds
Started Jul 07 05:12:09 PM PDT 24
Finished Jul 07 05:12:10 PM PDT 24
Peak memory 204252 kb
Host smart-3c8974cc-311b-4192-ab12-09ec20e801ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570361406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3570361406
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.367541184
Short name T207
Test name
Test status
Simulation time 123225473 ps
CPU time 0.97 seconds
Started Jul 07 05:12:13 PM PDT 24
Finished Jul 07 05:12:15 PM PDT 24
Peak memory 204320 kb
Host smart-46f732be-2515-4955-b19a-0fb89cce3a77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367541184 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.367541184
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1432920711
Short name T216
Test name
Test status
Simulation time 15694717 ps
CPU time 0.69 seconds
Started Jul 07 05:12:11 PM PDT 24
Finished Jul 07 05:12:12 PM PDT 24
Peak memory 204240 kb
Host smart-e16d67d9-a0f6-43cd-9f06-5bf9297a15aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432920711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1432920711
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3739002613
Short name T1604
Test name
Test status
Simulation time 55110231 ps
CPU time 0.65 seconds
Started Jul 07 05:12:16 PM PDT 24
Finished Jul 07 05:12:17 PM PDT 24
Peak memory 204204 kb
Host smart-3eadeb49-7f21-4e80-84b5-1e59e42684ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739002613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3739002613
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3711981284
Short name T1548
Test name
Test status
Simulation time 35650539 ps
CPU time 0.83 seconds
Started Jul 07 05:12:09 PM PDT 24
Finished Jul 07 05:12:11 PM PDT 24
Peak memory 204212 kb
Host smart-8ffed280-5a57-4c8e-8009-04895c87724e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711981284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.3711981284
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.292332693
Short name T1586
Test name
Test status
Simulation time 287912941 ps
CPU time 1.86 seconds
Started Jul 07 05:12:07 PM PDT 24
Finished Jul 07 05:12:10 PM PDT 24
Peak memory 204576 kb
Host smart-c2cd096e-d8e3-4d4c-84d4-69a9656b90e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292332693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.292332693
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3888298065
Short name T1581
Test name
Test status
Simulation time 49865379 ps
CPU time 1.41 seconds
Started Jul 07 05:12:08 PM PDT 24
Finished Jul 07 05:12:10 PM PDT 24
Peak memory 204748 kb
Host smart-ba3e70ba-21f6-488f-bfec-bcb7ac863705
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888298065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3888298065
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1203841157
Short name T1575
Test name
Test status
Simulation time 141280492 ps
CPU time 1.08 seconds
Started Jul 07 05:12:17 PM PDT 24
Finished Jul 07 05:12:19 PM PDT 24
Peak memory 204376 kb
Host smart-bb5c90d4-dbd7-42c9-81ed-6f68ac80c90a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203841157 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1203841157
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1724082964
Short name T218
Test name
Test status
Simulation time 49184089 ps
CPU time 0.74 seconds
Started Jul 07 05:12:18 PM PDT 24
Finished Jul 07 05:12:19 PM PDT 24
Peak memory 204232 kb
Host smart-4fe03c87-fd9d-496a-9902-e696946b5169
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724082964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1724082964
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3158727712
Short name T1538
Test name
Test status
Simulation time 41006294 ps
CPU time 0.7 seconds
Started Jul 07 05:12:15 PM PDT 24
Finished Jul 07 05:12:17 PM PDT 24
Peak memory 204236 kb
Host smart-9d0b3043-732d-4581-a09e-e6140f67b3d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158727712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3158727712
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2400053766
Short name T1568
Test name
Test status
Simulation time 34303655 ps
CPU time 1.58 seconds
Started Jul 07 05:12:16 PM PDT 24
Finished Jul 07 05:12:18 PM PDT 24
Peak memory 204540 kb
Host smart-4836d171-054f-4288-a5f8-3705b6bf50ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400053766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2400053766
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4060776243
Short name T1607
Test name
Test status
Simulation time 119539057 ps
CPU time 2.24 seconds
Started Jul 07 05:12:19 PM PDT 24
Finished Jul 07 05:12:22 PM PDT 24
Peak memory 204528 kb
Host smart-468e008f-c5cd-48cf-8578-7224d25c0fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060776243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.4060776243
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1004175474
Short name T1622
Test name
Test status
Simulation time 124968958 ps
CPU time 0.97 seconds
Started Jul 07 05:12:20 PM PDT 24
Finished Jul 07 05:12:22 PM PDT 24
Peak memory 204300 kb
Host smart-8eed3045-1b4d-4588-bcdd-54bd238491ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004175474 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1004175474
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3085629829
Short name T93
Test name
Test status
Simulation time 20002206 ps
CPU time 0.67 seconds
Started Jul 07 05:12:14 PM PDT 24
Finished Jul 07 05:12:15 PM PDT 24
Peak memory 204240 kb
Host smart-78dc99b7-3964-411e-a5f2-d46df6c0c090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085629829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3085629829
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.70304517
Short name T1600
Test name
Test status
Simulation time 18730006 ps
CPU time 0.65 seconds
Started Jul 07 05:12:17 PM PDT 24
Finished Jul 07 05:12:19 PM PDT 24
Peak memory 204072 kb
Host smart-a364c591-fbee-4ead-9a87-ad2f433b69d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70304517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.70304517
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2021771028
Short name T231
Test name
Test status
Simulation time 35591451 ps
CPU time 0.89 seconds
Started Jul 07 05:12:17 PM PDT 24
Finished Jul 07 05:12:19 PM PDT 24
Peak memory 204236 kb
Host smart-63c1e197-5e73-4631-aded-f136cbfa65fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021771028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2021771028
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2989745279
Short name T1632
Test name
Test status
Simulation time 52202528 ps
CPU time 1.26 seconds
Started Jul 07 05:12:17 PM PDT 24
Finished Jul 07 05:12:19 PM PDT 24
Peak memory 204564 kb
Host smart-4e772acc-80ca-4393-ac31-a093279947f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989745279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2989745279
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.579282367
Short name T266
Test name
Test status
Simulation time 82446039 ps
CPU time 1.58 seconds
Started Jul 07 05:12:19 PM PDT 24
Finished Jul 07 05:12:22 PM PDT 24
Peak memory 204472 kb
Host smart-3cde3d24-6996-4c43-9e6b-c384937a1cf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579282367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.579282367
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3484427919
Short name T1541
Test name
Test status
Simulation time 58802797 ps
CPU time 0.99 seconds
Started Jul 07 05:12:18 PM PDT 24
Finished Jul 07 05:12:20 PM PDT 24
Peak memory 204324 kb
Host smart-7baa6fc6-e065-421e-9fb2-ce9ba536b240
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484427919 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3484427919
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1890269030
Short name T219
Test name
Test status
Simulation time 42054056 ps
CPU time 0.77 seconds
Started Jul 07 05:12:19 PM PDT 24
Finished Jul 07 05:12:21 PM PDT 24
Peak memory 204236 kb
Host smart-4e9b6d16-14cd-4211-b291-b6489695d8b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890269030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1890269030
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2334819872
Short name T1625
Test name
Test status
Simulation time 27608783 ps
CPU time 0.64 seconds
Started Jul 07 05:12:20 PM PDT 24
Finished Jul 07 05:12:22 PM PDT 24
Peak memory 204136 kb
Host smart-dd49d267-1bc0-4f31-9099-0dbe8b607da7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334819872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2334819872
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1568812908
Short name T1631
Test name
Test status
Simulation time 75509930 ps
CPU time 1.88 seconds
Started Jul 07 05:12:19 PM PDT 24
Finished Jul 07 05:12:21 PM PDT 24
Peak memory 204524 kb
Host smart-236a15ee-4c7b-4435-8d96-28e4ab5ec9a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568812908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1568812908
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1121420620
Short name T1606
Test name
Test status
Simulation time 24267396 ps
CPU time 1.07 seconds
Started Jul 07 05:12:26 PM PDT 24
Finished Jul 07 05:12:28 PM PDT 24
Peak memory 204440 kb
Host smart-7942ea70-8adc-49e7-ab0e-91034f1f6578
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121420620 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1121420620
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.818122184
Short name T227
Test name
Test status
Simulation time 15776561 ps
CPU time 0.69 seconds
Started Jul 07 05:12:19 PM PDT 24
Finished Jul 07 05:12:20 PM PDT 24
Peak memory 204136 kb
Host smart-87141047-f97f-4a10-bc61-2802303b2e1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818122184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.818122184
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2902155328
Short name T1594
Test name
Test status
Simulation time 18018293 ps
CPU time 0.68 seconds
Started Jul 07 05:12:21 PM PDT 24
Finished Jul 07 05:12:23 PM PDT 24
Peak memory 204220 kb
Host smart-2a548702-eccb-4eac-932f-5815a0668e29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902155328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2902155328
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3457006601
Short name T232
Test name
Test status
Simulation time 26294272 ps
CPU time 1.08 seconds
Started Jul 07 05:12:22 PM PDT 24
Finished Jul 07 05:12:24 PM PDT 24
Peak memory 204536 kb
Host smart-29e4529c-2198-4f92-83ee-aeb96d612e1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457006601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3457006601
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3291434655
Short name T1630
Test name
Test status
Simulation time 30986037 ps
CPU time 1.35 seconds
Started Jul 07 05:12:20 PM PDT 24
Finished Jul 07 05:12:23 PM PDT 24
Peak memory 204536 kb
Host smart-2fe4b150-fcaf-4b19-b22b-5cda599d5188
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291434655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3291434655
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3055387588
Short name T202
Test name
Test status
Simulation time 134939557 ps
CPU time 2.18 seconds
Started Jul 07 05:12:21 PM PDT 24
Finished Jul 07 05:12:24 PM PDT 24
Peak memory 204504 kb
Host smart-a3a8785f-f0ee-4e3f-8ffb-365db0057fe3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055387588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3055387588
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1868454422
Short name T1564
Test name
Test status
Simulation time 30562436 ps
CPU time 0.86 seconds
Started Jul 07 05:12:27 PM PDT 24
Finished Jul 07 05:12:29 PM PDT 24
Peak memory 204648 kb
Host smart-adbce781-074c-4b4b-809b-2e01418b3097
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868454422 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1868454422
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.859870494
Short name T1620
Test name
Test status
Simulation time 42384315 ps
CPU time 0.72 seconds
Started Jul 07 05:12:21 PM PDT 24
Finished Jul 07 05:12:23 PM PDT 24
Peak memory 204276 kb
Host smart-6ded98f3-96d6-42e7-8b71-38bae83936b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859870494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.859870494
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.2109600994
Short name T1593
Test name
Test status
Simulation time 18306318 ps
CPU time 0.71 seconds
Started Jul 07 05:12:21 PM PDT 24
Finished Jul 07 05:12:23 PM PDT 24
Peak memory 204244 kb
Host smart-b481a7e2-ecd8-4839-a044-c81072cd1d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109600994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.2109600994
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2859808163
Short name T100
Test name
Test status
Simulation time 38365816 ps
CPU time 0.87 seconds
Started Jul 07 05:12:19 PM PDT 24
Finished Jul 07 05:12:21 PM PDT 24
Peak memory 204272 kb
Host smart-7ae0c36d-5769-49dc-bceb-d7dd87516a14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859808163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2859808163
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.322026316
Short name T1561
Test name
Test status
Simulation time 293757866 ps
CPU time 1.97 seconds
Started Jul 07 05:12:25 PM PDT 24
Finished Jul 07 05:12:28 PM PDT 24
Peak memory 204404 kb
Host smart-35a9db6d-10a1-4fea-8a53-b5495f6f36ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322026316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.322026316
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3924589975
Short name T200
Test name
Test status
Simulation time 589190443 ps
CPU time 2.38 seconds
Started Jul 07 05:12:20 PM PDT 24
Finished Jul 07 05:12:24 PM PDT 24
Peak memory 204412 kb
Host smart-7a6b51e9-f3bd-4f06-9056-d6b92575f550
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924589975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3924589975
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1276313415
Short name T1610
Test name
Test status
Simulation time 26022434 ps
CPU time 1.14 seconds
Started Jul 07 05:12:20 PM PDT 24
Finished Jul 07 05:12:23 PM PDT 24
Peak memory 204592 kb
Host smart-ad0d768e-a5d5-48fc-971e-62bf7f01531f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276313415 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1276313415
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3832431064
Short name T95
Test name
Test status
Simulation time 95873430 ps
CPU time 0.72 seconds
Started Jul 07 05:12:21 PM PDT 24
Finished Jul 07 05:12:23 PM PDT 24
Peak memory 204244 kb
Host smart-e27382d2-2d59-4b68-aeb5-2be19996e0c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832431064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3832431064
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.2843029401
Short name T121
Test name
Test status
Simulation time 120713979 ps
CPU time 0.74 seconds
Started Jul 07 05:12:19 PM PDT 24
Finished Jul 07 05:12:21 PM PDT 24
Peak memory 204232 kb
Host smart-7ed1f770-98db-47ac-b3df-36df7b939902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843029401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2843029401
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1456395442
Short name T1624
Test name
Test status
Simulation time 241549571 ps
CPU time 1.09 seconds
Started Jul 07 05:12:19 PM PDT 24
Finished Jul 07 05:12:22 PM PDT 24
Peak memory 204524 kb
Host smart-29b7fdf9-37f5-447e-ae4b-1c358f98ee3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456395442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.1456395442
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1680033723
Short name T1556
Test name
Test status
Simulation time 247016094 ps
CPU time 1.69 seconds
Started Jul 07 05:12:22 PM PDT 24
Finished Jul 07 05:12:24 PM PDT 24
Peak memory 204548 kb
Host smart-6d16e9fd-a02c-46c1-95f4-1a99b245b762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680033723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1680033723
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.361194482
Short name T1557
Test name
Test status
Simulation time 41829695 ps
CPU time 0.8 seconds
Started Jul 07 05:12:21 PM PDT 24
Finished Jul 07 05:12:23 PM PDT 24
Peak memory 204372 kb
Host smart-a8084dde-e34f-43ef-8bd9-164fee53cf1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361194482 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.361194482
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2439682767
Short name T1587
Test name
Test status
Simulation time 19563569 ps
CPU time 0.75 seconds
Started Jul 07 05:12:20 PM PDT 24
Finished Jul 07 05:12:22 PM PDT 24
Peak memory 204200 kb
Host smart-056cb977-7ee5-4e25-9043-7f186a32e998
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439682767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2439682767
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.2701345421
Short name T1601
Test name
Test status
Simulation time 17212654 ps
CPU time 0.71 seconds
Started Jul 07 05:12:24 PM PDT 24
Finished Jul 07 05:12:25 PM PDT 24
Peak memory 204236 kb
Host smart-336c56db-9ad4-4389-81fd-bc6d1f55d98f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701345421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2701345421
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3729008926
Short name T1602
Test name
Test status
Simulation time 112262867 ps
CPU time 0.85 seconds
Started Jul 07 05:12:22 PM PDT 24
Finished Jul 07 05:12:23 PM PDT 24
Peak memory 204264 kb
Host smart-279895ec-731f-4ca3-b1dc-b95dfa0458ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729008926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3729008926
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.768468784
Short name T199
Test name
Test status
Simulation time 74974873 ps
CPU time 1.17 seconds
Started Jul 07 05:12:22 PM PDT 24
Finished Jul 07 05:12:24 PM PDT 24
Peak memory 204556 kb
Host smart-942e7681-9d88-439e-a85c-8a5b815ae721
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768468784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.768468784
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.829126686
Short name T198
Test name
Test status
Simulation time 446434808 ps
CPU time 2.33 seconds
Started Jul 07 05:12:23 PM PDT 24
Finished Jul 07 05:12:26 PM PDT 24
Peak memory 204548 kb
Host smart-ce985940-fe32-4cd5-9324-52d9c16bc0b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829126686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.829126686
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3480122036
Short name T1543
Test name
Test status
Simulation time 34270693 ps
CPU time 0.97 seconds
Started Jul 07 05:12:22 PM PDT 24
Finished Jul 07 05:12:24 PM PDT 24
Peak memory 204344 kb
Host smart-5cb0ba7a-429b-4049-b76b-09055223e278
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480122036 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3480122036
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4286829795
Short name T115
Test name
Test status
Simulation time 19576845 ps
CPU time 0.75 seconds
Started Jul 07 05:12:25 PM PDT 24
Finished Jul 07 05:12:27 PM PDT 24
Peak memory 204220 kb
Host smart-4cdaf519-97ae-4205-888e-24c86ab3d16f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286829795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.4286829795
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.3935510658
Short name T1580
Test name
Test status
Simulation time 20373634 ps
CPU time 0.73 seconds
Started Jul 07 05:12:25 PM PDT 24
Finished Jul 07 05:12:27 PM PDT 24
Peak memory 203796 kb
Host smart-1738c06d-1744-4ed6-a674-27d119cf1b36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935510658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.3935510658
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.4218573642
Short name T1634
Test name
Test status
Simulation time 179177891 ps
CPU time 0.92 seconds
Started Jul 07 05:12:24 PM PDT 24
Finished Jul 07 05:12:26 PM PDT 24
Peak memory 204352 kb
Host smart-f00c4051-e68d-4693-b439-0f85a0dc20d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218573642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.4218573642
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3681968807
Short name T206
Test name
Test status
Simulation time 70232081 ps
CPU time 1.62 seconds
Started Jul 07 05:12:28 PM PDT 24
Finished Jul 07 05:12:30 PM PDT 24
Peak memory 204564 kb
Host smart-d0990640-9db2-4379-85e2-a3c9ca2c7672
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681968807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3681968807
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2539198754
Short name T97
Test name
Test status
Simulation time 40587113 ps
CPU time 0.97 seconds
Started Jul 07 05:12:24 PM PDT 24
Finished Jul 07 05:12:25 PM PDT 24
Peak memory 204260 kb
Host smart-99efa9fc-fa31-49b7-8229-fc46a10bfa75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539198754 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2539198754
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.62163619
Short name T221
Test name
Test status
Simulation time 15298677 ps
CPU time 0.66 seconds
Started Jul 07 05:12:25 PM PDT 24
Finished Jul 07 05:12:26 PM PDT 24
Peak memory 204180 kb
Host smart-975fc5f8-108c-48f4-ab69-0258b400a1c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62163619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.62163619
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3899094591
Short name T1566
Test name
Test status
Simulation time 15841117 ps
CPU time 0.76 seconds
Started Jul 07 05:12:25 PM PDT 24
Finished Jul 07 05:12:27 PM PDT 24
Peak memory 204244 kb
Host smart-9996dd1c-3c92-4f54-a23c-a3c15a1303f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899094591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3899094591
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.650810227
Short name T1628
Test name
Test status
Simulation time 23574383 ps
CPU time 0.88 seconds
Started Jul 07 05:12:25 PM PDT 24
Finished Jul 07 05:12:27 PM PDT 24
Peak memory 203928 kb
Host smart-9f408cd3-982a-47c2-b128-d64d392523b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650810227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_ou
tstanding.650810227
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3565386367
Short name T151
Test name
Test status
Simulation time 110957014 ps
CPU time 1.64 seconds
Started Jul 07 05:12:25 PM PDT 24
Finished Jul 07 05:12:28 PM PDT 24
Peak memory 213836 kb
Host smart-08805956-594b-49cb-8d90-ca3bc4cc767b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565386367 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3565386367
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2790997498
Short name T223
Test name
Test status
Simulation time 22009040 ps
CPU time 0.75 seconds
Started Jul 07 05:12:25 PM PDT 24
Finished Jul 07 05:12:27 PM PDT 24
Peak memory 204252 kb
Host smart-00413fa2-edec-47e2-ac49-1c19d07eab8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790997498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2790997498
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.3555070102
Short name T1553
Test name
Test status
Simulation time 17012338 ps
CPU time 0.72 seconds
Started Jul 07 05:12:23 PM PDT 24
Finished Jul 07 05:12:24 PM PDT 24
Peak memory 204244 kb
Host smart-c4b4a21d-01f5-4d17-a1ec-667cbd3c634f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555070102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.3555070102
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2969385817
Short name T1545
Test name
Test status
Simulation time 100725703 ps
CPU time 0.87 seconds
Started Jul 07 05:12:23 PM PDT 24
Finished Jul 07 05:12:24 PM PDT 24
Peak memory 204348 kb
Host smart-92b2a2f1-784e-4d38-bafd-5391a8ab3f47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969385817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2969385817
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2430949966
Short name T1551
Test name
Test status
Simulation time 199399509 ps
CPU time 2.62 seconds
Started Jul 07 05:12:23 PM PDT 24
Finished Jul 07 05:12:26 PM PDT 24
Peak memory 204520 kb
Host smart-ca27e53f-2fdf-4c32-a081-04920d537084
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430949966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2430949966
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2213435043
Short name T1599
Test name
Test status
Simulation time 141715511 ps
CPU time 2.26 seconds
Started Jul 07 05:12:23 PM PDT 24
Finished Jul 07 05:12:26 PM PDT 24
Peak memory 204492 kb
Host smart-a7c56064-797c-4302-919e-b01dfc452af8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213435043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2213435043
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1908963290
Short name T226
Test name
Test status
Simulation time 93964536 ps
CPU time 1.94 seconds
Started Jul 07 05:12:12 PM PDT 24
Finished Jul 07 05:12:14 PM PDT 24
Peak memory 204476 kb
Host smart-24bb3058-1372-45ad-be81-184a9e1d62f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908963290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1908963290
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.405375652
Short name T1589
Test name
Test status
Simulation time 758898936 ps
CPU time 2.76 seconds
Started Jul 07 05:12:11 PM PDT 24
Finished Jul 07 05:12:14 PM PDT 24
Peak memory 204400 kb
Host smart-2d2c2ec9-71ae-4d11-abcb-61fbf6306c8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405375652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.405375652
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.92276823
Short name T1615
Test name
Test status
Simulation time 64978178 ps
CPU time 0.7 seconds
Started Jul 07 05:12:07 PM PDT 24
Finished Jul 07 05:12:08 PM PDT 24
Peak memory 204208 kb
Host smart-42aedc59-ae79-40a5-92a6-7d46acccbef3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92276823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.92276823
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.905671389
Short name T233
Test name
Test status
Simulation time 19289855 ps
CPU time 0.7 seconds
Started Jul 07 05:12:06 PM PDT 24
Finished Jul 07 05:12:08 PM PDT 24
Peak memory 204176 kb
Host smart-a0adbcc1-b024-4315-bc20-b76d9252e7ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905671389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.905671389
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.2866672458
Short name T1576
Test name
Test status
Simulation time 18675053 ps
CPU time 0.72 seconds
Started Jul 07 05:12:15 PM PDT 24
Finished Jul 07 05:12:16 PM PDT 24
Peak memory 204228 kb
Host smart-27ed244c-910a-42bf-b928-e95e1d23d360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866672458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.2866672458
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1933232535
Short name T1613
Test name
Test status
Simulation time 149353437 ps
CPU time 0.98 seconds
Started Jul 07 05:12:11 PM PDT 24
Finished Jul 07 05:12:12 PM PDT 24
Peak memory 204436 kb
Host smart-8e217d36-9b08-47e8-a3d8-41eb6397d314
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933232535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1933232535
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3580759232
Short name T1582
Test name
Test status
Simulation time 103748313 ps
CPU time 1.62 seconds
Started Jul 07 05:12:12 PM PDT 24
Finished Jul 07 05:12:14 PM PDT 24
Peak memory 204552 kb
Host smart-b1f6a3a7-2caf-4751-aed4-d6381411d852
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580759232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3580759232
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3910783568
Short name T1588
Test name
Test status
Simulation time 150300508 ps
CPU time 1.43 seconds
Started Jul 07 05:12:08 PM PDT 24
Finished Jul 07 05:12:10 PM PDT 24
Peak memory 204464 kb
Host smart-bca5df2c-d021-40d6-a73b-15f058909d63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910783568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3910783568
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.4279701863
Short name T1560
Test name
Test status
Simulation time 34279997 ps
CPU time 0.67 seconds
Started Jul 07 05:12:23 PM PDT 24
Finished Jul 07 05:12:24 PM PDT 24
Peak memory 204228 kb
Host smart-f4750c2c-53c4-428f-8429-52759f2293bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279701863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.4279701863
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.1104921870
Short name T1618
Test name
Test status
Simulation time 29172569 ps
CPU time 0.68 seconds
Started Jul 07 05:12:28 PM PDT 24
Finished Jul 07 05:12:29 PM PDT 24
Peak memory 204224 kb
Host smart-5901d579-1624-4e8a-bf70-68475a722f33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104921870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1104921870
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.4046277083
Short name T1573
Test name
Test status
Simulation time 17404352 ps
CPU time 0.69 seconds
Started Jul 07 05:12:29 PM PDT 24
Finished Jul 07 05:12:30 PM PDT 24
Peak memory 204268 kb
Host smart-52112482-cc24-4d88-8994-be88f18b2612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046277083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.4046277083
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1703155247
Short name T1544
Test name
Test status
Simulation time 22768803 ps
CPU time 0.72 seconds
Started Jul 07 05:12:31 PM PDT 24
Finished Jul 07 05:12:32 PM PDT 24
Peak memory 204248 kb
Host smart-e7eab27e-cf93-47d8-83f6-250f9cba70de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703155247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1703155247
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.2580915967
Short name T1550
Test name
Test status
Simulation time 18332604 ps
CPU time 0.68 seconds
Started Jul 07 05:12:29 PM PDT 24
Finished Jul 07 05:12:30 PM PDT 24
Peak memory 204244 kb
Host smart-2103d37f-9098-4020-8e88-dddce82f8613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580915967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2580915967
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.2817502925
Short name T1590
Test name
Test status
Simulation time 45434415 ps
CPU time 0.7 seconds
Started Jul 07 05:12:28 PM PDT 24
Finished Jul 07 05:12:29 PM PDT 24
Peak memory 204208 kb
Host smart-37ef300c-a4f6-4d60-86f1-ebfa5eb24252
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817502925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2817502925
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.323698385
Short name T1617
Test name
Test status
Simulation time 14553634 ps
CPU time 0.65 seconds
Started Jul 07 05:12:29 PM PDT 24
Finished Jul 07 05:12:30 PM PDT 24
Peak memory 204248 kb
Host smart-ceca294b-2ac9-4c04-afb1-2e3016963669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323698385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.323698385
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2677329895
Short name T1533
Test name
Test status
Simulation time 22166378 ps
CPU time 0.71 seconds
Started Jul 07 05:12:30 PM PDT 24
Finished Jul 07 05:12:31 PM PDT 24
Peak memory 204232 kb
Host smart-41a0fc8a-c274-4cfa-b8d6-7e01dabd7555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677329895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2677329895
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.2133171732
Short name T1565
Test name
Test status
Simulation time 18129045 ps
CPU time 0.68 seconds
Started Jul 07 05:12:27 PM PDT 24
Finished Jul 07 05:12:28 PM PDT 24
Peak memory 204504 kb
Host smart-b75a68cb-ccc5-4f03-8856-3e3356b2e550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133171732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2133171732
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.4139192636
Short name T225
Test name
Test status
Simulation time 84079946 ps
CPU time 1.31 seconds
Started Jul 07 05:12:09 PM PDT 24
Finished Jul 07 05:12:11 PM PDT 24
Peak memory 204480 kb
Host smart-9e46367b-1713-47c6-b77d-cfb97590540d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139192636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.4139192636
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.894070069
Short name T1562
Test name
Test status
Simulation time 67619641 ps
CPU time 2.47 seconds
Started Jul 07 05:12:06 PM PDT 24
Finished Jul 07 05:12:10 PM PDT 24
Peak memory 204336 kb
Host smart-76d8fa49-9d43-4f75-8328-394eefd96896
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894070069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.894070069
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1746798305
Short name T228
Test name
Test status
Simulation time 31166992 ps
CPU time 0.79 seconds
Started Jul 07 05:12:09 PM PDT 24
Finished Jul 07 05:12:11 PM PDT 24
Peak memory 204236 kb
Host smart-9d4d00e0-de89-45b9-b4c1-7d57fa81e33e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746798305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1746798305
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3683586807
Short name T101
Test name
Test status
Simulation time 37560326 ps
CPU time 0.89 seconds
Started Jul 07 05:12:14 PM PDT 24
Finished Jul 07 05:12:16 PM PDT 24
Peak memory 204340 kb
Host smart-13558198-2d3d-4470-b279-4049c90b5ecc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683586807 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3683586807
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2007473703
Short name T1546
Test name
Test status
Simulation time 77166514 ps
CPU time 0.86 seconds
Started Jul 07 05:12:15 PM PDT 24
Finished Jul 07 05:12:17 PM PDT 24
Peak memory 204244 kb
Host smart-4a073ef1-c28a-49b9-9c8f-1a5b53cf9544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007473703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.2007473703
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.539611993
Short name T1638
Test name
Test status
Simulation time 36800822 ps
CPU time 0.71 seconds
Started Jul 07 05:12:14 PM PDT 24
Finished Jul 07 05:12:16 PM PDT 24
Peak memory 204112 kb
Host smart-9aa11e72-2a9e-44f6-916b-2be9107a9145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539611993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.539611993
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.284870918
Short name T234
Test name
Test status
Simulation time 185477262 ps
CPU time 1.26 seconds
Started Jul 07 05:12:11 PM PDT 24
Finished Jul 07 05:12:13 PM PDT 24
Peak memory 204564 kb
Host smart-174ec710-683c-47d0-8ab6-565e1815bc74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284870918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_out
standing.284870918
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3493190705
Short name T210
Test name
Test status
Simulation time 376609802 ps
CPU time 2.43 seconds
Started Jul 07 05:12:14 PM PDT 24
Finished Jul 07 05:12:18 PM PDT 24
Peak memory 204248 kb
Host smart-5680a3e9-419e-48fc-8ece-9d1ba161d9d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493190705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3493190705
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.3928266939
Short name T122
Test name
Test status
Simulation time 35699837 ps
CPU time 0.68 seconds
Started Jul 07 05:12:25 PM PDT 24
Finished Jul 07 05:12:27 PM PDT 24
Peak memory 204192 kb
Host smart-0b2af57b-237d-4a86-a9f8-c1c6637a2ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928266939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3928266939
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2640027478
Short name T1637
Test name
Test status
Simulation time 27246774 ps
CPU time 0.69 seconds
Started Jul 07 05:12:27 PM PDT 24
Finished Jul 07 05:12:28 PM PDT 24
Peak memory 204180 kb
Host smart-27abf91f-3ea6-4a8f-8da4-6e1bf5d13d3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640027478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2640027478
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.1649785474
Short name T1609
Test name
Test status
Simulation time 50971169 ps
CPU time 0.72 seconds
Started Jul 07 05:12:29 PM PDT 24
Finished Jul 07 05:12:30 PM PDT 24
Peak memory 204244 kb
Host smart-a247a4c3-3945-420d-b831-45bee9942e60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649785474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1649785474
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.662448181
Short name T1592
Test name
Test status
Simulation time 27401190 ps
CPU time 0.67 seconds
Started Jul 07 05:12:29 PM PDT 24
Finished Jul 07 05:12:30 PM PDT 24
Peak memory 204244 kb
Host smart-e9d3ed57-1d77-4c07-ac33-040a7218d379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662448181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.662448181
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.4184780240
Short name T1537
Test name
Test status
Simulation time 20348211 ps
CPU time 0.72 seconds
Started Jul 07 05:12:35 PM PDT 24
Finished Jul 07 05:12:37 PM PDT 24
Peak memory 204288 kb
Host smart-1bd7589d-88db-4d2d-90f2-201143398e1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184780240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.4184780240
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.1066889810
Short name T1577
Test name
Test status
Simulation time 80107560 ps
CPU time 0.7 seconds
Started Jul 07 05:12:32 PM PDT 24
Finished Jul 07 05:12:33 PM PDT 24
Peak memory 204200 kb
Host smart-755a8a7f-f762-46f3-b9f4-ccca42a06d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066889810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1066889810
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1775818345
Short name T1578
Test name
Test status
Simulation time 31620122 ps
CPU time 0.64 seconds
Started Jul 07 05:12:36 PM PDT 24
Finished Jul 07 05:12:37 PM PDT 24
Peak memory 204240 kb
Host smart-842edbfc-1485-48c9-9a7f-581931ad2970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775818345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1775818345
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.2916319274
Short name T1542
Test name
Test status
Simulation time 27507055 ps
CPU time 0.67 seconds
Started Jul 07 05:12:33 PM PDT 24
Finished Jul 07 05:12:34 PM PDT 24
Peak memory 204236 kb
Host smart-947491f2-d209-46e3-be0d-88ba86516d81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916319274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.2916319274
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2886056797
Short name T1629
Test name
Test status
Simulation time 18623660 ps
CPU time 0.67 seconds
Started Jul 07 05:12:32 PM PDT 24
Finished Jul 07 05:12:33 PM PDT 24
Peak memory 204252 kb
Host smart-0c3a229d-f871-4d29-aef9-ad884a22a52c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886056797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2886056797
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.3593839104
Short name T1535
Test name
Test status
Simulation time 177616390 ps
CPU time 0.71 seconds
Started Jul 07 05:12:34 PM PDT 24
Finished Jul 07 05:12:34 PM PDT 24
Peak memory 204284 kb
Host smart-06817723-0dc9-4ae2-9ed5-8d3dc51aedad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593839104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3593839104
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2054236271
Short name T220
Test name
Test status
Simulation time 30722940 ps
CPU time 1.27 seconds
Started Jul 07 05:12:13 PM PDT 24
Finished Jul 07 05:12:15 PM PDT 24
Peak memory 204448 kb
Host smart-4c6004dd-09ac-41a7-b9e7-6aa8aba5a1a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054236271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2054236271
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1525619489
Short name T1539
Test name
Test status
Simulation time 214862619 ps
CPU time 2.54 seconds
Started Jul 07 05:12:12 PM PDT 24
Finished Jul 07 05:12:16 PM PDT 24
Peak memory 204472 kb
Host smart-29dc06bf-2d94-4ec9-8480-8632ff9b8873
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525619489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1525619489
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.519132573
Short name T1552
Test name
Test status
Simulation time 96083281 ps
CPU time 0.75 seconds
Started Jul 07 05:12:14 PM PDT 24
Finished Jul 07 05:12:16 PM PDT 24
Peak memory 204248 kb
Host smart-603b3f1b-7f37-4de5-a1d4-7623960e8174
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519132573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.519132573
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.627437204
Short name T1635
Test name
Test status
Simulation time 60089982 ps
CPU time 1 seconds
Started Jul 07 05:12:14 PM PDT 24
Finished Jul 07 05:12:16 PM PDT 24
Peak memory 204340 kb
Host smart-406a8caa-9826-48b4-beb3-7523e728a0b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627437204 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.627437204
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1678358983
Short name T229
Test name
Test status
Simulation time 20208327 ps
CPU time 0.67 seconds
Started Jul 07 05:12:13 PM PDT 24
Finished Jul 07 05:12:15 PM PDT 24
Peak memory 204192 kb
Host smart-8da8a642-37cf-4032-81d5-2a40936354f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678358983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1678358983
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1766103974
Short name T1534
Test name
Test status
Simulation time 27166296 ps
CPU time 0.69 seconds
Started Jul 07 05:12:12 PM PDT 24
Finished Jul 07 05:12:13 PM PDT 24
Peak memory 204228 kb
Host smart-b365a69a-6a0c-498a-98a6-4b55137154cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766103974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1766103974
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1881494357
Short name T1603
Test name
Test status
Simulation time 62571395 ps
CPU time 0.89 seconds
Started Jul 07 05:12:12 PM PDT 24
Finished Jul 07 05:12:13 PM PDT 24
Peak memory 204276 kb
Host smart-f8f5157b-a7de-4692-a173-623ac593743e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881494357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1881494357
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3127327498
Short name T148
Test name
Test status
Simulation time 396068744 ps
CPU time 2.14 seconds
Started Jul 07 05:12:08 PM PDT 24
Finished Jul 07 05:12:11 PM PDT 24
Peak memory 204544 kb
Host smart-330da825-f85d-4dc8-8b50-a4c19cfe28d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127327498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3127327498
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2894729626
Short name T1567
Test name
Test status
Simulation time 37637965 ps
CPU time 0.67 seconds
Started Jul 07 05:12:36 PM PDT 24
Finished Jul 07 05:12:38 PM PDT 24
Peak memory 204520 kb
Host smart-a2d125da-5aff-4207-9410-4eb38c2934a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894729626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2894729626
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3244846684
Short name T1554
Test name
Test status
Simulation time 50977338 ps
CPU time 0.7 seconds
Started Jul 07 05:12:36 PM PDT 24
Finished Jul 07 05:12:37 PM PDT 24
Peak memory 204220 kb
Host smart-b5fdd435-9253-4b4d-af41-f28b3ba297cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244846684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3244846684
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.3902968794
Short name T1626
Test name
Test status
Simulation time 60320137 ps
CPU time 0.66 seconds
Started Jul 07 05:12:34 PM PDT 24
Finished Jul 07 05:12:36 PM PDT 24
Peak memory 204264 kb
Host smart-bf4b6e95-9034-4f22-b3b5-91ff94ebd683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902968794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3902968794
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.2179448009
Short name T1572
Test name
Test status
Simulation time 32478766 ps
CPU time 0.68 seconds
Started Jul 07 05:12:34 PM PDT 24
Finished Jul 07 05:12:35 PM PDT 24
Peak memory 204232 kb
Host smart-1b71f029-dd56-4f69-807b-2120733e40f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179448009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2179448009
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.2055606694
Short name T1558
Test name
Test status
Simulation time 17025074 ps
CPU time 0.7 seconds
Started Jul 07 05:12:32 PM PDT 24
Finished Jul 07 05:12:33 PM PDT 24
Peak memory 204192 kb
Host smart-de78b871-1570-4c01-83a8-255ad2461e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055606694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2055606694
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2027691334
Short name T1585
Test name
Test status
Simulation time 27325588 ps
CPU time 0.71 seconds
Started Jul 07 05:12:34 PM PDT 24
Finished Jul 07 05:12:36 PM PDT 24
Peak memory 204208 kb
Host smart-c7b0ba12-0dcb-43ca-8b21-49bcb445e750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027691334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2027691334
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.300554056
Short name T1636
Test name
Test status
Simulation time 58198045 ps
CPU time 0.7 seconds
Started Jul 07 05:12:33 PM PDT 24
Finished Jul 07 05:12:34 PM PDT 24
Peak memory 204240 kb
Host smart-cce37d9b-0402-463c-b61a-49e6b87cb3d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300554056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.300554056
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.2525409577
Short name T1540
Test name
Test status
Simulation time 17732791 ps
CPU time 0.72 seconds
Started Jul 07 05:12:32 PM PDT 24
Finished Jul 07 05:12:33 PM PDT 24
Peak memory 204180 kb
Host smart-0e0abe88-1bee-4b0d-8353-5a6e1f6249b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525409577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2525409577
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.257275432
Short name T1570
Test name
Test status
Simulation time 24242032 ps
CPU time 0.69 seconds
Started Jul 07 05:12:37 PM PDT 24
Finished Jul 07 05:12:38 PM PDT 24
Peak memory 204236 kb
Host smart-e39f6430-02df-4a9a-81bd-125fa0911fa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257275432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.257275432
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.4021145594
Short name T1559
Test name
Test status
Simulation time 18440706 ps
CPU time 0.68 seconds
Started Jul 07 05:12:32 PM PDT 24
Finished Jul 07 05:12:33 PM PDT 24
Peak memory 204204 kb
Host smart-e777f105-dbd3-4ef6-a083-4e673f1dade9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021145594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.4021145594
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.274584567
Short name T1584
Test name
Test status
Simulation time 57833770 ps
CPU time 1.19 seconds
Started Jul 07 05:12:12 PM PDT 24
Finished Jul 07 05:12:13 PM PDT 24
Peak memory 204584 kb
Host smart-1c0a14a3-5d0d-4f7f-a7c1-8710c232f455
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274584567 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.274584567
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.945159836
Short name T1605
Test name
Test status
Simulation time 17936200 ps
CPU time 0.72 seconds
Started Jul 07 05:12:12 PM PDT 24
Finished Jul 07 05:12:14 PM PDT 24
Peak memory 204212 kb
Host smart-7f131343-d11d-4810-844b-be9c4894d789
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945159836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.945159836
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.3374388976
Short name T1619
Test name
Test status
Simulation time 41386894 ps
CPU time 0.67 seconds
Started Jul 07 05:12:13 PM PDT 24
Finished Jul 07 05:12:15 PM PDT 24
Peak memory 204180 kb
Host smart-864bda70-598f-40da-886d-b2005bc8e4f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374388976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3374388976
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1713963172
Short name T230
Test name
Test status
Simulation time 72103208 ps
CPU time 0.89 seconds
Started Jul 07 05:12:12 PM PDT 24
Finished Jul 07 05:12:14 PM PDT 24
Peak memory 204284 kb
Host smart-3cef7bc0-f665-40de-b8f4-f57d8eea63de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713963172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.1713963172
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3041860992
Short name T1583
Test name
Test status
Simulation time 56459879 ps
CPU time 1.19 seconds
Started Jul 07 05:12:13 PM PDT 24
Finished Jul 07 05:12:15 PM PDT 24
Peak memory 204580 kb
Host smart-81261d31-77ad-4597-a5a8-358b05eda190
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041860992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3041860992
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3053704002
Short name T152
Test name
Test status
Simulation time 301119523 ps
CPU time 1.45 seconds
Started Jul 07 05:12:12 PM PDT 24
Finished Jul 07 05:12:14 PM PDT 24
Peak memory 204536 kb
Host smart-55bffad1-944f-4ef3-b14e-a46edc0b82b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053704002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3053704002
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3235269248
Short name T1571
Test name
Test status
Simulation time 43777010 ps
CPU time 0.83 seconds
Started Jul 07 05:12:13 PM PDT 24
Finished Jul 07 05:12:14 PM PDT 24
Peak memory 204404 kb
Host smart-32bde0f7-60e7-47b2-8453-fbbaaf195993
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235269248 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3235269248
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3683791904
Short name T217
Test name
Test status
Simulation time 17987416 ps
CPU time 0.77 seconds
Started Jul 07 05:12:12 PM PDT 24
Finished Jul 07 05:12:14 PM PDT 24
Peak memory 204216 kb
Host smart-bb2b0eed-4d89-4739-b4e9-94e02d2be621
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683791904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3683791904
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1888186818
Short name T1595
Test name
Test status
Simulation time 43137858 ps
CPU time 0.7 seconds
Started Jul 07 05:12:13 PM PDT 24
Finished Jul 07 05:12:14 PM PDT 24
Peak memory 204260 kb
Host smart-cfbf9257-6120-4dc8-91f6-94bf97137b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888186818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1888186818
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4091843738
Short name T1616
Test name
Test status
Simulation time 42478114 ps
CPU time 0.96 seconds
Started Jul 07 05:12:13 PM PDT 24
Finished Jul 07 05:12:15 PM PDT 24
Peak memory 204324 kb
Host smart-3957e83e-9cde-417a-96a0-b8a62670f8a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091843738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.4091843738
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3785126550
Short name T1614
Test name
Test status
Simulation time 138851142 ps
CPU time 2.15 seconds
Started Jul 07 05:12:13 PM PDT 24
Finished Jul 07 05:12:16 PM PDT 24
Peak memory 204504 kb
Host smart-233b4cec-22c4-4de4-8f00-26edbd340a80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785126550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3785126550
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3987967977
Short name T264
Test name
Test status
Simulation time 103887361 ps
CPU time 1.98 seconds
Started Jul 07 05:12:12 PM PDT 24
Finished Jul 07 05:12:14 PM PDT 24
Peak memory 204528 kb
Host smart-b3472973-dcca-4920-8150-3231e12499e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987967977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3987967977
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2205903006
Short name T196
Test name
Test status
Simulation time 49513179 ps
CPU time 1.19 seconds
Started Jul 07 05:12:14 PM PDT 24
Finished Jul 07 05:12:17 PM PDT 24
Peak memory 212768 kb
Host smart-9d2c1434-0d42-4409-8508-3121b731fba5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205903006 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2205903006
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3625332002
Short name T222
Test name
Test status
Simulation time 40977137 ps
CPU time 0.76 seconds
Started Jul 07 05:12:13 PM PDT 24
Finished Jul 07 05:12:14 PM PDT 24
Peak memory 204236 kb
Host smart-e44c397c-fd93-4a94-ad55-35e1598e5dc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625332002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3625332002
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.2244932887
Short name T1549
Test name
Test status
Simulation time 24378452 ps
CPU time 0.7 seconds
Started Jul 07 05:12:14 PM PDT 24
Finished Jul 07 05:12:16 PM PDT 24
Peak memory 204096 kb
Host smart-bf464966-dd95-450d-9eff-8d75aa537065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244932887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2244932887
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3226889512
Short name T1627
Test name
Test status
Simulation time 524895290 ps
CPU time 0.93 seconds
Started Jul 07 05:12:17 PM PDT 24
Finished Jul 07 05:12:18 PM PDT 24
Peak memory 204280 kb
Host smart-414874e9-8b9d-45da-8e3b-911021255a37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226889512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3226889512
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.4178575713
Short name T1596
Test name
Test status
Simulation time 175986840 ps
CPU time 2.36 seconds
Started Jul 07 05:12:11 PM PDT 24
Finished Jul 07 05:12:14 PM PDT 24
Peak memory 204536 kb
Host smart-ff4b435e-df8a-415e-85c3-4e5ab218dea8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178575713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.4178575713
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2732485721
Short name T208
Test name
Test status
Simulation time 1915163334 ps
CPU time 2.3 seconds
Started Jul 07 05:12:16 PM PDT 24
Finished Jul 07 05:12:19 PM PDT 24
Peak memory 204484 kb
Host smart-b484f6a7-6b70-42f5-8217-8801c6794afa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732485721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2732485721
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1511187909
Short name T1555
Test name
Test status
Simulation time 26352343 ps
CPU time 1.07 seconds
Started Jul 07 05:12:16 PM PDT 24
Finished Jul 07 05:12:18 PM PDT 24
Peak memory 212748 kb
Host smart-a75e5c28-2d39-4089-a813-8e2cfb9facf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511187909 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1511187909
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.404592665
Short name T224
Test name
Test status
Simulation time 238324975 ps
CPU time 1.2 seconds
Started Jul 07 05:12:16 PM PDT 24
Finished Jul 07 05:12:18 PM PDT 24
Peak memory 204208 kb
Host smart-0c357c27-ea1a-4b73-b259-ce9a00441bda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404592665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.404592665
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.3609192037
Short name T1532
Test name
Test status
Simulation time 17268609 ps
CPU time 0.7 seconds
Started Jul 07 05:12:17 PM PDT 24
Finished Jul 07 05:12:19 PM PDT 24
Peak memory 204180 kb
Host smart-de379c97-5bf8-4c11-80cf-860d10ecee20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609192037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3609192037
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4136340580
Short name T1608
Test name
Test status
Simulation time 153975838 ps
CPU time 1.22 seconds
Started Jul 07 05:12:20 PM PDT 24
Finished Jul 07 05:12:22 PM PDT 24
Peak memory 204452 kb
Host smart-562dba6d-9aa2-4b41-8fd9-a38c3301dd7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136340580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.4136340580
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2092767862
Short name T149
Test name
Test status
Simulation time 398255921 ps
CPU time 1.88 seconds
Started Jul 07 05:12:18 PM PDT 24
Finished Jul 07 05:12:20 PM PDT 24
Peak memory 204520 kb
Host smart-40e49cec-f886-4d54-ad81-208fdc8e6077
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092767862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2092767862
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.4158099199
Short name T204
Test name
Test status
Simulation time 909155788 ps
CPU time 2.51 seconds
Started Jul 07 05:12:19 PM PDT 24
Finished Jul 07 05:12:23 PM PDT 24
Peak memory 204540 kb
Host smart-10294a34-21e7-4acd-85bc-d7d1ee8f4289
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158099199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.4158099199
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2052469342
Short name T150
Test name
Test status
Simulation time 64809934 ps
CPU time 1.01 seconds
Started Jul 07 05:12:18 PM PDT 24
Finished Jul 07 05:12:19 PM PDT 24
Peak memory 204336 kb
Host smart-2f05cda4-c820-475a-8b5c-d66e530e107f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052469342 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2052469342
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.637658000
Short name T1639
Test name
Test status
Simulation time 47013644 ps
CPU time 0.77 seconds
Started Jul 07 05:12:19 PM PDT 24
Finished Jul 07 05:12:21 PM PDT 24
Peak memory 204236 kb
Host smart-02f4c4eb-c17f-4e4e-80a6-cd305804d0e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637658000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.637658000
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.3680779566
Short name T1574
Test name
Test status
Simulation time 30656948 ps
CPU time 0.65 seconds
Started Jul 07 05:12:16 PM PDT 24
Finished Jul 07 05:12:17 PM PDT 24
Peak memory 204220 kb
Host smart-a1ac9e38-e5e1-416c-90a9-7cf677636dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680779566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3680779566
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2162558070
Short name T1563
Test name
Test status
Simulation time 163353881 ps
CPU time 1.16 seconds
Started Jul 07 05:12:19 PM PDT 24
Finished Jul 07 05:12:21 PM PDT 24
Peak memory 204532 kb
Host smart-f263c7cf-cc61-4bbf-a240-eabfd64559dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162558070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.2162558070
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1738317463
Short name T1598
Test name
Test status
Simulation time 2204502504 ps
CPU time 2.27 seconds
Started Jul 07 05:12:16 PM PDT 24
Finished Jul 07 05:12:19 PM PDT 24
Peak memory 204576 kb
Host smart-4c65f748-8c17-4745-98ed-49d334da46ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738317463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1738317463
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.83514669
Short name T205
Test name
Test status
Simulation time 89238566 ps
CPU time 1.47 seconds
Started Jul 07 05:12:20 PM PDT 24
Finished Jul 07 05:12:22 PM PDT 24
Peak memory 204492 kb
Host smart-acb37a65-67de-4aab-a7c7-7beff5dac292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83514669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.83514669
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.201090868
Short name T1472
Test name
Test status
Simulation time 16146302 ps
CPU time 0.67 seconds
Started Jul 07 05:32:58 PM PDT 24
Finished Jul 07 05:32:59 PM PDT 24
Peak memory 204588 kb
Host smart-70d219be-440a-47a3-9ce3-a871bb0f44c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201090868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.201090868
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2023109968
Short name T172
Test name
Test status
Simulation time 2223775420 ps
CPU time 4.61 seconds
Started Jul 07 05:33:02 PM PDT 24
Finished Jul 07 05:33:07 PM PDT 24
Peak memory 233884 kb
Host smart-44cf167a-792d-43af-a181-a17ec704fda8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023109968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2023109968
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3316320809
Short name T279
Test name
Test status
Simulation time 7999963891 ps
CPU time 44.22 seconds
Started Jul 07 05:32:52 PM PDT 24
Finished Jul 07 05:33:36 PM PDT 24
Peak memory 308628 kb
Host smart-b9525ed0-ea01-4c77-adfc-53c7b69d21fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316320809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3316320809
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.1829788603
Short name T1433
Test name
Test status
Simulation time 4880854132 ps
CPU time 180.13 seconds
Started Jul 07 05:32:54 PM PDT 24
Finished Jul 07 05:35:55 PM PDT 24
Peak memory 764784 kb
Host smart-81ed2dcd-dc50-45d9-8b11-a0dd0de306f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829788603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.1829788603
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3121860789
Short name T1511
Test name
Test status
Simulation time 215308599 ps
CPU time 1.12 seconds
Started Jul 07 05:33:02 PM PDT 24
Finished Jul 07 05:33:04 PM PDT 24
Peak memory 204752 kb
Host smart-6b68cef5-0c39-458a-84e4-b1bf3e93911c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121860789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.3121860789
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1889151224
Short name T1247
Test name
Test status
Simulation time 811891527 ps
CPU time 7.26 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:33:09 PM PDT 24
Peak memory 255188 kb
Host smart-01b52079-dee5-46bd-b67d-50f5e38dfb97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889151224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1889151224
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.981640305
Short name T1249
Test name
Test status
Simulation time 4375922973 ps
CPU time 312.72 seconds
Started Jul 07 05:32:53 PM PDT 24
Finished Jul 07 05:38:06 PM PDT 24
Peak memory 1259812 kb
Host smart-34d99a5c-86b2-42fd-931a-3b09f4544e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981640305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.981640305
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.7872400
Short name T1188
Test name
Test status
Simulation time 426081231 ps
CPU time 9.02 seconds
Started Jul 07 05:32:57 PM PDT 24
Finished Jul 07 05:33:07 PM PDT 24
Peak memory 205048 kb
Host smart-3079e756-422c-41e9-87f4-3fdee33dd08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7872400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.7872400
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_perf.743292151
Short name T1213
Test name
Test status
Simulation time 2561495557 ps
CPU time 35.47 seconds
Started Jul 07 05:32:55 PM PDT 24
Finished Jul 07 05:33:31 PM PDT 24
Peak memory 205608 kb
Host smart-191de367-c7ff-46c8-a76d-aba6d1d99ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743292151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.743292151
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.623763837
Short name T531
Test name
Test status
Simulation time 2561558808 ps
CPU time 64.9 seconds
Started Jul 07 05:32:55 PM PDT 24
Finished Jul 07 05:34:00 PM PDT 24
Peak memory 505804 kb
Host smart-678174f6-6eef-497a-b4ef-d4f396e07c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623763837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.623763837
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.4100727705
Short name T320
Test name
Test status
Simulation time 4814938759 ps
CPU time 58.77 seconds
Started Jul 07 05:32:52 PM PDT 24
Finished Jul 07 05:33:51 PM PDT 24
Peak memory 336000 kb
Host smart-d783b09f-6081-4b48-abd6-84e30a8a98a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100727705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.4100727705
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.2999525800
Short name T276
Test name
Test status
Simulation time 22518002477 ps
CPU time 408.8 seconds
Started Jul 07 05:32:54 PM PDT 24
Finished Jul 07 05:39:43 PM PDT 24
Peak memory 1263536 kb
Host smart-a1aa8a5d-6b17-4ead-b26f-532365e3f430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999525800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.2999525800
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.548995044
Short name T1182
Test name
Test status
Simulation time 739578315 ps
CPU time 32.65 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:33:35 PM PDT 24
Peak memory 213196 kb
Host smart-ffb574a7-242f-447f-b2cf-444cfe5b4fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548995044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.548995044
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.3515281272
Short name T1440
Test name
Test status
Simulation time 1702290722 ps
CPU time 4.38 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:33:06 PM PDT 24
Peak memory 213156 kb
Host smart-303f4972-1b54-4e9b-af9f-81634b7c71cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515281272 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3515281272
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.1129255521
Short name T852
Test name
Test status
Simulation time 181853374 ps
CPU time 0.81 seconds
Started Jul 07 05:32:57 PM PDT 24
Finished Jul 07 05:32:58 PM PDT 24
Peak memory 204672 kb
Host smart-8f833db5-e4c8-4297-80e9-2ab554131d95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129255521 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.1129255521
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.2091759
Short name T730
Test name
Test status
Simulation time 210528655 ps
CPU time 1.26 seconds
Started Jul 07 05:32:57 PM PDT 24
Finished Jul 07 05:32:58 PM PDT 24
Peak memory 205000 kb
Host smart-33087658-2caf-49c6-aead-0a9a79c69363
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091759 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_target_fifo_reset_tx.2091759
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.2397988669
Short name T1224
Test name
Test status
Simulation time 1804322547 ps
CPU time 2.42 seconds
Started Jul 07 05:32:58 PM PDT 24
Finished Jul 07 05:33:01 PM PDT 24
Peak memory 205060 kb
Host smart-86eede0d-800a-43ee-99b1-af83e8dca284
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397988669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.2397988669
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.738065300
Short name T831
Test name
Test status
Simulation time 658446912 ps
CPU time 1.24 seconds
Started Jul 07 05:32:52 PM PDT 24
Finished Jul 07 05:32:54 PM PDT 24
Peak memory 204800 kb
Host smart-f75c12b2-e2c6-4629-a3ee-9b29e38c31d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738065300 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.738065300
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.1722628853
Short name T15
Test name
Test status
Simulation time 2313343744 ps
CPU time 12.81 seconds
Started Jul 07 05:32:51 PM PDT 24
Finished Jul 07 05:33:05 PM PDT 24
Peak memory 213748 kb
Host smart-4f2bb65d-f880-4a73-8e11-5b476539a253
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722628853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.1722628853
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1529807579
Short name T310
Test name
Test status
Simulation time 680415034 ps
CPU time 4.07 seconds
Started Jul 07 05:32:54 PM PDT 24
Finished Jul 07 05:32:58 PM PDT 24
Peak memory 205008 kb
Host smart-1e6c8734-5efa-4735-8cde-8ef6c569dcca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529807579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1529807579
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.619008119
Short name T89
Test name
Test status
Simulation time 9188494298 ps
CPU time 6.22 seconds
Started Jul 07 05:32:56 PM PDT 24
Finished Jul 07 05:33:02 PM PDT 24
Peak memory 217424 kb
Host smart-f67b4158-5e22-41ce-affa-cafb23b47fda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619008119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.619008119
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.931706102
Short name T157
Test name
Test status
Simulation time 18861720627 ps
CPU time 48.07 seconds
Started Jul 07 05:33:36 PM PDT 24
Finished Jul 07 05:34:24 PM PDT 24
Peak memory 781792 kb
Host smart-047fafae-5edb-4097-853f-c32ed35939ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931706102 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.931706102
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.3868389023
Short name T889
Test name
Test status
Simulation time 1319924903 ps
CPU time 9.98 seconds
Started Jul 07 05:32:49 PM PDT 24
Finished Jul 07 05:32:59 PM PDT 24
Peak memory 205048 kb
Host smart-f7d43eb9-c46c-4b25-9294-e4772e29d630
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868389023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.3868389023
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.2353771720
Short name T1171
Test name
Test status
Simulation time 29649253139 ps
CPU time 31.03 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:33:33 PM PDT 24
Peak memory 652372 kb
Host smart-5c5030aa-d49b-49b5-9427-3bcc18a20e2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353771720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.2353771720
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.4133361524
Short name T130
Test name
Test status
Simulation time 2180448211 ps
CPU time 7.36 seconds
Started Jul 07 05:32:56 PM PDT 24
Finished Jul 07 05:33:04 PM PDT 24
Peak memory 287712 kb
Host smart-1c242f57-182c-4ed8-ad55-b0c470fb23a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133361524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.4133361524
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.372383895
Short name T454
Test name
Test status
Simulation time 5081973488 ps
CPU time 7.79 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:33:10 PM PDT 24
Peak memory 219588 kb
Host smart-27c3effa-99c4-4433-98dd-bc296f684a23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372383895 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_timeout.372383895
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.1311232028
Short name T515
Test name
Test status
Simulation time 511099454 ps
CPU time 6.99 seconds
Started Jul 07 05:32:54 PM PDT 24
Finished Jul 07 05:33:02 PM PDT 24
Peak memory 204968 kb
Host smart-a299fbb3-3f97-4c8f-9e87-cdc70b2d7c4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311232028 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.1311232028
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2190006100
Short name T466
Test name
Test status
Simulation time 16624840 ps
CPU time 0.62 seconds
Started Jul 07 05:33:05 PM PDT 24
Finished Jul 07 05:33:06 PM PDT 24
Peak memory 204608 kb
Host smart-53e3a993-3b65-4d6f-b0ba-1116e49899a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190006100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2190006100
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.1923861622
Short name T570
Test name
Test status
Simulation time 81106650 ps
CPU time 1.97 seconds
Started Jul 07 05:33:00 PM PDT 24
Finished Jul 07 05:33:02 PM PDT 24
Peak memory 213584 kb
Host smart-04bde540-58e7-43eb-87cd-b813c967ce94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923861622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.1923861622
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.1288893873
Short name T1309
Test name
Test status
Simulation time 1708772897 ps
CPU time 4.8 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:33:06 PM PDT 24
Peak memory 249048 kb
Host smart-978590be-40a6-4caf-ae5f-8e013037f908
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288893873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.1288893873
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.460860459
Short name T1519
Test name
Test status
Simulation time 1446964560 ps
CPU time 44.94 seconds
Started Jul 07 05:32:59 PM PDT 24
Finished Jul 07 05:33:45 PM PDT 24
Peak memory 554852 kb
Host smart-eeda39f8-1375-4913-b40c-c6064202f825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460860459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.460860459
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.4161308471
Short name T581
Test name
Test status
Simulation time 4114628094 ps
CPU time 71.56 seconds
Started Jul 07 05:32:57 PM PDT 24
Finished Jul 07 05:34:09 PM PDT 24
Peak memory 687004 kb
Host smart-bc71cb23-b65a-4c5e-b7a9-8937b0c4ceb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161308471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.4161308471
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.1095249900
Short name T931
Test name
Test status
Simulation time 256484842 ps
CPU time 7.92 seconds
Started Jul 07 05:33:00 PM PDT 24
Finished Jul 07 05:33:09 PM PDT 24
Peak memory 228912 kb
Host smart-a6afe7f7-e873-4eeb-b1e6-674658bf5390
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095249900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
1095249900
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.117236655
Short name T768
Test name
Test status
Simulation time 1644717184 ps
CPU time 31.05 seconds
Started Jul 07 05:33:07 PM PDT 24
Finished Jul 07 05:33:39 PM PDT 24
Peak memory 366932 kb
Host smart-fd8b2d8a-b54d-497f-a40b-9f0b86a59b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117236655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.117236655
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.2782438820
Short name T136
Test name
Test status
Simulation time 99755731 ps
CPU time 0.72 seconds
Started Jul 07 05:32:57 PM PDT 24
Finished Jul 07 05:32:58 PM PDT 24
Peak memory 204708 kb
Host smart-9a863fff-308b-40c4-ae43-f89a03afaff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782438820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2782438820
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.430084769
Short name T918
Test name
Test status
Simulation time 7765132030 ps
CPU time 88.35 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:34:30 PM PDT 24
Peak memory 809952 kb
Host smart-94f73907-d0ca-43e5-85d5-d82c042805c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430084769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.430084769
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.2777322351
Short name T725
Test name
Test status
Simulation time 2909290703 ps
CPU time 16.24 seconds
Started Jul 07 05:33:00 PM PDT 24
Finished Jul 07 05:33:17 PM PDT 24
Peak memory 377124 kb
Host smart-1a3d42c2-f849-47b6-bf58-e7a2adaa78c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777322351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.2777322351
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.4114563262
Short name T1090
Test name
Test status
Simulation time 7297370735 ps
CPU time 79.55 seconds
Started Jul 07 05:32:58 PM PDT 24
Finished Jul 07 05:34:18 PM PDT 24
Peak memory 341180 kb
Host smart-f7bf5dfd-bf40-4320-af80-e55f82543ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114563262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.4114563262
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.904634640
Short name T1034
Test name
Test status
Simulation time 83146866925 ps
CPU time 1138.77 seconds
Started Jul 07 05:33:00 PM PDT 24
Finished Jul 07 05:52:00 PM PDT 24
Peak memory 3077968 kb
Host smart-0fc06264-4e2c-4da5-a28c-8f31c7fbdbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904634640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.904634640
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.30962913
Short name T954
Test name
Test status
Simulation time 533141027 ps
CPU time 25.88 seconds
Started Jul 07 05:32:58 PM PDT 24
Finished Jul 07 05:33:24 PM PDT 24
Peak memory 213228 kb
Host smart-efb1da12-7dfc-4305-b85e-60560bcb8526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30962913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.30962913
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.723749459
Short name T185
Test name
Test status
Simulation time 75058282 ps
CPU time 0.86 seconds
Started Jul 07 05:33:02 PM PDT 24
Finished Jul 07 05:33:04 PM PDT 24
Peak memory 222112 kb
Host smart-de56de7f-d75c-4a9b-b669-dac93b976fa6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723749459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.723749459
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.2342787738
Short name T792
Test name
Test status
Simulation time 3161478419 ps
CPU time 3.65 seconds
Started Jul 07 05:32:59 PM PDT 24
Finished Jul 07 05:33:03 PM PDT 24
Peak memory 205084 kb
Host smart-a4dcadc4-ed04-470f-89df-a5c7fc95866b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342787738 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.2342787738
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3080624016
Short name T517
Test name
Test status
Simulation time 163823248 ps
CPU time 1.15 seconds
Started Jul 07 05:33:02 PM PDT 24
Finished Jul 07 05:33:04 PM PDT 24
Peak memory 204804 kb
Host smart-82a24e9a-ad35-4d73-b3b2-4ee10680f80d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080624016 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3080624016
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.373233224
Short name T1118
Test name
Test status
Simulation time 305317996 ps
CPU time 0.9 seconds
Started Jul 07 05:32:59 PM PDT 24
Finished Jul 07 05:33:01 PM PDT 24
Peak memory 204768 kb
Host smart-b68e1acf-661f-43e4-902b-1dda3ad728a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373233224 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_tx.373233224
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.653198226
Short name T1407
Test name
Test status
Simulation time 1990069940 ps
CPU time 2.62 seconds
Started Jul 07 05:33:02 PM PDT 24
Finished Jul 07 05:33:05 PM PDT 24
Peak memory 205008 kb
Host smart-063cea4d-040f-446d-8696-81468cea3df8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653198226 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.653198226
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.2792841080
Short name T545
Test name
Test status
Simulation time 258997435 ps
CPU time 1.28 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:33:03 PM PDT 24
Peak memory 204680 kb
Host smart-5e573784-09a2-49c1-8b08-6a73140c3ff2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792841080 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.2792841080
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.1863201378
Short name T1076
Test name
Test status
Simulation time 2229554019 ps
CPU time 5.74 seconds
Started Jul 07 05:32:59 PM PDT 24
Finished Jul 07 05:33:05 PM PDT 24
Peak memory 204972 kb
Host smart-086f8f80-83db-4050-9e00-e2a71b075205
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863201378 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.1863201378
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.3616848075
Short name T1394
Test name
Test status
Simulation time 21751127899 ps
CPU time 59.29 seconds
Started Jul 07 05:32:58 PM PDT 24
Finished Jul 07 05:33:58 PM PDT 24
Peak memory 1228264 kb
Host smart-f36acae5-f3fe-4386-947c-9090f29a093b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616848075 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3616848075
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1763941235
Short name T575
Test name
Test status
Simulation time 2493431449 ps
CPU time 11.03 seconds
Started Jul 07 05:32:58 PM PDT 24
Finished Jul 07 05:33:10 PM PDT 24
Peak memory 205052 kb
Host smart-1d78fd8a-1895-4e13-a854-8306363322e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763941235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1763941235
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.3759740064
Short name T851
Test name
Test status
Simulation time 367078121 ps
CPU time 16.12 seconds
Started Jul 07 05:32:58 PM PDT 24
Finished Jul 07 05:33:15 PM PDT 24
Peak memory 205276 kb
Host smart-e9cb12f8-3154-4b39-ba4b-e99779d25ae8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759740064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.3759740064
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.812077974
Short name T770
Test name
Test status
Simulation time 68642939242 ps
CPU time 848.29 seconds
Started Jul 07 05:33:00 PM PDT 24
Finished Jul 07 05:47:09 PM PDT 24
Peak memory 6289264 kb
Host smart-9f3081bd-a029-4e74-b374-a5c4a165f78a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812077974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_wr.812077974
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.3909406047
Short name T1110
Test name
Test status
Simulation time 3408719580 ps
CPU time 7.19 seconds
Started Jul 07 05:32:57 PM PDT 24
Finished Jul 07 05:33:04 PM PDT 24
Peak memory 294108 kb
Host smart-238b18f1-d25d-4a51-85a2-3e73c6f306d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909406047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.3909406047
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.2686143849
Short name T374
Test name
Test status
Simulation time 360309275 ps
CPU time 4.83 seconds
Started Jul 07 05:33:05 PM PDT 24
Finished Jul 07 05:33:10 PM PDT 24
Peak memory 204992 kb
Host smart-ad4209ca-053c-4f08-aff3-53726d8ec680
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686143849 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.2686143849
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_alert_test.2239801500
Short name T838
Test name
Test status
Simulation time 18958384 ps
CPU time 0.68 seconds
Started Jul 07 05:33:54 PM PDT 24
Finished Jul 07 05:33:56 PM PDT 24
Peak memory 204608 kb
Host smart-a38a05ac-32f3-4e93-ba57-e5ff905ab976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239801500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2239801500
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2566715788
Short name T1
Test name
Test status
Simulation time 66581028 ps
CPU time 1.43 seconds
Started Jul 07 05:33:47 PM PDT 24
Finished Jul 07 05:33:49 PM PDT 24
Peak memory 217652 kb
Host smart-ef45de75-022f-40a3-9c6c-9af39c5e18ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566715788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2566715788
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.1893382666
Short name T1404
Test name
Test status
Simulation time 788921185 ps
CPU time 12.02 seconds
Started Jul 07 05:33:49 PM PDT 24
Finished Jul 07 05:34:01 PM PDT 24
Peak memory 252664 kb
Host smart-dc9ab937-f0cc-4201-ba41-d133861fafbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893382666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.1893382666
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.91047149
Short name T1469
Test name
Test status
Simulation time 1885531014 ps
CPU time 47.07 seconds
Started Jul 07 05:33:50 PM PDT 24
Finished Jul 07 05:34:37 PM PDT 24
Peak memory 484896 kb
Host smart-b0a13b47-b0d0-463f-97b3-573732cf83fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91047149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.91047149
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.2244090960
Short name T428
Test name
Test status
Simulation time 2469934773 ps
CPU time 88.32 seconds
Started Jul 07 05:33:48 PM PDT 24
Finished Jul 07 05:35:17 PM PDT 24
Peak memory 794792 kb
Host smart-04d159de-9a30-4d45-8147-6d91e7a855ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244090960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.2244090960
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.749040573
Short name T1186
Test name
Test status
Simulation time 110443327 ps
CPU time 1.14 seconds
Started Jul 07 05:33:50 PM PDT 24
Finished Jul 07 05:33:51 PM PDT 24
Peak memory 204752 kb
Host smart-6309553c-13af-4e57-be5e-472040d87e64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749040573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fm
t.749040573
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.2050404297
Short name T965
Test name
Test status
Simulation time 132828338 ps
CPU time 3.13 seconds
Started Jul 07 05:33:46 PM PDT 24
Finished Jul 07 05:33:49 PM PDT 24
Peak memory 204976 kb
Host smart-1b271c64-472c-4167-a34d-e2a8cd082175
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050404297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.2050404297
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.121288521
Short name T776
Test name
Test status
Simulation time 4232045437 ps
CPU time 127.65 seconds
Started Jul 07 05:33:48 PM PDT 24
Finished Jul 07 05:35:56 PM PDT 24
Peak memory 1230000 kb
Host smart-29c5c257-aaff-4d6d-a4ce-5b4022019a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121288521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.121288521
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.522857878
Short name T405
Test name
Test status
Simulation time 2111506851 ps
CPU time 21.67 seconds
Started Jul 07 05:33:51 PM PDT 24
Finished Jul 07 05:34:13 PM PDT 24
Peak memory 205056 kb
Host smart-b11d0065-8244-4ee3-9368-0cb15f831f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522857878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.522857878
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.1680133338
Short name T1530
Test name
Test status
Simulation time 20772209146 ps
CPU time 38.21 seconds
Started Jul 07 05:33:48 PM PDT 24
Finished Jul 07 05:34:27 PM PDT 24
Peak memory 345740 kb
Host smart-4bbc859e-24f8-4a9a-8911-cb15e0176eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680133338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.1680133338
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.278362041
Short name T731
Test name
Test status
Simulation time 16426907 ps
CPU time 0.66 seconds
Started Jul 07 05:33:47 PM PDT 24
Finished Jul 07 05:33:48 PM PDT 24
Peak memory 204700 kb
Host smart-57a6acfc-3e57-4c80-b1b8-6356f11647d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278362041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.278362041
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.918879886
Short name T1172
Test name
Test status
Simulation time 52693834191 ps
CPU time 1930.23 seconds
Started Jul 07 05:33:49 PM PDT 24
Finished Jul 07 06:06:00 PM PDT 24
Peak memory 589936 kb
Host smart-c5f295cc-da1c-4dd6-9913-9206bcd06c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918879886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.918879886
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.3363720047
Short name T1372
Test name
Test status
Simulation time 79566182 ps
CPU time 1.53 seconds
Started Jul 07 05:33:46 PM PDT 24
Finished Jul 07 05:33:48 PM PDT 24
Peak memory 206532 kb
Host smart-39a23203-7cca-4676-ae5b-6386676ebaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363720047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.3363720047
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.3365565692
Short name T722
Test name
Test status
Simulation time 1085801582 ps
CPU time 54.69 seconds
Started Jul 07 05:33:46 PM PDT 24
Finished Jul 07 05:34:41 PM PDT 24
Peak memory 359528 kb
Host smart-f424ea10-32d7-440e-8b33-daee437f9fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365565692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3365565692
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.1599717947
Short name T280
Test name
Test status
Simulation time 2658347915 ps
CPU time 6.87 seconds
Started Jul 07 05:33:48 PM PDT 24
Finished Jul 07 05:33:55 PM PDT 24
Peak memory 213228 kb
Host smart-4cfb466a-9db1-477f-bcfb-42df9c6b8c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599717947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.1599717947
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2312570968
Short name T1352
Test name
Test status
Simulation time 199225610 ps
CPU time 1.23 seconds
Started Jul 07 05:33:51 PM PDT 24
Finished Jul 07 05:33:52 PM PDT 24
Peak memory 204712 kb
Host smart-c421b43a-9364-496c-b8aa-c75c643a9d99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312570968 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2312570968
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1855471591
Short name T690
Test name
Test status
Simulation time 239094272 ps
CPU time 1.44 seconds
Started Jul 07 05:33:50 PM PDT 24
Finished Jul 07 05:33:52 PM PDT 24
Peak memory 204868 kb
Host smart-38e5c090-3c5e-4080-9ef5-0949b10c5ce6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855471591 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1855471591
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.3368338129
Short name T580
Test name
Test status
Simulation time 439999545 ps
CPU time 1.39 seconds
Started Jul 07 05:33:49 PM PDT 24
Finished Jul 07 05:33:51 PM PDT 24
Peak memory 204720 kb
Host smart-33996d26-44a7-4705-bf14-35d867ac20b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368338129 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.3368338129
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.3108916480
Short name T461
Test name
Test status
Simulation time 76558083 ps
CPU time 0.96 seconds
Started Jul 07 05:33:50 PM PDT 24
Finished Jul 07 05:33:52 PM PDT 24
Peak memory 204784 kb
Host smart-fc16ad3c-e76b-4f28-baaa-27a510e2b363
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108916480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.3108916480
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.2683743264
Short name T1039
Test name
Test status
Simulation time 2028540586 ps
CPU time 3.62 seconds
Started Jul 07 05:33:52 PM PDT 24
Finished Jul 07 05:33:56 PM PDT 24
Peak memory 205128 kb
Host smart-a5d1852a-bc59-4ee8-83df-261eb63e2096
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683743264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.2683743264
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.4170303775
Short name T354
Test name
Test status
Simulation time 1346079626 ps
CPU time 7.15 seconds
Started Jul 07 05:33:50 PM PDT 24
Finished Jul 07 05:33:58 PM PDT 24
Peak memory 221212 kb
Host smart-84ceb9c8-9c25-4767-967a-fcf06d5a3813
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170303775 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.4170303775
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.321706618
Short name T331
Test name
Test status
Simulation time 2223441838 ps
CPU time 5.12 seconds
Started Jul 07 05:33:56 PM PDT 24
Finished Jul 07 05:34:02 PM PDT 24
Peak memory 204844 kb
Host smart-95be0645-735a-48cd-9d2d-0a53caf3f8e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321706618 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.321706618
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.3697997288
Short name T1238
Test name
Test status
Simulation time 5121709208 ps
CPU time 49.59 seconds
Started Jul 07 05:33:48 PM PDT 24
Finished Jul 07 05:34:38 PM PDT 24
Peak memory 205012 kb
Host smart-5149e2e4-3f3f-40ea-8729-fc90b9cb39ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697997288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.3697997288
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3379744518
Short name T1310
Test name
Test status
Simulation time 1561408112 ps
CPU time 63.5 seconds
Started Jul 07 05:33:46 PM PDT 24
Finished Jul 07 05:34:49 PM PDT 24
Peak memory 205844 kb
Host smart-1fe92013-d415-4245-ab16-0d772a2c0328
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379744518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3379744518
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.1542937709
Short name T1444
Test name
Test status
Simulation time 13417225299 ps
CPU time 14.23 seconds
Started Jul 07 05:33:47 PM PDT 24
Finished Jul 07 05:34:02 PM PDT 24
Peak memory 205024 kb
Host smart-81fa1269-da8b-4bda-839d-dcfee60d3d4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542937709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.1542937709
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.1346975918
Short name T1011
Test name
Test status
Simulation time 926674307 ps
CPU time 14.81 seconds
Started Jul 07 05:33:50 PM PDT 24
Finished Jul 07 05:34:05 PM PDT 24
Peak memory 372100 kb
Host smart-9dedf4a4-230e-42a1-87f8-77e530f13b00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346975918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.1346975918
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.1031447891
Short name T663
Test name
Test status
Simulation time 8653787626 ps
CPU time 6.5 seconds
Started Jul 07 05:33:49 PM PDT 24
Finished Jul 07 05:33:55 PM PDT 24
Peak memory 213192 kb
Host smart-70a08db8-c165-4e3f-9e74-a51c0e91c22a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031447891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.1031447891
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.2519445497
Short name T804
Test name
Test status
Simulation time 306025065 ps
CPU time 4.22 seconds
Started Jul 07 05:33:56 PM PDT 24
Finished Jul 07 05:34:00 PM PDT 24
Peak memory 205000 kb
Host smart-6c060b0c-6ac3-4f59-b0c5-5bc403a0c3fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519445497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.2519445497
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.3986882864
Short name T1062
Test name
Test status
Simulation time 16437580 ps
CPU time 0.64 seconds
Started Jul 07 05:34:06 PM PDT 24
Finished Jul 07 05:34:07 PM PDT 24
Peak memory 204600 kb
Host smart-1affe811-abbb-48a1-bc11-c89bc6c815a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986882864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3986882864
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.971887829
Short name T653
Test name
Test status
Simulation time 1583179327 ps
CPU time 2.84 seconds
Started Jul 07 05:33:56 PM PDT 24
Finished Jul 07 05:33:59 PM PDT 24
Peak memory 218760 kb
Host smart-e071b5f1-f4da-4950-bdcf-a24c18dfce1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971887829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.971887829
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.2971577124
Short name T1279
Test name
Test status
Simulation time 819410607 ps
CPU time 21.8 seconds
Started Jul 07 05:33:56 PM PDT 24
Finished Jul 07 05:34:19 PM PDT 24
Peak memory 293320 kb
Host smart-930f67be-7bb4-4ee2-9621-5803878cd978
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971577124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.2971577124
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.611220847
Short name T330
Test name
Test status
Simulation time 8377690111 ps
CPU time 77.28 seconds
Started Jul 07 05:33:56 PM PDT 24
Finished Jul 07 05:35:14 PM PDT 24
Peak memory 727376 kb
Host smart-75a0d127-b9e3-4e21-a95e-48dcafab7b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611220847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.611220847
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.3518078775
Short name T1286
Test name
Test status
Simulation time 5026565361 ps
CPU time 87.95 seconds
Started Jul 07 05:34:08 PM PDT 24
Finished Jul 07 05:35:37 PM PDT 24
Peak memory 477304 kb
Host smart-9f1873c8-00a4-47fd-af8e-ed414dccfec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518078775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3518078775
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1532681170
Short name T1423
Test name
Test status
Simulation time 126567034 ps
CPU time 1.19 seconds
Started Jul 07 05:33:57 PM PDT 24
Finished Jul 07 05:33:59 PM PDT 24
Peak memory 204892 kb
Host smart-4639bc2d-9c82-4844-8a2c-d5cc4983cc2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532681170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.1532681170
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3669637482
Short name T421
Test name
Test status
Simulation time 354707260 ps
CPU time 6.39 seconds
Started Jul 07 05:33:54 PM PDT 24
Finished Jul 07 05:34:00 PM PDT 24
Peak memory 245852 kb
Host smart-0399f4a3-320d-4ead-b290-1d51811fd40c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669637482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3669637482
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.1225411355
Short name T1483
Test name
Test status
Simulation time 4549892813 ps
CPU time 109.22 seconds
Started Jul 07 05:33:55 PM PDT 24
Finished Jul 07 05:35:45 PM PDT 24
Peak memory 1258940 kb
Host smart-82773533-8a32-4289-9a79-6ade8d2d90b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225411355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1225411355
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.1121911556
Short name T821
Test name
Test status
Simulation time 6820096538 ps
CPU time 7.05 seconds
Started Jul 07 05:33:58 PM PDT 24
Finished Jul 07 05:34:06 PM PDT 24
Peak memory 204948 kb
Host smart-51833e09-427d-4a8c-834b-337b23511a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121911556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.1121911556
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.3230885194
Short name T1109
Test name
Test status
Simulation time 1794851301 ps
CPU time 36.51 seconds
Started Jul 07 05:33:58 PM PDT 24
Finished Jul 07 05:34:35 PM PDT 24
Peak memory 376420 kb
Host smart-aa2eb477-9453-4f6d-bf0f-e93abacffbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230885194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3230885194
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.4196838315
Short name T10
Test name
Test status
Simulation time 22288836 ps
CPU time 0.72 seconds
Started Jul 07 05:33:55 PM PDT 24
Finished Jul 07 05:33:57 PM PDT 24
Peak memory 204672 kb
Host smart-3fcae28f-081b-427a-b379-5611f67b3804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196838315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.4196838315
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.2613468803
Short name T1242
Test name
Test status
Simulation time 841313836 ps
CPU time 10.43 seconds
Started Jul 07 05:33:56 PM PDT 24
Finished Jul 07 05:34:07 PM PDT 24
Peak memory 204964 kb
Host smart-5fc19f65-ebf8-4250-9bb8-2be1b5893473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613468803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2613468803
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.748715583
Short name T914
Test name
Test status
Simulation time 24279989013 ps
CPU time 1876.86 seconds
Started Jul 07 05:33:55 PM PDT 24
Finished Jul 07 06:05:13 PM PDT 24
Peak memory 3972848 kb
Host smart-cbda68cc-17e9-49e0-a6c7-b6d5156649a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748715583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.748715583
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3253187803
Short name T1414
Test name
Test status
Simulation time 4004667542 ps
CPU time 94.94 seconds
Started Jul 07 05:33:58 PM PDT 24
Finished Jul 07 05:35:34 PM PDT 24
Peak memory 326668 kb
Host smart-4bc77185-0077-4de9-96bf-467ff518a86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253187803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3253187803
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.2074983619
Short name T667
Test name
Test status
Simulation time 4132927460 ps
CPU time 14.88 seconds
Started Jul 07 05:33:57 PM PDT 24
Finished Jul 07 05:34:13 PM PDT 24
Peak memory 221052 kb
Host smart-cb9b53d0-fd45-45c4-991d-8d9ebb9e69e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074983619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2074983619
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.2537010948
Short name T693
Test name
Test status
Simulation time 16911204136 ps
CPU time 4.48 seconds
Started Jul 07 05:34:06 PM PDT 24
Finished Jul 07 05:34:11 PM PDT 24
Peak memory 205140 kb
Host smart-9a123351-a41c-40d4-b5f3-382fae4b87fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537010948 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.2537010948
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.2637421458
Short name T165
Test name
Test status
Simulation time 274257111 ps
CPU time 1.54 seconds
Started Jul 07 05:33:55 PM PDT 24
Finished Jul 07 05:33:57 PM PDT 24
Peak memory 204960 kb
Host smart-f176ad40-88a3-465a-a218-8c387216b9f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637421458 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.2637421458
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1466681334
Short name T1485
Test name
Test status
Simulation time 1167178895 ps
CPU time 1.4 seconds
Started Jul 07 05:33:54 PM PDT 24
Finished Jul 07 05:33:56 PM PDT 24
Peak memory 213484 kb
Host smart-447fec85-c1a6-4816-b634-7adfa8ba9cd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466681334 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.1466681334
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.3466771648
Short name T652
Test name
Test status
Simulation time 1308221992 ps
CPU time 2.05 seconds
Started Jul 07 05:34:06 PM PDT 24
Finished Jul 07 05:34:09 PM PDT 24
Peak memory 204928 kb
Host smart-7c5d6ac6-71d5-4b87-9240-69c855b9a070
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466771648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.3466771648
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.3509534718
Short name T142
Test name
Test status
Simulation time 537444672 ps
CPU time 2.86 seconds
Started Jul 07 05:34:01 PM PDT 24
Finished Jul 07 05:34:04 PM PDT 24
Peak memory 205020 kb
Host smart-2197c07c-4df9-4c0d-835d-23e935d235ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509534718 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.3509534718
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.3229733149
Short name T1232
Test name
Test status
Simulation time 5264411299 ps
CPU time 7.33 seconds
Started Jul 07 05:34:00 PM PDT 24
Finished Jul 07 05:34:08 PM PDT 24
Peak memory 219360 kb
Host smart-c915cbe9-fa09-46b8-abf0-1e5b507c7c6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229733149 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.3229733149
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3128383694
Short name T875
Test name
Test status
Simulation time 20025368720 ps
CPU time 29.49 seconds
Started Jul 07 05:33:57 PM PDT 24
Finished Jul 07 05:34:27 PM PDT 24
Peak memory 574088 kb
Host smart-cae22785-cf94-4973-a99b-380878d08784
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128383694 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3128383694
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.2113427427
Short name T572
Test name
Test status
Simulation time 955485415 ps
CPU time 13.47 seconds
Started Jul 07 05:33:56 PM PDT 24
Finished Jul 07 05:34:10 PM PDT 24
Peak memory 204904 kb
Host smart-f4e831ce-fa9a-4dab-a845-a1d93e4b64f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113427427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.2113427427
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1326409692
Short name T564
Test name
Test status
Simulation time 1969876848 ps
CPU time 8.06 seconds
Started Jul 07 05:33:58 PM PDT 24
Finished Jul 07 05:34:06 PM PDT 24
Peak memory 205036 kb
Host smart-45285449-dd6c-4766-bc77-ece9a25d66f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326409692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1326409692
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.93579945
Short name T523
Test name
Test status
Simulation time 44498487215 ps
CPU time 33.98 seconds
Started Jul 07 05:34:00 PM PDT 24
Finished Jul 07 05:34:35 PM PDT 24
Peak memory 692768 kb
Host smart-8a787937-9be1-4af5-9419-850a4bd7a96a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93579945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stress_wr.93579945
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.3218504962
Short name T813
Test name
Test status
Simulation time 3184610750 ps
CPU time 41.24 seconds
Started Jul 07 05:33:56 PM PDT 24
Finished Jul 07 05:34:38 PM PDT 24
Peak memory 385936 kb
Host smart-9ba161fa-453a-42f6-ab40-743f513dc73d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218504962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.3218504962
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1700645090
Short name T366
Test name
Test status
Simulation time 2709331938 ps
CPU time 7.65 seconds
Started Jul 07 05:33:55 PM PDT 24
Finished Jul 07 05:34:03 PM PDT 24
Peak memory 221364 kb
Host smart-a99f7337-17a6-45d5-be21-d8db63d498a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700645090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1700645090
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.3365817379
Short name T544
Test name
Test status
Simulation time 132842595 ps
CPU time 2.8 seconds
Started Jul 07 05:33:58 PM PDT 24
Finished Jul 07 05:34:02 PM PDT 24
Peak memory 205036 kb
Host smart-0d1f2eac-e54c-45ae-8056-5aaaebe43877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365817379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.3365817379
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.2758429821
Short name T585
Test name
Test status
Simulation time 16276943 ps
CPU time 0.65 seconds
Started Jul 07 05:34:04 PM PDT 24
Finished Jul 07 05:34:05 PM PDT 24
Peak memory 204588 kb
Host smart-c1c1cff6-6f6e-4ec0-ab29-89d8f6fe264e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758429821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.2758429821
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3910885106
Short name T1346
Test name
Test status
Simulation time 195315005 ps
CPU time 2.48 seconds
Started Jul 07 05:33:57 PM PDT 24
Finished Jul 07 05:34:00 PM PDT 24
Peak memory 213284 kb
Host smart-4a818f9f-b4c1-4945-b749-25af06848b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910885106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3910885106
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2242355076
Short name T817
Test name
Test status
Simulation time 1409993427 ps
CPU time 6.76 seconds
Started Jul 07 05:33:59 PM PDT 24
Finished Jul 07 05:34:07 PM PDT 24
Peak memory 279796 kb
Host smart-90d025de-5a58-4ac0-bf93-8326cf0409b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242355076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2242355076
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3340372013
Short name T1050
Test name
Test status
Simulation time 2637725186 ps
CPU time 108.04 seconds
Started Jul 07 05:34:01 PM PDT 24
Finished Jul 07 05:35:49 PM PDT 24
Peak memory 864696 kb
Host smart-02bcea8c-967b-495d-9416-5b4d2b926dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340372013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3340372013
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.1622678081
Short name T144
Test name
Test status
Simulation time 1520645313 ps
CPU time 37.11 seconds
Started Jul 07 05:33:57 PM PDT 24
Finished Jul 07 05:34:34 PM PDT 24
Peak memory 388592 kb
Host smart-2634d0ac-63ab-49e2-b826-2bde44bcf73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622678081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.1622678081
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.4039998394
Short name T370
Test name
Test status
Simulation time 100008286 ps
CPU time 1.17 seconds
Started Jul 07 05:34:03 PM PDT 24
Finished Jul 07 05:34:05 PM PDT 24
Peak memory 204892 kb
Host smart-178fb9c4-54fd-4d1e-847f-e2dacd926d36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039998394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.4039998394
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2483339916
Short name T886
Test name
Test status
Simulation time 1795884270 ps
CPU time 9.24 seconds
Started Jul 07 05:34:00 PM PDT 24
Finished Jul 07 05:34:10 PM PDT 24
Peak memory 233016 kb
Host smart-4eb346c0-8d0d-4e66-ad9c-579c52651247
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483339916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2483339916
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.204408416
Short name T109
Test name
Test status
Simulation time 12645924550 ps
CPU time 70.34 seconds
Started Jul 07 05:34:05 PM PDT 24
Finished Jul 07 05:35:17 PM PDT 24
Peak memory 928676 kb
Host smart-52fe26c6-5868-4e57-bb97-f7f643c1d891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204408416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.204408416
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.3375360940
Short name T1322
Test name
Test status
Simulation time 484344247 ps
CPU time 8.33 seconds
Started Jul 07 05:34:02 PM PDT 24
Finished Jul 07 05:34:11 PM PDT 24
Peak memory 205032 kb
Host smart-146c3b78-6921-4cfd-91c4-5f512010c81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375360940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.3375360940
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.1772866681
Short name T127
Test name
Test status
Simulation time 1444498668 ps
CPU time 22.54 seconds
Started Jul 07 05:34:06 PM PDT 24
Finished Jul 07 05:34:29 PM PDT 24
Peak memory 334464 kb
Host smart-b60e6ebd-563f-4f11-87fb-93148b4f6de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772866681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.1772866681
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.1406333402
Short name T403
Test name
Test status
Simulation time 38435367 ps
CPU time 0.66 seconds
Started Jul 07 05:33:59 PM PDT 24
Finished Jul 07 05:34:00 PM PDT 24
Peak memory 204648 kb
Host smart-2764d293-1e6c-493a-9270-98824c3df674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406333402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1406333402
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.335708956
Short name T700
Test name
Test status
Simulation time 5245191100 ps
CPU time 103.15 seconds
Started Jul 07 05:33:59 PM PDT 24
Finished Jul 07 05:35:42 PM PDT 24
Peak memory 761156 kb
Host smart-8344ae00-5e83-4403-80fd-c9eaa3496845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335708956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.335708956
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.679386779
Short name T873
Test name
Test status
Simulation time 1347154226 ps
CPU time 24.9 seconds
Started Jul 07 05:34:00 PM PDT 24
Finished Jul 07 05:34:26 PM PDT 24
Peak memory 323320 kb
Host smart-01a2a855-5da5-49d3-846c-12b9d9c7b5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679386779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.679386779
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.1483163651
Short name T1294
Test name
Test status
Simulation time 21325912626 ps
CPU time 295.3 seconds
Started Jul 07 05:33:59 PM PDT 24
Finished Jul 07 05:38:55 PM PDT 24
Peak memory 766268 kb
Host smart-b9675cc4-40cf-47fd-935b-49511ab1fa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483163651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.1483163651
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.1416803047
Short name T1306
Test name
Test status
Simulation time 759387655 ps
CPU time 34.18 seconds
Started Jul 07 05:33:58 PM PDT 24
Finished Jul 07 05:34:33 PM PDT 24
Peak memory 213244 kb
Host smart-e0d75206-cfc3-4318-b321-a475eafa62fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416803047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.1416803047
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2465166823
Short name T685
Test name
Test status
Simulation time 2592062869 ps
CPU time 3.54 seconds
Started Jul 07 05:34:04 PM PDT 24
Finished Jul 07 05:34:08 PM PDT 24
Peak memory 205104 kb
Host smart-5995c238-5208-4d4d-b163-1a745dd166df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465166823 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2465166823
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.1934051826
Short name T783
Test name
Test status
Simulation time 403903241 ps
CPU time 1.55 seconds
Started Jul 07 05:33:58 PM PDT 24
Finished Jul 07 05:34:00 PM PDT 24
Peak memory 204988 kb
Host smart-d75c22fa-a7d8-4302-8f30-661261e1554c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934051826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.1934051826
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.3959844976
Short name T1290
Test name
Test status
Simulation time 611876515 ps
CPU time 1.3 seconds
Started Jul 07 05:34:01 PM PDT 24
Finished Jul 07 05:34:03 PM PDT 24
Peak memory 204920 kb
Host smart-78bf4bcc-8eab-4a3b-9972-ee6fd386b789
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959844976 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.3959844976
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.2339543446
Short name T503
Test name
Test status
Simulation time 312724941 ps
CPU time 1.79 seconds
Started Jul 07 05:34:03 PM PDT 24
Finished Jul 07 05:34:05 PM PDT 24
Peak memory 204920 kb
Host smart-27e2e0fa-658d-4c2a-8d79-7311621e26b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339543446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.2339543446
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.2769986380
Short name T29
Test name
Test status
Simulation time 744765809 ps
CPU time 1.22 seconds
Started Jul 07 05:34:04 PM PDT 24
Finished Jul 07 05:34:06 PM PDT 24
Peak memory 205088 kb
Host smart-42ff73e8-5b34-4069-898e-22c352af6898
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769986380 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.2769986380
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.1689563409
Short name T1382
Test name
Test status
Simulation time 4455627269 ps
CPU time 5.79 seconds
Started Jul 07 05:33:59 PM PDT 24
Finished Jul 07 05:34:06 PM PDT 24
Peak memory 207028 kb
Host smart-48ba66ea-c15e-4306-a163-3e6daebe1b93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689563409 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.1689563409
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.2751482407
Short name T86
Test name
Test status
Simulation time 6168538116 ps
CPU time 4.72 seconds
Started Jul 07 05:34:07 PM PDT 24
Finished Jul 07 05:34:13 PM PDT 24
Peak memory 205112 kb
Host smart-114ef4a6-3884-42d3-9277-aaf6a700dcdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751482407 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.2751482407
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.3104241971
Short name T143
Test name
Test status
Simulation time 3495780545 ps
CPU time 13.82 seconds
Started Jul 07 05:33:59 PM PDT 24
Finished Jul 07 05:34:13 PM PDT 24
Peak memory 204912 kb
Host smart-bf2fca2f-bdff-4a26-bd3b-3138167d4d3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104241971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.3104241971
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.3294166725
Short name T1499
Test name
Test status
Simulation time 549692166 ps
CPU time 4.53 seconds
Started Jul 07 05:34:05 PM PDT 24
Finished Jul 07 05:34:10 PM PDT 24
Peak memory 205048 kb
Host smart-99720ce1-1e57-49e4-a979-9c15653f1823
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294166725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.3294166725
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.4283616259
Short name T644
Test name
Test status
Simulation time 3625941973 ps
CPU time 46.99 seconds
Started Jul 07 05:33:59 PM PDT 24
Finished Jul 07 05:34:47 PM PDT 24
Peak memory 592392 kb
Host smart-b551d710-2d99-49b5-90bd-fc9088ef2e69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283616259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.4283616259
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2555015712
Short name T1156
Test name
Test status
Simulation time 3160199358 ps
CPU time 7.23 seconds
Started Jul 07 05:34:00 PM PDT 24
Finished Jul 07 05:34:08 PM PDT 24
Peak memory 213600 kb
Host smart-4ad699a7-07df-42d3-abda-5505f7507f19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555015712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2555015712
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.1921007550
Short name T171
Test name
Test status
Simulation time 112583333 ps
CPU time 1.77 seconds
Started Jul 07 05:34:05 PM PDT 24
Finished Jul 07 05:34:07 PM PDT 24
Peak memory 204988 kb
Host smart-c3278d9e-d0dc-42fa-9612-fbf20fa8cc17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921007550 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.1921007550
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2411535434
Short name T870
Test name
Test status
Simulation time 38341243 ps
CPU time 0.63 seconds
Started Jul 07 05:34:10 PM PDT 24
Finished Jul 07 05:34:12 PM PDT 24
Peak memory 204604 kb
Host smart-8c6cbed0-542b-4fe6-9297-3c38cff5b656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411535434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2411535434
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.4109088297
Short name T1127
Test name
Test status
Simulation time 270058622 ps
CPU time 2.11 seconds
Started Jul 07 05:34:04 PM PDT 24
Finished Jul 07 05:34:07 PM PDT 24
Peak memory 213236 kb
Host smart-526af29b-8387-4c25-a188-128adf620779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109088297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.4109088297
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.3613614617
Short name T1047
Test name
Test status
Simulation time 1247775559 ps
CPU time 5.9 seconds
Started Jul 07 05:34:05 PM PDT 24
Finished Jul 07 05:34:11 PM PDT 24
Peak memory 274088 kb
Host smart-ece787aa-6e7c-47ca-a775-15b5682e95b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613614617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.3613614617
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1886723707
Short name T1151
Test name
Test status
Simulation time 3647943413 ps
CPU time 159.27 seconds
Started Jul 07 05:34:04 PM PDT 24
Finished Jul 07 05:36:44 PM PDT 24
Peak memory 731908 kb
Host smart-ea1111e8-fc65-4a5d-8313-6b55b1095453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886723707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1886723707
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.30341880
Short name T777
Test name
Test status
Simulation time 2779681050 ps
CPU time 85.26 seconds
Started Jul 07 05:34:09 PM PDT 24
Finished Jul 07 05:35:34 PM PDT 24
Peak memory 865652 kb
Host smart-0c97bf72-211c-4911-a3e3-d0f416e33da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30341880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.30341880
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2653528183
Short name T933
Test name
Test status
Simulation time 116143655 ps
CPU time 1.1 seconds
Started Jul 07 05:34:05 PM PDT 24
Finished Jul 07 05:34:07 PM PDT 24
Peak memory 204720 kb
Host smart-d16e3a70-41a7-45bb-9096-3c0e0fa8ea8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653528183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2653528183
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3674766763
Short name T482
Test name
Test status
Simulation time 2116746256 ps
CPU time 5.26 seconds
Started Jul 07 05:34:06 PM PDT 24
Finished Jul 07 05:34:12 PM PDT 24
Peak memory 238684 kb
Host smart-ce0c45c4-6c61-4544-a94a-1959ea61db8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674766763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3674766763
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.1288969996
Short name T859
Test name
Test status
Simulation time 7507467570 ps
CPU time 252.53 seconds
Started Jul 07 05:34:03 PM PDT 24
Finished Jul 07 05:38:16 PM PDT 24
Peak memory 1105860 kb
Host smart-da444644-86a7-4f92-88b1-cfe4dc80c798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288969996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1288969996
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.1462629735
Short name T1228
Test name
Test status
Simulation time 738929329 ps
CPU time 8.3 seconds
Started Jul 07 05:34:08 PM PDT 24
Finished Jul 07 05:34:17 PM PDT 24
Peak memory 204936 kb
Host smart-fe9fbd5b-1920-44da-a241-8a25ae1a5213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462629735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.1462629735
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.2432426040
Short name T38
Test name
Test status
Simulation time 10648236037 ps
CPU time 23.44 seconds
Started Jul 07 05:34:06 PM PDT 24
Finished Jul 07 05:34:30 PM PDT 24
Peak memory 284336 kb
Host smart-93c23f85-72d7-4644-a4fb-ce6d5afdb27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432426040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.2432426040
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.3602422578
Short name T1464
Test name
Test status
Simulation time 34336237 ps
CPU time 0.69 seconds
Started Jul 07 05:34:05 PM PDT 24
Finished Jul 07 05:34:06 PM PDT 24
Peak memory 204680 kb
Host smart-1c549427-e174-44b9-a63e-b4f8274a516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602422578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.3602422578
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.1314412899
Short name T759
Test name
Test status
Simulation time 193663317 ps
CPU time 1.94 seconds
Started Jul 07 05:34:07 PM PDT 24
Finished Jul 07 05:34:10 PM PDT 24
Peak memory 229480 kb
Host smart-c7e86942-c149-4638-973c-7186ca0b5d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314412899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1314412899
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.1863429775
Short name T332
Test name
Test status
Simulation time 114968855 ps
CPU time 1.18 seconds
Started Jul 07 05:34:07 PM PDT 24
Finished Jul 07 05:34:09 PM PDT 24
Peak memory 205036 kb
Host smart-bdebf8b4-0ed7-4198-aec2-d798586bca82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863429775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.1863429775
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.1978553799
Short name T1278
Test name
Test status
Simulation time 1205181672 ps
CPU time 20.91 seconds
Started Jul 07 05:34:03 PM PDT 24
Finished Jul 07 05:34:24 PM PDT 24
Peak memory 343548 kb
Host smart-263e3d09-6ce6-4286-884e-86e6cbf563b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978553799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.1978553799
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.3817305012
Short name T285
Test name
Test status
Simulation time 204149243140 ps
CPU time 2308.68 seconds
Started Jul 07 05:34:01 PM PDT 24
Finished Jul 07 06:12:31 PM PDT 24
Peak memory 3022572 kb
Host smart-f111946a-7fc5-410f-8335-fd190501dfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817305012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.3817305012
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.3533054205
Short name T739
Test name
Test status
Simulation time 1884873753 ps
CPU time 21.23 seconds
Started Jul 07 05:34:04 PM PDT 24
Finished Jul 07 05:34:26 PM PDT 24
Peak memory 213276 kb
Host smart-6c56c8de-3a6f-4887-a7e8-293376c75b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533054205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.3533054205
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3053666049
Short name T468
Test name
Test status
Simulation time 1690133231 ps
CPU time 2.45 seconds
Started Jul 07 05:34:06 PM PDT 24
Finished Jul 07 05:34:09 PM PDT 24
Peak memory 205024 kb
Host smart-6961c678-609f-4e9c-bf10-3687f9ef3d0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053666049 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3053666049
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.497927848
Short name T1370
Test name
Test status
Simulation time 282782164 ps
CPU time 1.09 seconds
Started Jul 07 05:34:07 PM PDT 24
Finished Jul 07 05:34:09 PM PDT 24
Peak memory 204764 kb
Host smart-e4de7d0c-f30e-4360-afd2-4587d5a32d0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497927848 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_acq.497927848
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.967471707
Short name T1486
Test name
Test status
Simulation time 618158777 ps
CPU time 2.84 seconds
Started Jul 07 05:34:08 PM PDT 24
Finished Jul 07 05:34:11 PM PDT 24
Peak memory 204948 kb
Host smart-5c9b663d-5069-4322-9a4b-812a73cc9b43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967471707 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.967471707
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.3577896993
Short name T1198
Test name
Test status
Simulation time 81881315 ps
CPU time 1 seconds
Started Jul 07 05:34:09 PM PDT 24
Finished Jul 07 05:34:10 PM PDT 24
Peak memory 204828 kb
Host smart-6bfc0db6-9fff-4800-8cba-219132add139
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577896993 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.3577896993
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.1590633831
Short name T212
Test name
Test status
Simulation time 2028179492 ps
CPU time 5.76 seconds
Started Jul 07 05:34:07 PM PDT 24
Finished Jul 07 05:34:14 PM PDT 24
Peak memory 219096 kb
Host smart-ad867f06-dbaf-44e6-86a5-f50317c1c59c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590633831 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.1590633831
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.1939105389
Short name T26
Test name
Test status
Simulation time 21056415385 ps
CPU time 135.55 seconds
Started Jul 07 05:34:05 PM PDT 24
Finished Jul 07 05:36:22 PM PDT 24
Peak memory 1746340 kb
Host smart-1bc29a63-ba24-436a-b4fe-634840f47bd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939105389 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.1939105389
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.3977384976
Short name T1460
Test name
Test status
Simulation time 8422700293 ps
CPU time 12.56 seconds
Started Jul 07 05:34:00 PM PDT 24
Finished Jul 07 05:34:13 PM PDT 24
Peak memory 205112 kb
Host smart-fcbd2c3c-9718-4269-9e07-493a17da33b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977384976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.3977384976
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.1503237351
Short name T1459
Test name
Test status
Simulation time 6594359613 ps
CPU time 24.73 seconds
Started Jul 07 05:34:04 PM PDT 24
Finished Jul 07 05:34:29 PM PDT 24
Peak memory 233268 kb
Host smart-876b9972-b21c-45ec-b79b-ae195ede4ae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503237351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.1503237351
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.832586679
Short name T340
Test name
Test status
Simulation time 30131781225 ps
CPU time 35.26 seconds
Started Jul 07 05:34:02 PM PDT 24
Finished Jul 07 05:34:38 PM PDT 24
Peak memory 740956 kb
Host smart-306ae2b4-a34e-48a6-9c18-8bd75e4130aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832586679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_wr.832586679
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.2061007105
Short name T626
Test name
Test status
Simulation time 1069611261 ps
CPU time 41.81 seconds
Started Jul 07 05:34:08 PM PDT 24
Finished Jul 07 05:34:50 PM PDT 24
Peak memory 386304 kb
Host smart-dc8b4ad8-d896-49f9-b7a9-67d446875450
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061007105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.2061007105
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.2702727162
Short name T1184
Test name
Test status
Simulation time 1487412607 ps
CPU time 8.29 seconds
Started Jul 07 05:34:07 PM PDT 24
Finished Jul 07 05:34:16 PM PDT 24
Peak memory 221584 kb
Host smart-78e84239-6a96-41f5-b1dd-1aebf1d26231
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702727162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.2702727162
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.1160616560
Short name T147
Test name
Test status
Simulation time 265529486 ps
CPU time 3.79 seconds
Started Jul 07 05:34:08 PM PDT 24
Finished Jul 07 05:34:12 PM PDT 24
Peak memory 205024 kb
Host smart-eeba2f71-6e41-4867-beb5-8f2d0dcee1b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160616560 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.1160616560
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.429230775
Short name T937
Test name
Test status
Simulation time 19113579 ps
CPU time 0.65 seconds
Started Jul 07 05:34:15 PM PDT 24
Finished Jul 07 05:34:16 PM PDT 24
Peak memory 204572 kb
Host smart-d4c668f4-62d4-4f5a-98e4-661fa2721229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429230775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.429230775
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.1384837398
Short name T342
Test name
Test status
Simulation time 308434652 ps
CPU time 1.86 seconds
Started Jul 07 05:34:13 PM PDT 24
Finished Jul 07 05:34:16 PM PDT 24
Peak memory 213352 kb
Host smart-7e69c442-c43d-48f5-8ff9-98722e8d36f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384837398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1384837398
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.3123827619
Short name T848
Test name
Test status
Simulation time 2455006254 ps
CPU time 5.07 seconds
Started Jul 07 05:34:10 PM PDT 24
Finished Jul 07 05:34:15 PM PDT 24
Peak memory 257896 kb
Host smart-35aacbd0-d17e-4a00-9a19-2cc545c85b48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123827619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.3123827619
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.3098665103
Short name T498
Test name
Test status
Simulation time 1909717743 ps
CPU time 59.22 seconds
Started Jul 07 05:34:11 PM PDT 24
Finished Jul 07 05:35:11 PM PDT 24
Peak memory 573520 kb
Host smart-467a66c8-026f-4e91-bbb9-8354d7e1ee58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098665103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3098665103
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.3215576923
Short name T799
Test name
Test status
Simulation time 2228199289 ps
CPU time 67.16 seconds
Started Jul 07 05:34:12 PM PDT 24
Finished Jul 07 05:35:20 PM PDT 24
Peak memory 742136 kb
Host smart-98d06ae2-e7ee-4bcb-8a4a-76550592e06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215576923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3215576923
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.4142396328
Short name T378
Test name
Test status
Simulation time 191159920 ps
CPU time 1.34 seconds
Started Jul 07 05:34:10 PM PDT 24
Finished Jul 07 05:34:12 PM PDT 24
Peak memory 204724 kb
Host smart-6aca7d4a-74b6-4df4-b024-e2cb3358f5d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142396328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.4142396328
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.3258502359
Short name T1049
Test name
Test status
Simulation time 700402708 ps
CPU time 10.76 seconds
Started Jul 07 05:34:09 PM PDT 24
Finished Jul 07 05:34:20 PM PDT 24
Peak memory 205064 kb
Host smart-e358004c-df6d-4d00-bbdc-1247e43624b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258502359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.3258502359
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.3545390329
Short name T816
Test name
Test status
Simulation time 8369741148 ps
CPU time 309.56 seconds
Started Jul 07 05:34:11 PM PDT 24
Finished Jul 07 05:39:22 PM PDT 24
Peak memory 1250692 kb
Host smart-1260d2e3-b1b0-429b-9a53-0c067da63611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545390329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.3545390329
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.3786882175
Short name T824
Test name
Test status
Simulation time 273090834 ps
CPU time 11.45 seconds
Started Jul 07 05:34:16 PM PDT 24
Finished Jul 07 05:34:28 PM PDT 24
Peak memory 204984 kb
Host smart-80580e29-2cac-4a4e-9d60-7a0c599cf664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786882175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.3786882175
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.3469521568
Short name T246
Test name
Test status
Simulation time 22495569735 ps
CPU time 51.64 seconds
Started Jul 07 05:34:09 PM PDT 24
Finished Jul 07 05:35:01 PM PDT 24
Peak memory 237600 kb
Host smart-1627174e-9dae-4b4e-8ee7-1d42df3d34e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469521568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.3469521568
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.1539644137
Short name T315
Test name
Test status
Simulation time 294656165 ps
CPU time 0.72 seconds
Started Jul 07 05:34:08 PM PDT 24
Finished Jul 07 05:34:09 PM PDT 24
Peak memory 205012 kb
Host smart-a8d6cd1f-3660-4754-871c-a143d0b0d944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539644137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1539644137
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.2401062937
Short name T975
Test name
Test status
Simulation time 137604092 ps
CPU time 6.45 seconds
Started Jul 07 05:34:09 PM PDT 24
Finished Jul 07 05:34:16 PM PDT 24
Peak memory 229852 kb
Host smart-2d4ec8dd-efcc-4854-82dc-1faa3a85e174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401062937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2401062937
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.426318400
Short name T605
Test name
Test status
Simulation time 64477715 ps
CPU time 1.43 seconds
Started Jul 07 05:34:13 PM PDT 24
Finished Jul 07 05:34:15 PM PDT 24
Peak memory 205408 kb
Host smart-f21a87b7-4212-4155-af47-5949f3b514c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426318400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.426318400
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3228409960
Short name T977
Test name
Test status
Simulation time 9672719203 ps
CPU time 40.26 seconds
Started Jul 07 05:34:08 PM PDT 24
Finished Jul 07 05:34:48 PM PDT 24
Peak memory 417864 kb
Host smart-1158fb67-45f3-47d2-a038-897546259bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228409960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3228409960
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.1389667733
Short name T1376
Test name
Test status
Simulation time 20994619226 ps
CPU time 437.05 seconds
Started Jul 07 05:34:11 PM PDT 24
Finished Jul 07 05:41:29 PM PDT 24
Peak memory 1889772 kb
Host smart-3b1d516f-2154-469b-86c7-596b68ebcc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389667733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.1389667733
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.3076877199
Short name T1210
Test name
Test status
Simulation time 715492196 ps
CPU time 31.43 seconds
Started Jul 07 05:34:15 PM PDT 24
Finished Jul 07 05:34:47 PM PDT 24
Peak memory 213204 kb
Host smart-13fc0001-214a-4400-9fff-62cb07532fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076877199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.3076877199
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1901937714
Short name T1079
Test name
Test status
Simulation time 952947490 ps
CPU time 4.7 seconds
Started Jul 07 05:34:12 PM PDT 24
Finished Jul 07 05:34:18 PM PDT 24
Peak memory 213904 kb
Host smart-d2af2517-e15d-44d6-b880-617d34e4213e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901937714 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1901937714
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2665387669
Short name T1207
Test name
Test status
Simulation time 214160503 ps
CPU time 1.52 seconds
Started Jul 07 05:34:17 PM PDT 24
Finished Jul 07 05:34:19 PM PDT 24
Peak memory 204800 kb
Host smart-9eac7b5e-b56a-41ec-8cbc-4ec41c62a4ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665387669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2665387669
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3864713650
Short name T992
Test name
Test status
Simulation time 144924493 ps
CPU time 0.95 seconds
Started Jul 07 05:34:14 PM PDT 24
Finished Jul 07 05:34:15 PM PDT 24
Peak memory 204796 kb
Host smart-4c31e592-e7aa-4056-bdad-3518a6379b35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864713650 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3864713650
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.2545140264
Short name T476
Test name
Test status
Simulation time 477830599 ps
CPU time 2.48 seconds
Started Jul 07 05:34:16 PM PDT 24
Finished Jul 07 05:34:19 PM PDT 24
Peak memory 205000 kb
Host smart-0585a26a-0c2c-45d8-bbce-0c29dd0c24b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545140264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.2545140264
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.2192994518
Short name T563
Test name
Test status
Simulation time 523674236 ps
CPU time 1.27 seconds
Started Jul 07 05:34:16 PM PDT 24
Finished Jul 07 05:34:18 PM PDT 24
Peak memory 204732 kb
Host smart-53c24289-689a-4b2a-8705-b21c39eb1cac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192994518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.2192994518
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.1788834817
Short name T1107
Test name
Test status
Simulation time 3010727263 ps
CPU time 7.79 seconds
Started Jul 07 05:34:11 PM PDT 24
Finished Jul 07 05:34:20 PM PDT 24
Peak memory 213304 kb
Host smart-0713fd77-8f8e-49f2-ab56-17ae150771d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788834817 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.1788834817
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.2364038246
Short name T1387
Test name
Test status
Simulation time 3081627513 ps
CPU time 11.03 seconds
Started Jul 07 05:34:10 PM PDT 24
Finished Jul 07 05:34:22 PM PDT 24
Peak memory 527452 kb
Host smart-7c0a7938-57d6-4bdb-9d22-079b48e9612c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364038246 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.2364038246
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.4008574928
Short name T808
Test name
Test status
Simulation time 14022121278 ps
CPU time 20.97 seconds
Started Jul 07 05:34:17 PM PDT 24
Finished Jul 07 05:34:38 PM PDT 24
Peak memory 205068 kb
Host smart-ece58905-7f7c-47d5-a223-ad46096677e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008574928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.4008574928
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.1895577675
Short name T719
Test name
Test status
Simulation time 2345878055 ps
CPU time 6.31 seconds
Started Jul 07 05:34:13 PM PDT 24
Finished Jul 07 05:34:20 PM PDT 24
Peak memory 205040 kb
Host smart-19454c29-770f-4b35-a37d-79e2bfcb1b12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895577675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.1895577675
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3474447633
Short name T632
Test name
Test status
Simulation time 24650800862 ps
CPU time 80.66 seconds
Started Jul 07 05:34:15 PM PDT 24
Finished Jul 07 05:35:36 PM PDT 24
Peak memory 1123996 kb
Host smart-46e234b1-e5ee-4b6f-ba1e-fe836469e93a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474447633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3474447633
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.1372211218
Short name T609
Test name
Test status
Simulation time 5268794686 ps
CPU time 6.5 seconds
Started Jul 07 05:34:10 PM PDT 24
Finished Jul 07 05:34:17 PM PDT 24
Peak memory 213288 kb
Host smart-273e9d76-2b92-40da-8945-9aa4c0854900
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372211218 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.1372211218
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.3117173899
Short name T1348
Test name
Test status
Simulation time 270802010 ps
CPU time 4.62 seconds
Started Jul 07 05:34:18 PM PDT 24
Finished Jul 07 05:34:23 PM PDT 24
Peak memory 205000 kb
Host smart-d80ab808-b8cd-489c-a9d4-10ed278a454c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117173899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.3117173899
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.2804053181
Short name T631
Test name
Test status
Simulation time 18692599 ps
CPU time 0.68 seconds
Started Jul 07 05:34:17 PM PDT 24
Finished Jul 07 05:34:18 PM PDT 24
Peak memory 204556 kb
Host smart-69c3adae-36c7-4cb4-9630-b5d6f623486f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804053181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2804053181
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.769659195
Short name T1028
Test name
Test status
Simulation time 478635185 ps
CPU time 9.53 seconds
Started Jul 07 05:34:16 PM PDT 24
Finished Jul 07 05:34:27 PM PDT 24
Peak memory 215204 kb
Host smart-ae1be848-aad5-4b25-96bd-00dfa32cb3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769659195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.769659195
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3514746713
Short name T978
Test name
Test status
Simulation time 975495133 ps
CPU time 3.75 seconds
Started Jul 07 05:34:16 PM PDT 24
Finished Jul 07 05:34:20 PM PDT 24
Peak memory 235608 kb
Host smart-722b2a92-7f7d-4f9e-aa60-bf1ffd1d5867
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514746713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3514746713
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.4258125029
Short name T154
Test name
Test status
Simulation time 18966434488 ps
CPU time 75.72 seconds
Started Jul 07 05:34:15 PM PDT 24
Finished Jul 07 05:35:31 PM PDT 24
Peak memory 704088 kb
Host smart-68834c86-aca0-4113-b198-ebf910094b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258125029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.4258125029
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.1181483429
Short name T1128
Test name
Test status
Simulation time 10860187780 ps
CPU time 119.73 seconds
Started Jul 07 05:34:19 PM PDT 24
Finished Jul 07 05:36:20 PM PDT 24
Peak memory 635952 kb
Host smart-b9f1f889-7778-4885-9c97-52d05a926ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181483429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1181483429
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.1279808691
Short name T319
Test name
Test status
Simulation time 142344914 ps
CPU time 1.12 seconds
Started Jul 07 05:34:13 PM PDT 24
Finished Jul 07 05:34:14 PM PDT 24
Peak memory 204744 kb
Host smart-5c2c02aa-9393-4f75-9f5d-5fb3bc7c7b4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279808691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.1279808691
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1158018515
Short name T1146
Test name
Test status
Simulation time 168294530 ps
CPU time 4.24 seconds
Started Jul 07 05:34:15 PM PDT 24
Finished Jul 07 05:34:20 PM PDT 24
Peak memory 233756 kb
Host smart-7a742c8f-2d28-4d74-9a31-30021feffbec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158018515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1158018515
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.4107415326
Short name T180
Test name
Test status
Simulation time 5463462765 ps
CPU time 179.21 seconds
Started Jul 07 05:34:12 PM PDT 24
Finished Jul 07 05:37:12 PM PDT 24
Peak memory 857932 kb
Host smart-dafb1b86-9b4b-42e7-9792-10d97b9c06a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107415326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.4107415326
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.1615412202
Short name T47
Test name
Test status
Simulation time 2291850754 ps
CPU time 4.39 seconds
Started Jul 07 05:34:19 PM PDT 24
Finished Jul 07 05:34:24 PM PDT 24
Peak memory 205128 kb
Host smart-473de932-607d-4aeb-bc9f-7c399cf2c788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615412202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1615412202
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.121971299
Short name T1070
Test name
Test status
Simulation time 7240427440 ps
CPU time 78.4 seconds
Started Jul 07 05:34:27 PM PDT 24
Finished Jul 07 05:35:46 PM PDT 24
Peak memory 325396 kb
Host smart-35b50dde-69eb-404b-811d-b612b77ea089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121971299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.121971299
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.1425154405
Short name T462
Test name
Test status
Simulation time 85881167 ps
CPU time 0.69 seconds
Started Jul 07 05:34:16 PM PDT 24
Finished Jul 07 05:34:17 PM PDT 24
Peak memory 204712 kb
Host smart-e1f1d54a-e801-4e32-b869-9d67d3e55655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425154405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1425154405
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.2964971626
Short name T1117
Test name
Test status
Simulation time 8274621204 ps
CPU time 22.34 seconds
Started Jul 07 05:34:23 PM PDT 24
Finished Jul 07 05:34:46 PM PDT 24
Peak memory 214552 kb
Host smart-0baf7011-415e-47d8-86b6-6eff875c5d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964971626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.2964971626
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.967568163
Short name T1293
Test name
Test status
Simulation time 211982227 ps
CPU time 8.46 seconds
Started Jul 07 05:34:13 PM PDT 24
Finished Jul 07 05:34:22 PM PDT 24
Peak memory 213236 kb
Host smart-a4880eb7-e310-4524-ba02-3345ea0ad02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967568163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.967568163
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.3009401827
Short name T34
Test name
Test status
Simulation time 2319421284 ps
CPU time 39.92 seconds
Started Jul 07 05:34:16 PM PDT 24
Finished Jul 07 05:34:56 PM PDT 24
Peak memory 405500 kb
Host smart-0f54cd24-33cc-4716-a803-10e6908c915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009401827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3009401827
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.2578531715
Short name T56
Test name
Test status
Simulation time 24552406624 ps
CPU time 1587.06 seconds
Started Jul 07 05:34:15 PM PDT 24
Finished Jul 07 06:00:43 PM PDT 24
Peak memory 2929988 kb
Host smart-5234da57-c0ce-4bdf-99f7-a6d1e89a98eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578531715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.2578531715
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3732675260
Short name T698
Test name
Test status
Simulation time 2457127497 ps
CPU time 29.23 seconds
Started Jul 07 05:34:14 PM PDT 24
Finished Jul 07 05:34:44 PM PDT 24
Peak memory 213280 kb
Host smart-f6c43820-b720-4ddc-bc9f-3b35ac2487e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732675260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3732675260
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.1600754598
Short name T1031
Test name
Test status
Simulation time 888717437 ps
CPU time 4.46 seconds
Started Jul 07 05:34:20 PM PDT 24
Finished Jul 07 05:34:25 PM PDT 24
Peak memory 213184 kb
Host smart-ef45d887-40d7-4242-83a6-799a8cd2afae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600754598 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.1600754598
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2449621097
Short name T794
Test name
Test status
Simulation time 189040571 ps
CPU time 1.15 seconds
Started Jul 07 05:34:17 PM PDT 24
Finished Jul 07 05:34:18 PM PDT 24
Peak memory 204780 kb
Host smart-1b147ead-96e2-40d5-a3e0-9ba9e22d486d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449621097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.2449621097
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.159857334
Short name T1111
Test name
Test status
Simulation time 394584978 ps
CPU time 0.97 seconds
Started Jul 07 05:34:20 PM PDT 24
Finished Jul 07 05:34:22 PM PDT 24
Peak memory 204772 kb
Host smart-bfa5fa7e-36bf-4223-81f8-04ea1c186950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159857334 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_tx.159857334
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.1775123147
Short name T577
Test name
Test status
Simulation time 2141878840 ps
CPU time 2.86 seconds
Started Jul 07 05:34:20 PM PDT 24
Finished Jul 07 05:34:23 PM PDT 24
Peak memory 205036 kb
Host smart-ec82c5f5-9587-4b2d-8fcc-f622916f66fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775123147 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.1775123147
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.2959502739
Short name T782
Test name
Test status
Simulation time 143850216 ps
CPU time 1.29 seconds
Started Jul 07 05:34:20 PM PDT 24
Finished Jul 07 05:34:22 PM PDT 24
Peak memory 204804 kb
Host smart-aa814de4-e5dd-42f9-b825-e5ea6c00f838
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959502739 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.2959502739
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.2738949893
Short name T1493
Test name
Test status
Simulation time 2538229265 ps
CPU time 4.01 seconds
Started Jul 07 05:34:17 PM PDT 24
Finished Jul 07 05:34:21 PM PDT 24
Peak memory 205044 kb
Host smart-cc9be13a-efcc-4687-93c1-02475a094018
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738949893 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.2738949893
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.1432765557
Short name T1424
Test name
Test status
Simulation time 14367110281 ps
CPU time 47.18 seconds
Started Jul 07 05:34:20 PM PDT 24
Finished Jul 07 05:35:08 PM PDT 24
Peak memory 1167360 kb
Host smart-672bb1f8-abdb-44d1-843e-100e9a7d1786
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432765557 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.1432765557
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.3879435879
Short name T550
Test name
Test status
Simulation time 4496784147 ps
CPU time 19.67 seconds
Started Jul 07 05:34:22 PM PDT 24
Finished Jul 07 05:34:42 PM PDT 24
Peak memory 205108 kb
Host smart-24231889-eb1f-4cb3-bdd7-e00add61e934
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879435879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.3879435879
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.3070949707
Short name T1221
Test name
Test status
Simulation time 4306043582 ps
CPU time 19.2 seconds
Started Jul 07 05:34:17 PM PDT 24
Finished Jul 07 05:34:37 PM PDT 24
Peak memory 216276 kb
Host smart-02c1fc7f-ef68-4db9-a10b-ad7b9995350a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070949707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.3070949707
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.550896369
Short name T659
Test name
Test status
Simulation time 31060153337 ps
CPU time 34.77 seconds
Started Jul 07 05:34:14 PM PDT 24
Finished Jul 07 05:34:49 PM PDT 24
Peak memory 757104 kb
Host smart-4ac48dc1-5492-40a1-883d-91201dd4a90f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550896369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_wr.550896369
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.1046358455
Short name T1152
Test name
Test status
Simulation time 4745344529 ps
CPU time 104.21 seconds
Started Jul 07 05:34:10 PM PDT 24
Finished Jul 07 05:35:55 PM PDT 24
Peak memory 1303388 kb
Host smart-928753e5-c30c-4b64-950b-feffcdd23d4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046358455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.1046358455
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3910445406
Short name T1531
Test name
Test status
Simulation time 1318161102 ps
CPU time 6.92 seconds
Started Jul 07 05:34:24 PM PDT 24
Finished Jul 07 05:34:31 PM PDT 24
Peak memory 205048 kb
Host smart-cbfc6952-8143-49ea-a083-172e043fb3ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910445406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3910445406
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.2331824509
Short name T829
Test name
Test status
Simulation time 477166753 ps
CPU time 6.43 seconds
Started Jul 07 05:34:20 PM PDT 24
Finished Jul 07 05:34:27 PM PDT 24
Peak memory 205024 kb
Host smart-d203bc3b-94d7-4f79-aeea-54568bf5d423
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331824509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.2331824509
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.3376602387
Short name T674
Test name
Test status
Simulation time 40291256 ps
CPU time 0.62 seconds
Started Jul 07 05:34:26 PM PDT 24
Finished Jul 07 05:34:27 PM PDT 24
Peak memory 204568 kb
Host smart-9a269b53-3a65-4c70-89fe-2c09782a5460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376602387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3376602387
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.2883670513
Short name T772
Test name
Test status
Simulation time 56990726 ps
CPU time 1.21 seconds
Started Jul 07 05:34:25 PM PDT 24
Finished Jul 07 05:34:27 PM PDT 24
Peak memory 213256 kb
Host smart-461d5507-ded7-4edd-91e6-4c18dc222009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883670513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.2883670513
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.4111479999
Short name T938
Test name
Test status
Simulation time 209547120 ps
CPU time 3.67 seconds
Started Jul 07 05:34:22 PM PDT 24
Finished Jul 07 05:34:27 PM PDT 24
Peak memory 229484 kb
Host smart-47371cae-3ef0-4e8b-add5-99dcb5b1c2e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111479999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.4111479999
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.1147009357
Short name T762
Test name
Test status
Simulation time 6559232159 ps
CPU time 41.71 seconds
Started Jul 07 05:34:21 PM PDT 24
Finished Jul 07 05:35:04 PM PDT 24
Peak memory 457492 kb
Host smart-d33d7920-30fe-4550-be32-9cb9d6ff45fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147009357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1147009357
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.1931014732
Short name T1356
Test name
Test status
Simulation time 5285247157 ps
CPU time 171.84 seconds
Started Jul 07 05:34:18 PM PDT 24
Finished Jul 07 05:37:10 PM PDT 24
Peak memory 625896 kb
Host smart-2ea70cd4-04da-4255-b03b-c59266081ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931014732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.1931014732
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.2171413154
Short name T1193
Test name
Test status
Simulation time 264406815 ps
CPU time 1.24 seconds
Started Jul 07 05:34:23 PM PDT 24
Finished Jul 07 05:34:25 PM PDT 24
Peak memory 204760 kb
Host smart-3c2155ac-126c-4ca1-b80c-7d2e7bfb037d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171413154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.2171413154
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.2897180260
Short name T1241
Test name
Test status
Simulation time 742252934 ps
CPU time 5.24 seconds
Started Jul 07 05:34:22 PM PDT 24
Finished Jul 07 05:34:28 PM PDT 24
Peak memory 236492 kb
Host smart-8cf96c13-84e2-4304-b392-669999456dbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897180260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.2897180260
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.3649040798
Short name T533
Test name
Test status
Simulation time 33072604098 ps
CPU time 260.77 seconds
Started Jul 07 05:34:23 PM PDT 24
Finished Jul 07 05:38:44 PM PDT 24
Peak memory 1119660 kb
Host smart-943cd56e-a8af-4449-8c11-5e218f9b1875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649040798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3649040798
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.3052339325
Short name T1272
Test name
Test status
Simulation time 1902127024 ps
CPU time 5.65 seconds
Started Jul 07 05:34:38 PM PDT 24
Finished Jul 07 05:34:45 PM PDT 24
Peak memory 205060 kb
Host smart-e00de66a-4b9e-4756-80f7-1d2458710531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052339325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.3052339325
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.2835872370
Short name T39
Test name
Test status
Simulation time 6379330340 ps
CPU time 26.85 seconds
Started Jul 07 05:34:23 PM PDT 24
Finished Jul 07 05:34:50 PM PDT 24
Peak memory 378740 kb
Host smart-411a1beb-e3ba-49b1-848f-dba21c2159d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835872370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.2835872370
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.3197614680
Short name T1449
Test name
Test status
Simulation time 119020003 ps
CPU time 0.67 seconds
Started Jul 07 05:34:23 PM PDT 24
Finished Jul 07 05:34:24 PM PDT 24
Peak memory 204724 kb
Host smart-7952c4b1-7e6a-4a62-9356-f42323d37b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197614680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.3197614680
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.2760492989
Short name T1165
Test name
Test status
Simulation time 12959054093 ps
CPU time 37.72 seconds
Started Jul 07 05:34:22 PM PDT 24
Finished Jul 07 05:35:01 PM PDT 24
Peak memory 253768 kb
Host smart-dcf8fcb1-8ff7-458f-914a-e1c85a18e380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760492989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.2760492989
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.3677576284
Short name T559
Test name
Test status
Simulation time 265474162 ps
CPU time 1.6 seconds
Started Jul 07 05:34:20 PM PDT 24
Finished Jul 07 05:34:22 PM PDT 24
Peak memory 204992 kb
Host smart-86b3f9ef-b885-4724-9f37-89f22974b4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677576284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.3677576284
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.445588499
Short name T312
Test name
Test status
Simulation time 6265940236 ps
CPU time 33.25 seconds
Started Jul 07 05:34:18 PM PDT 24
Finished Jul 07 05:34:52 PM PDT 24
Peak memory 381316 kb
Host smart-6cb27781-39b6-4e1a-9380-254a0c7623fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445588499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.445588499
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.580985800
Short name T119
Test name
Test status
Simulation time 83053786341 ps
CPU time 310.48 seconds
Started Jul 07 05:34:25 PM PDT 24
Finished Jul 07 05:39:36 PM PDT 24
Peak memory 1464652 kb
Host smart-e186956d-6e5d-4374-8b55-e1430a6e62e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580985800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.580985800
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.42194736
Short name T926
Test name
Test status
Simulation time 796050302 ps
CPU time 29.11 seconds
Started Jul 07 05:34:38 PM PDT 24
Finished Jul 07 05:35:08 PM PDT 24
Peak memory 213304 kb
Host smart-f0712f9e-48f3-45b6-9104-cdfe993b2f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42194736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.42194736
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.1511596916
Short name T1080
Test name
Test status
Simulation time 5442593264 ps
CPU time 3.72 seconds
Started Jul 07 05:34:23 PM PDT 24
Finished Jul 07 05:34:28 PM PDT 24
Peak memory 205076 kb
Host smart-5c1f463a-95da-4766-a42e-086033227369
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511596916 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1511596916
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.3327586149
Short name T296
Test name
Test status
Simulation time 219270018 ps
CPU time 1.35 seconds
Started Jul 07 05:34:26 PM PDT 24
Finished Jul 07 05:34:28 PM PDT 24
Peak memory 204784 kb
Host smart-bea516a0-944b-40ea-807c-8d5fb308cd3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327586149 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.3327586149
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.870812810
Short name T885
Test name
Test status
Simulation time 193987885 ps
CPU time 1.21 seconds
Started Jul 07 05:34:38 PM PDT 24
Finished Jul 07 05:34:40 PM PDT 24
Peak memory 213200 kb
Host smart-d546ca48-7bfd-4d34-af09-385e5dbeb7b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870812810 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.870812810
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.480405462
Short name T987
Test name
Test status
Simulation time 375881193 ps
CPU time 2.15 seconds
Started Jul 07 05:34:23 PM PDT 24
Finished Jul 07 05:34:26 PM PDT 24
Peak memory 205256 kb
Host smart-6e7160a0-7cd1-499a-b372-e14c43ca9541
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480405462 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.480405462
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.2787712017
Short name T1160
Test name
Test status
Simulation time 541710198 ps
CPU time 1.21 seconds
Started Jul 07 05:34:22 PM PDT 24
Finished Jul 07 05:34:24 PM PDT 24
Peak memory 204796 kb
Host smart-95c4ab9b-1907-47e3-9fb7-3a658391ebc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787712017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.2787712017
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1467655463
Short name T599
Test name
Test status
Simulation time 855576713 ps
CPU time 4.99 seconds
Started Jul 07 05:34:26 PM PDT 24
Finished Jul 07 05:34:31 PM PDT 24
Peak memory 213248 kb
Host smart-8715edfb-ea18-42fd-baf8-5f37d6e3ad9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467655463 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1467655463
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.989995340
Short name T805
Test name
Test status
Simulation time 2943962176 ps
CPU time 3.88 seconds
Started Jul 07 05:34:26 PM PDT 24
Finished Jul 07 05:34:31 PM PDT 24
Peak memory 205036 kb
Host smart-cc9f5c5d-7e0e-48e5-9eeb-914eb552a3ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989995340 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.989995340
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.4214209034
Short name T1461
Test name
Test status
Simulation time 626314670 ps
CPU time 8.43 seconds
Started Jul 07 05:34:24 PM PDT 24
Finished Jul 07 05:34:33 PM PDT 24
Peak memory 205348 kb
Host smart-9502c43f-3c1b-41b6-8a94-6219bf071992
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214209034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.4214209034
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.1854745479
Short name T686
Test name
Test status
Simulation time 1420977567 ps
CPU time 19.76 seconds
Started Jul 07 05:34:23 PM PDT 24
Finished Jul 07 05:34:44 PM PDT 24
Peak memory 228736 kb
Host smart-48b463f3-3d3a-44cf-9bc0-33d8696792cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854745479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.1854745479
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2854736204
Short name T1514
Test name
Test status
Simulation time 30104597449 ps
CPU time 32.08 seconds
Started Jul 07 05:34:22 PM PDT 24
Finished Jul 07 05:34:55 PM PDT 24
Peak memory 671728 kb
Host smart-d1c47fd2-6dba-4ec1-ba71-0fa60e7dbd3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854736204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.2854736204
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.117134879
Short name T1211
Test name
Test status
Simulation time 5023216071 ps
CPU time 216.15 seconds
Started Jul 07 05:34:38 PM PDT 24
Finished Jul 07 05:38:15 PM PDT 24
Peak memory 1353732 kb
Host smart-eb7307d0-53e6-404b-bb45-50ed38acbf0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117134879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_t
arget_stretch.117134879
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.3911716330
Short name T1497
Test name
Test status
Simulation time 3091020028 ps
CPU time 7.99 seconds
Started Jul 07 05:34:38 PM PDT 24
Finished Jul 07 05:34:47 PM PDT 24
Peak memory 221404 kb
Host smart-582c142a-fac2-4435-bc9a-d39984c39da2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911716330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.3911716330
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.4059531600
Short name T1001
Test name
Test status
Simulation time 129438882 ps
CPU time 2.8 seconds
Started Jul 07 05:34:24 PM PDT 24
Finished Jul 07 05:34:28 PM PDT 24
Peak memory 205056 kb
Host smart-ff5e43cf-1ebe-41a8-b044-c9708e50c5a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059531600 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.4059531600
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.1909661564
Short name T1164
Test name
Test status
Simulation time 23103036 ps
CPU time 0.64 seconds
Started Jul 07 05:34:35 PM PDT 24
Finished Jul 07 05:34:36 PM PDT 24
Peak memory 204564 kb
Host smart-bad548a5-3113-485c-82e8-6286f901c539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909661564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.1909661564
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.2014595926
Short name T1375
Test name
Test status
Simulation time 151429182 ps
CPU time 1.87 seconds
Started Jul 07 05:34:24 PM PDT 24
Finished Jul 07 05:34:27 PM PDT 24
Peak memory 213320 kb
Host smart-58083f42-b479-4f50-9100-8fa4c500b4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014595926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.2014595926
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.154436969
Short name T607
Test name
Test status
Simulation time 1870876632 ps
CPU time 4.79 seconds
Started Jul 07 05:34:25 PM PDT 24
Finished Jul 07 05:34:31 PM PDT 24
Peak memory 238300 kb
Host smart-4c2a1937-08c4-48ad-ba06-afa529bd0968
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154436969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empt
y.154436969
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.646393140
Short name T1490
Test name
Test status
Simulation time 5238759955 ps
CPU time 96.31 seconds
Started Jul 07 05:34:26 PM PDT 24
Finished Jul 07 05:36:03 PM PDT 24
Peak memory 799744 kb
Host smart-5850028c-227d-462b-ba33-a93c37ea525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646393140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.646393140
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2739526315
Short name T865
Test name
Test status
Simulation time 2844496947 ps
CPU time 77.07 seconds
Started Jul 07 05:34:27 PM PDT 24
Finished Jul 07 05:35:44 PM PDT 24
Peak memory 724796 kb
Host smart-bfb88451-dc5b-4bf6-a447-438138fae57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739526315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2739526315
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3492784155
Short name T365
Test name
Test status
Simulation time 204022512 ps
CPU time 0.94 seconds
Started Jul 07 05:34:24 PM PDT 24
Finished Jul 07 05:34:25 PM PDT 24
Peak memory 204728 kb
Host smart-f0002e3a-a899-4a41-bcc3-44a01240bd7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492784155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.3492784155
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.814369830
Short name T956
Test name
Test status
Simulation time 454892477 ps
CPU time 7.09 seconds
Started Jul 07 05:34:28 PM PDT 24
Finished Jul 07 05:34:35 PM PDT 24
Peak memory 205028 kb
Host smart-020b2427-8b1b-4afc-b9e3-9bb0cbcd44f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814369830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.
814369830
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.326553013
Short name T621
Test name
Test status
Simulation time 2682286907 ps
CPU time 66.91 seconds
Started Jul 07 05:34:26 PM PDT 24
Finished Jul 07 05:35:33 PM PDT 24
Peak memory 804680 kb
Host smart-053647ab-74dd-4d9a-902b-bc300cca75fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326553013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.326553013
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.3415314398
Short name T714
Test name
Test status
Simulation time 268941549 ps
CPU time 4.27 seconds
Started Jul 07 05:34:30 PM PDT 24
Finished Jul 07 05:34:35 PM PDT 24
Peak memory 205040 kb
Host smart-4047ceb1-7775-4f89-9bff-2fb58aa4e087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415314398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.3415314398
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.3937913711
Short name T834
Test name
Test status
Simulation time 9898807722 ps
CPU time 52.69 seconds
Started Jul 07 05:34:29 PM PDT 24
Finished Jul 07 05:35:22 PM PDT 24
Peak memory 268300 kb
Host smart-48e5798d-7917-47b1-9dff-5b8bcc1344f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937913711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.3937913711
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.2323026532
Short name T1386
Test name
Test status
Simulation time 50656051 ps
CPU time 0.68 seconds
Started Jul 07 05:34:35 PM PDT 24
Finished Jul 07 05:34:36 PM PDT 24
Peak memory 204544 kb
Host smart-39ccce05-3365-4190-af7f-3391e75e3864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323026532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.2323026532
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.314951697
Short name T576
Test name
Test status
Simulation time 674949594 ps
CPU time 4.69 seconds
Started Jul 07 05:34:27 PM PDT 24
Finished Jul 07 05:34:32 PM PDT 24
Peak memory 223144 kb
Host smart-3794e4b8-9100-43aa-a014-ae4174ef39f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314951697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.314951697
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.1120567235
Short name T385
Test name
Test status
Simulation time 23593637223 ps
CPU time 64.58 seconds
Started Jul 07 05:34:25 PM PDT 24
Finished Jul 07 05:35:31 PM PDT 24
Peak memory 205108 kb
Host smart-fa2a552a-7b7f-4f5c-acea-60cfbb4b070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120567235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.1120567235
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.76048399
Short name T328
Test name
Test status
Simulation time 1934634449 ps
CPU time 85.88 seconds
Started Jul 07 05:34:34 PM PDT 24
Finished Jul 07 05:36:01 PM PDT 24
Peak memory 344544 kb
Host smart-681c6094-8e3b-4edb-956d-a3e394755beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76048399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.76048399
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.3531029129
Short name T513
Test name
Test status
Simulation time 2775078146 ps
CPU time 11.91 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:34:51 PM PDT 24
Peak memory 215016 kb
Host smart-c8ad60bc-9e9a-4d3f-a5cc-69db7676d21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531029129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.3531029129
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.2675659411
Short name T1431
Test name
Test status
Simulation time 938771363 ps
CPU time 4.66 seconds
Started Jul 07 05:34:25 PM PDT 24
Finished Jul 07 05:34:30 PM PDT 24
Peak memory 205064 kb
Host smart-1470069c-cb3c-45e4-8217-a7deca1e7059
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675659411 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.2675659411
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2095564917
Short name T558
Test name
Test status
Simulation time 524722895 ps
CPU time 1.46 seconds
Started Jul 07 05:34:29 PM PDT 24
Finished Jul 07 05:34:30 PM PDT 24
Peak memory 205464 kb
Host smart-a47f9927-6706-4a42-83ea-307073030251
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095564917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.2095564917
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.2429949894
Short name T724
Test name
Test status
Simulation time 1100702565 ps
CPU time 1.49 seconds
Started Jul 07 05:34:26 PM PDT 24
Finished Jul 07 05:34:28 PM PDT 24
Peak memory 204856 kb
Host smart-7f4ba301-2232-4d7b-8637-a405521059ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429949894 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.2429949894
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.1652798925
Short name T497
Test name
Test status
Simulation time 1595638651 ps
CPU time 2.31 seconds
Started Jul 07 05:34:28 PM PDT 24
Finished Jul 07 05:34:31 PM PDT 24
Peak memory 204880 kb
Host smart-76be908d-aed2-4bde-8a41-85f8a3551ba8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652798925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.1652798925
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.2867579577
Short name T620
Test name
Test status
Simulation time 148312354 ps
CPU time 1.37 seconds
Started Jul 07 05:34:29 PM PDT 24
Finished Jul 07 05:34:31 PM PDT 24
Peak memory 204804 kb
Host smart-5e813204-7a05-4acb-b946-0f84b9d518c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867579577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.2867579577
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.2653494900
Short name T352
Test name
Test status
Simulation time 424341492 ps
CPU time 4.77 seconds
Started Jul 07 05:34:25 PM PDT 24
Finished Jul 07 05:34:31 PM PDT 24
Peak memory 205028 kb
Host smart-f9e38d80-c2b5-4c05-b262-e1331e8d0efb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653494900 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.2653494900
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.32632534
Short name T803
Test name
Test status
Simulation time 888323157 ps
CPU time 4.76 seconds
Started Jul 07 05:34:25 PM PDT 24
Finished Jul 07 05:34:30 PM PDT 24
Peak memory 213188 kb
Host smart-6e5ddc8e-8d5a-42f8-8247-58e26acc6407
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32632534 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_intr_smoke.32632534
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.2329171317
Short name T494
Test name
Test status
Simulation time 31307451353 ps
CPU time 100.08 seconds
Started Jul 07 05:34:25 PM PDT 24
Finished Jul 07 05:36:06 PM PDT 24
Peak memory 1841216 kb
Host smart-44a12a9f-a6db-4306-81dd-011fb3367c40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329171317 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.2329171317
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2293191627
Short name T646
Test name
Test status
Simulation time 865664680 ps
CPU time 11.6 seconds
Started Jul 07 05:34:29 PM PDT 24
Finished Jul 07 05:34:41 PM PDT 24
Peak memory 205060 kb
Host smart-f911f869-12c5-4cf4-bf15-db6d30355ea8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293191627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2293191627
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.2987102470
Short name T1098
Test name
Test status
Simulation time 299565600 ps
CPU time 4.87 seconds
Started Jul 07 05:34:26 PM PDT 24
Finished Jul 07 05:34:32 PM PDT 24
Peak memory 205056 kb
Host smart-be4ba1b3-dcef-430c-858d-757b58963044
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987102470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.2987102470
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.1424502027
Short name T985
Test name
Test status
Simulation time 55726506234 ps
CPU time 160.6 seconds
Started Jul 07 05:34:24 PM PDT 24
Finished Jul 07 05:37:05 PM PDT 24
Peak memory 2037528 kb
Host smart-f0b72583-35fa-43ae-915a-4c6852573be0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424502027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.1424502027
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1505358444
Short name T893
Test name
Test status
Simulation time 1792548364 ps
CPU time 18.16 seconds
Started Jul 07 05:34:38 PM PDT 24
Finished Jul 07 05:34:57 PM PDT 24
Peak memory 282740 kb
Host smart-2230646a-2ba2-4787-9aee-ba19567f69b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505358444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1505358444
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.1585838870
Short name T430
Test name
Test status
Simulation time 1244707483 ps
CPU time 6.79 seconds
Started Jul 07 05:34:38 PM PDT 24
Finished Jul 07 05:34:46 PM PDT 24
Peak memory 205068 kb
Host smart-ad2c3e78-1c4f-4e9a-b8a9-baaed7a980d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585838870 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.1585838870
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.4257845077
Short name T597
Test name
Test status
Simulation time 624655716 ps
CPU time 8.37 seconds
Started Jul 07 05:34:34 PM PDT 24
Finished Jul 07 05:34:43 PM PDT 24
Peak memory 214252 kb
Host smart-48a050bb-141a-44d1-8395-02b4c5e51ae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257845077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.4257845077
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.1533082781
Short name T642
Test name
Test status
Simulation time 23880370 ps
CPU time 0.63 seconds
Started Jul 07 05:34:36 PM PDT 24
Finished Jul 07 05:34:38 PM PDT 24
Peak memory 204560 kb
Host smart-b5a91607-30f0-46c2-be36-5b8449c605e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533082781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.1533082781
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3439906381
Short name T524
Test name
Test status
Simulation time 450349352 ps
CPU time 1.36 seconds
Started Jul 07 05:34:35 PM PDT 24
Finished Jul 07 05:34:37 PM PDT 24
Peak memory 213052 kb
Host smart-1a3bb24b-4aae-4f1f-a2a7-e00178e33064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439906381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3439906381
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2030832110
Short name T419
Test name
Test status
Simulation time 412220334 ps
CPU time 9.17 seconds
Started Jul 07 05:34:29 PM PDT 24
Finished Jul 07 05:34:38 PM PDT 24
Peak memory 290788 kb
Host smart-8559f2bf-2fb7-44b8-b6f4-83f4a52ed21d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030832110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2030832110
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.934449673
Short name T1101
Test name
Test status
Simulation time 2274818100 ps
CPU time 172.8 seconds
Started Jul 07 05:34:33 PM PDT 24
Finished Jul 07 05:37:26 PM PDT 24
Peak memory 772676 kb
Host smart-238e9e91-02a0-4906-a312-507535a4e5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934449673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.934449673
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2141710927
Short name T896
Test name
Test status
Simulation time 6856386789 ps
CPU time 122.82 seconds
Started Jul 07 05:34:35 PM PDT 24
Finished Jul 07 05:36:39 PM PDT 24
Peak memory 594596 kb
Host smart-bdef6924-256f-4a63-bfea-2f514d9afcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141710927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2141710927
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.1665279507
Short name T647
Test name
Test status
Simulation time 757367572 ps
CPU time 1.25 seconds
Started Jul 07 05:34:30 PM PDT 24
Finished Jul 07 05:34:32 PM PDT 24
Peak memory 204628 kb
Host smart-1364192e-10dd-49aa-864b-beb5a39b39a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665279507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.1665279507
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.144999998
Short name T467
Test name
Test status
Simulation time 157286849 ps
CPU time 3.98 seconds
Started Jul 07 05:34:28 PM PDT 24
Finished Jul 07 05:34:32 PM PDT 24
Peak memory 232460 kb
Host smart-41b23462-4339-4f1d-9e28-c7ea3e638dd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144999998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.
144999998
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.659986602
Short name T281
Test name
Test status
Simulation time 36426743820 ps
CPU time 91.4 seconds
Started Jul 07 05:34:30 PM PDT 24
Finished Jul 07 05:36:02 PM PDT 24
Peak memory 928280 kb
Host smart-19df4691-7329-411f-853a-ffbcd7fff67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659986602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.659986602
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.4120718258
Short name T940
Test name
Test status
Simulation time 1274425777 ps
CPU time 7.75 seconds
Started Jul 07 05:34:31 PM PDT 24
Finished Jul 07 05:34:39 PM PDT 24
Peak memory 205024 kb
Host smart-98169ad6-bb34-49c7-8912-4aa918f1bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120718258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.4120718258
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.4094563617
Short name T798
Test name
Test status
Simulation time 2021532930 ps
CPU time 88.62 seconds
Started Jul 07 05:34:32 PM PDT 24
Finished Jul 07 05:36:01 PM PDT 24
Peak memory 261988 kb
Host smart-1f4265ca-44dc-4f30-8d6b-c4e5da321908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094563617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.4094563617
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.3001751359
Short name T752
Test name
Test status
Simulation time 26420447 ps
CPU time 0.67 seconds
Started Jul 07 05:34:28 PM PDT 24
Finished Jul 07 05:34:29 PM PDT 24
Peak memory 204704 kb
Host smart-e4be6a84-31e1-4ed0-b111-5c25e70ee91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001751359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.3001751359
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.3237724934
Short name T145
Test name
Test status
Simulation time 42859006 ps
CPU time 1.26 seconds
Started Jul 07 05:34:28 PM PDT 24
Finished Jul 07 05:34:30 PM PDT 24
Peak memory 223420 kb
Host smart-b2fb5ba6-41cd-48b9-b7de-a8d0a3979633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237724934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.3237724934
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3461050219
Short name T1513
Test name
Test status
Simulation time 1794626415 ps
CPU time 96.88 seconds
Started Jul 07 05:34:34 PM PDT 24
Finished Jul 07 05:36:11 PM PDT 24
Peak memory 433608 kb
Host smart-767897a7-9f36-4232-ba21-ba53427c141f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461050219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3461050219
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.1798356728
Short name T286
Test name
Test status
Simulation time 30389270932 ps
CPU time 575.72 seconds
Started Jul 07 05:34:34 PM PDT 24
Finished Jul 07 05:44:10 PM PDT 24
Peak memory 1136528 kb
Host smart-4da6e205-451f-4c1e-a3e4-26296aa0e453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798356728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.1798356728
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.865327740
Short name T325
Test name
Test status
Simulation time 4457705855 ps
CPU time 9.23 seconds
Started Jul 07 05:34:31 PM PDT 24
Finished Jul 07 05:34:41 PM PDT 24
Peak memory 217136 kb
Host smart-ec06d169-58a1-440b-bb5f-3dd68cb4fda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865327740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.865327740
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.2159710468
Short name T1254
Test name
Test status
Simulation time 696779262 ps
CPU time 3.97 seconds
Started Jul 07 05:34:36 PM PDT 24
Finished Jul 07 05:34:41 PM PDT 24
Peak memory 213788 kb
Host smart-c27c8296-f538-480a-9b32-1a0029a6091c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159710468 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.2159710468
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.3572376585
Short name T552
Test name
Test status
Simulation time 589304809 ps
CPU time 1.36 seconds
Started Jul 07 05:34:34 PM PDT 24
Finished Jul 07 05:34:36 PM PDT 24
Peak memory 205004 kb
Host smart-ab679347-88c7-4917-985a-15b15a530948
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572376585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.3572376585
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2732162346
Short name T655
Test name
Test status
Simulation time 245625396 ps
CPU time 1.14 seconds
Started Jul 07 05:34:32 PM PDT 24
Finished Jul 07 05:34:34 PM PDT 24
Peak memory 204684 kb
Host smart-8b2e8517-1dfc-4ab7-b8f3-8c33e2ac1d9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732162346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.2732162346
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.3866121462
Short name T1004
Test name
Test status
Simulation time 295420884 ps
CPU time 1.81 seconds
Started Jul 07 05:34:34 PM PDT 24
Finished Jul 07 05:34:36 PM PDT 24
Peak memory 204992 kb
Host smart-5b24e6c7-c03d-4f17-8753-1823be1f890f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866121462 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.3866121462
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.4040966122
Short name T31
Test name
Test status
Simulation time 148897925 ps
CPU time 1.21 seconds
Started Jul 07 05:34:34 PM PDT 24
Finished Jul 07 05:34:36 PM PDT 24
Peak memory 204756 kb
Host smart-4268172d-585f-4b97-a9c6-a2b4ae28fb95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040966122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.4040966122
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.3802940108
Short name T481
Test name
Test status
Simulation time 1978810568 ps
CPU time 4.2 seconds
Started Jul 07 05:34:34 PM PDT 24
Finished Jul 07 05:34:38 PM PDT 24
Peak memory 205004 kb
Host smart-405b6f38-3833-490c-962e-dc6f132c7ed8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802940108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.3802940108
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.2741372355
Short name T860
Test name
Test status
Simulation time 1051502165 ps
CPU time 6.14 seconds
Started Jul 07 05:34:36 PM PDT 24
Finished Jul 07 05:34:43 PM PDT 24
Peak memory 219244 kb
Host smart-e7fca247-4cd4-471a-b736-09817938b0fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741372355 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.2741372355
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.1632927336
Short name T257
Test name
Test status
Simulation time 5396536825 ps
CPU time 4.28 seconds
Started Jul 07 05:34:35 PM PDT 24
Finished Jul 07 05:34:39 PM PDT 24
Peak memory 205124 kb
Host smart-cd034ac6-6288-4dd6-b475-9023621b1bb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632927336 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.1632927336
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.1449690958
Short name T1136
Test name
Test status
Simulation time 2661171796 ps
CPU time 26.86 seconds
Started Jul 07 05:34:28 PM PDT 24
Finished Jul 07 05:34:55 PM PDT 24
Peak memory 205024 kb
Host smart-83e314b2-951d-4f80-8772-f8fa9a8c90e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449690958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.1449690958
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2371053136
Short name T995
Test name
Test status
Simulation time 2802436994 ps
CPU time 29.06 seconds
Started Jul 07 05:34:39 PM PDT 24
Finished Jul 07 05:35:09 PM PDT 24
Peak memory 205108 kb
Host smart-390e1b2a-67b7-47ca-a810-00f7e9cb868b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371053136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2371053136
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.3778029173
Short name T392
Test name
Test status
Simulation time 35861187756 ps
CPU time 38.49 seconds
Started Jul 07 05:34:32 PM PDT 24
Finished Jul 07 05:35:11 PM PDT 24
Peak memory 775312 kb
Host smart-b2994816-4952-454f-bf0e-fefb539541d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778029173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.3778029173
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.59660016
Short name T355
Test name
Test status
Simulation time 5095748759 ps
CPU time 3.83 seconds
Started Jul 07 05:34:33 PM PDT 24
Finished Jul 07 05:34:37 PM PDT 24
Peak memory 299176 kb
Host smart-2baf361d-f82b-4989-88cf-30cfcf6b747a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59660016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_stretch.59660016
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.1720000554
Short name T845
Test name
Test status
Simulation time 1090662255 ps
CPU time 6.37 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:34:44 PM PDT 24
Peak memory 213244 kb
Host smart-f4de8c93-c751-410c-9900-cfff809d8a7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720000554 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.1720000554
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.1181925031
Short name T1347
Test name
Test status
Simulation time 373285097 ps
CPU time 4.99 seconds
Started Jul 07 05:34:35 PM PDT 24
Finished Jul 07 05:34:41 PM PDT 24
Peak memory 205028 kb
Host smart-7010f440-a68c-4f22-b421-a6cfd45d539e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181925031 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.1181925031
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.65876479
Short name T1174
Test name
Test status
Simulation time 19163201 ps
CPU time 0.65 seconds
Started Jul 07 05:34:41 PM PDT 24
Finished Jul 07 05:34:42 PM PDT 24
Peak memory 204528 kb
Host smart-c9fcd586-7e17-4eec-b559-90fead13d942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65876479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.65876479
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.2685129382
Short name T862
Test name
Test status
Simulation time 324840933 ps
CPU time 2.65 seconds
Started Jul 07 05:34:38 PM PDT 24
Finished Jul 07 05:34:41 PM PDT 24
Peak memory 218012 kb
Host smart-38d41756-c8ac-4dab-8ca4-c9a6ee02a6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685129382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.2685129382
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1250579445
Short name T1355
Test name
Test status
Simulation time 1284872496 ps
CPU time 6.61 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:34:45 PM PDT 24
Peak memory 274880 kb
Host smart-ea51d551-eb78-4855-86f3-562e32ccf596
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250579445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1250579445
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.3101154929
Short name T825
Test name
Test status
Simulation time 5935001190 ps
CPU time 84.22 seconds
Started Jul 07 05:34:36 PM PDT 24
Finished Jul 07 05:36:01 PM PDT 24
Peak memory 451576 kb
Host smart-ae74d2f8-e3f1-4db1-99b3-309caf261093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101154929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.3101154929
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1802980898
Short name T858
Test name
Test status
Simulation time 39956484501 ps
CPU time 150.58 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:37:09 PM PDT 24
Peak memory 674716 kb
Host smart-ea59bb62-dd88-4ff4-80e6-dd289ebe29b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802980898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1802980898
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.3430428560
Short name T60
Test name
Test status
Simulation time 1734192114 ps
CPU time 1.04 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:34:39 PM PDT 24
Peak memory 204716 kb
Host smart-48079818-480f-4114-9cab-f429dab0be7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430428560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.3430428560
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.2003766584
Short name T1153
Test name
Test status
Simulation time 766978238 ps
CPU time 9.85 seconds
Started Jul 07 05:34:39 PM PDT 24
Finished Jul 07 05:34:50 PM PDT 24
Peak memory 205016 kb
Host smart-53d15ced-a3ae-47d1-be36-995e74d7d59b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003766584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.2003766584
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.502074892
Short name T1005
Test name
Test status
Simulation time 4510114265 ps
CPU time 127.99 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:36:46 PM PDT 24
Peak memory 1251284 kb
Host smart-778b1724-3c6b-4765-8bab-a2b9a14aea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502074892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.502074892
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.687617118
Short name T193
Test name
Test status
Simulation time 1387370726 ps
CPU time 5.19 seconds
Started Jul 07 05:34:42 PM PDT 24
Finished Jul 07 05:34:48 PM PDT 24
Peak memory 205016 kb
Host smart-5c6fe524-b243-4743-a511-0664cd129dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687617118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.687617118
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.4020667627
Short name T1270
Test name
Test status
Simulation time 2388225899 ps
CPU time 24.62 seconds
Started Jul 07 05:34:42 PM PDT 24
Finished Jul 07 05:35:07 PM PDT 24
Peak memory 384428 kb
Host smart-bc6507de-1bfc-4649-8509-85ff05d2ad01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020667627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.4020667627
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.4285536286
Short name T1161
Test name
Test status
Simulation time 32620570 ps
CPU time 0.67 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:34:39 PM PDT 24
Peak memory 204672 kb
Host smart-896dae4b-715a-4b23-a3af-36b3e9fe0996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285536286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.4285536286
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.3048232822
Short name T967
Test name
Test status
Simulation time 553890770 ps
CPU time 2.56 seconds
Started Jul 07 05:34:35 PM PDT 24
Finished Jul 07 05:34:38 PM PDT 24
Peak memory 205304 kb
Host smart-64d27bb7-67ea-41f9-8aa4-c3d1140cb973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048232822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.3048232822
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.518677157
Short name T958
Test name
Test status
Simulation time 74203150 ps
CPU time 1.89 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:34:41 PM PDT 24
Peak memory 218152 kb
Host smart-b91322cd-e3c5-4257-8a9b-aad6af485882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518677157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.518677157
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2935234348
Short name T407
Test name
Test status
Simulation time 1364615806 ps
CPU time 59.24 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:35:37 PM PDT 24
Peak memory 264980 kb
Host smart-240ae201-1d1b-413d-bdbb-ba980dea77b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935234348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2935234348
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2188298467
Short name T54
Test name
Test status
Simulation time 10599589924 ps
CPU time 452.96 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:42:12 PM PDT 24
Peak memory 2282624 kb
Host smart-26212248-3efd-48b5-acc1-cd487826fd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188298467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2188298467
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.695091904
Short name T732
Test name
Test status
Simulation time 1913919666 ps
CPU time 21.49 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:34:59 PM PDT 24
Peak memory 213192 kb
Host smart-9be150fe-16a7-4f8a-a7cd-1026ef8b44b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695091904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.695091904
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.1480020433
Short name T892
Test name
Test status
Simulation time 2246711681 ps
CPU time 3.29 seconds
Started Jul 07 05:34:47 PM PDT 24
Finished Jul 07 05:34:51 PM PDT 24
Peak memory 205100 kb
Host smart-5ecae496-34f5-4081-ae60-b9157dd0577d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480020433 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.1480020433
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.1926066890
Short name T1417
Test name
Test status
Simulation time 224596240 ps
CPU time 0.98 seconds
Started Jul 07 05:34:44 PM PDT 24
Finished Jul 07 05:34:45 PM PDT 24
Peak memory 204796 kb
Host smart-6963360d-809d-469a-9e87-0bb1519e2d13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926066890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.1926066890
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3582150499
Short name T1196
Test name
Test status
Simulation time 269971949 ps
CPU time 1.54 seconds
Started Jul 07 05:34:38 PM PDT 24
Finished Jul 07 05:34:40 PM PDT 24
Peak memory 206096 kb
Host smart-d869f683-3ddf-49fb-b609-61ae7b28229f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582150499 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3582150499
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.1989238673
Short name T615
Test name
Test status
Simulation time 893305930 ps
CPU time 2.91 seconds
Started Jul 07 05:34:40 PM PDT 24
Finished Jul 07 05:34:43 PM PDT 24
Peak memory 205000 kb
Host smart-e3006095-831b-486a-b154-08b058bf2f1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989238673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.1989238673
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.3297756140
Short name T538
Test name
Test status
Simulation time 370658946 ps
CPU time 1.2 seconds
Started Jul 07 05:34:39 PM PDT 24
Finished Jul 07 05:34:41 PM PDT 24
Peak memory 204800 kb
Host smart-7f0d4af8-9108-4906-8d20-8b0756cca653
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297756140 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.3297756140
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.4151720435
Short name T1253
Test name
Test status
Simulation time 840209409 ps
CPU time 2 seconds
Started Jul 07 05:34:43 PM PDT 24
Finished Jul 07 05:34:45 PM PDT 24
Peak memory 205072 kb
Host smart-3eab4e76-a539-4813-9eba-169b314265f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151720435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.4151720435
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.1968899477
Short name T1112
Test name
Test status
Simulation time 13091705334 ps
CPU time 6.44 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:34:45 PM PDT 24
Peak memory 221268 kb
Host smart-6dff7968-3642-4420-9c35-dbcf8722271c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968899477 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.1968899477
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.1228547636
Short name T1341
Test name
Test status
Simulation time 10225329285 ps
CPU time 3.45 seconds
Started Jul 07 05:34:35 PM PDT 24
Finished Jul 07 05:34:39 PM PDT 24
Peak memory 205092 kb
Host smart-33e975e7-d2ab-45fe-aa97-c328e2445c06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228547636 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.1228547636
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.664827540
Short name T1259
Test name
Test status
Simulation time 5257367112 ps
CPU time 45.07 seconds
Started Jul 07 05:34:36 PM PDT 24
Finished Jul 07 05:35:22 PM PDT 24
Peak memory 205056 kb
Host smart-09ad5a9b-3d57-4b4e-be30-5ff854aa4fca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664827540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.664827540
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.2160631672
Short name T996
Test name
Test status
Simulation time 858738700 ps
CPU time 15.74 seconds
Started Jul 07 05:34:38 PM PDT 24
Finished Jul 07 05:34:55 PM PDT 24
Peak memory 212860 kb
Host smart-ce91cb4b-158f-4436-8459-03160a833245
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160631672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.2160631672
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.1492033816
Short name T635
Test name
Test status
Simulation time 8743234954 ps
CPU time 16.51 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:34:55 PM PDT 24
Peak memory 205048 kb
Host smart-a259d94b-65ec-4ed0-91f7-22edb427e6e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492033816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.1492033816
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.3270758592
Short name T1097
Test name
Test status
Simulation time 2008114859 ps
CPU time 17.62 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:34:55 PM PDT 24
Peak memory 400688 kb
Host smart-ecb35bd9-a8bc-4d00-8689-3835e315a2f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270758592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.3270758592
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.3746153775
Short name T1409
Test name
Test status
Simulation time 1370198735 ps
CPU time 6.69 seconds
Started Jul 07 05:34:37 PM PDT 24
Finished Jul 07 05:34:44 PM PDT 24
Peak memory 213196 kb
Host smart-b9003965-f15f-4142-9b7a-26fd1d7a0201
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746153775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.3746153775
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.4126943081
Short name T898
Test name
Test status
Simulation time 105072975 ps
CPU time 2.2 seconds
Started Jul 07 05:34:44 PM PDT 24
Finished Jul 07 05:34:47 PM PDT 24
Peak memory 204996 kb
Host smart-4afeab8b-df6c-4d13-bb4d-65e3ebed3295
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126943081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.4126943081
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.3513562647
Short name T351
Test name
Test status
Simulation time 52647391 ps
CPU time 0.6 seconds
Started Jul 07 05:33:06 PM PDT 24
Finished Jul 07 05:33:07 PM PDT 24
Peak memory 204600 kb
Host smart-27869d9a-83b8-41fa-9ffd-bc41516b8b08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513562647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3513562647
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.650556259
Short name T1197
Test name
Test status
Simulation time 514016775 ps
CPU time 3.07 seconds
Started Jul 07 05:33:06 PM PDT 24
Finished Jul 07 05:33:10 PM PDT 24
Peak memory 213196 kb
Host smart-71aeac00-6c80-4368-b935-44f62455a87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650556259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.650556259
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.678960859
Short name T1380
Test name
Test status
Simulation time 362763582 ps
CPU time 8.16 seconds
Started Jul 07 05:33:02 PM PDT 24
Finished Jul 07 05:33:11 PM PDT 24
Peak memory 273464 kb
Host smart-07f09703-9726-4545-b5e9-9323f13d7567
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678960859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty
.678960859
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.4025412400
Short name T1470
Test name
Test status
Simulation time 29351185266 ps
CPU time 153.41 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:35:35 PM PDT 24
Peak memory 717228 kb
Host smart-cfdab5eb-5862-4e74-8870-69847c654925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025412400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.4025412400
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3487296260
Short name T455
Test name
Test status
Simulation time 1660265730 ps
CPU time 43.18 seconds
Started Jul 07 05:33:04 PM PDT 24
Finished Jul 07 05:33:48 PM PDT 24
Peak memory 535372 kb
Host smart-502b9296-5952-4486-90aa-132bb98c9c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487296260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3487296260
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2839806469
Short name T61
Test name
Test status
Simulation time 126052778 ps
CPU time 1.21 seconds
Started Jul 07 05:33:05 PM PDT 24
Finished Jul 07 05:33:07 PM PDT 24
Peak memory 205008 kb
Host smart-b3216c76-6f19-48a9-a7bc-8a14a6cc5cc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839806469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.2839806469
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.2367627246
Short name T568
Test name
Test status
Simulation time 754581487 ps
CPU time 4 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:33:05 PM PDT 24
Peak memory 204960 kb
Host smart-0e7f4e46-2bfa-425b-937d-c828b536a06e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367627246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
2367627246
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.1676096995
Short name T322
Test name
Test status
Simulation time 23816460017 ps
CPU time 307.96 seconds
Started Jul 07 05:33:07 PM PDT 24
Finished Jul 07 05:38:15 PM PDT 24
Peak memory 1277096 kb
Host smart-bcd7fbfa-2627-4d6c-a087-b110f71b9d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676096995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.1676096995
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.4004224556
Short name T864
Test name
Test status
Simulation time 1143314467 ps
CPU time 12.61 seconds
Started Jul 07 05:33:08 PM PDT 24
Finished Jul 07 05:33:21 PM PDT 24
Peak memory 205048 kb
Host smart-cc67bc5b-3917-4d6d-ab5c-9fe68e90ba77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004224556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.4004224556
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.3893655031
Short name T980
Test name
Test status
Simulation time 6474293231 ps
CPU time 28.29 seconds
Started Jul 07 05:33:12 PM PDT 24
Finished Jul 07 05:33:40 PM PDT 24
Peak memory 382464 kb
Host smart-54d7268d-dfae-4577-a9bb-92b3c848ed01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893655031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3893655031
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1640360204
Short name T1430
Test name
Test status
Simulation time 53342884 ps
CPU time 0.69 seconds
Started Jul 07 05:33:04 PM PDT 24
Finished Jul 07 05:33:05 PM PDT 24
Peak memory 204732 kb
Host smart-43d6b62a-3184-425e-80a3-b505cb584cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640360204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1640360204
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.2548317062
Short name T1330
Test name
Test status
Simulation time 379137203 ps
CPU time 1.05 seconds
Started Jul 07 05:33:02 PM PDT 24
Finished Jul 07 05:33:04 PM PDT 24
Peak memory 204748 kb
Host smart-372210e9-ba81-4a38-a4fd-68b029d0a55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548317062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.2548317062
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.984880040
Short name T807
Test name
Test status
Simulation time 7254509235 ps
CPU time 26.16 seconds
Started Jul 07 05:33:05 PM PDT 24
Finished Jul 07 05:33:31 PM PDT 24
Peak memory 326960 kb
Host smart-acbc3f5b-235a-4c04-8f57-2d65424864d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984880040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.984880040
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.1640431795
Short name T1044
Test name
Test status
Simulation time 1917296850 ps
CPU time 7.64 seconds
Started Jul 07 05:33:06 PM PDT 24
Finished Jul 07 05:33:14 PM PDT 24
Peak memory 213224 kb
Host smart-9ead3753-8585-4cd0-a3e7-05d57588f6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640431795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.1640431795
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2106984408
Short name T184
Test name
Test status
Simulation time 79464241 ps
CPU time 0.98 seconds
Started Jul 07 05:33:13 PM PDT 24
Finished Jul 07 05:33:14 PM PDT 24
Peak memory 223280 kb
Host smart-9d38de1b-157e-4026-83c6-53c7d7bd8f87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106984408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2106984408
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.2793217168
Short name T912
Test name
Test status
Simulation time 777739087 ps
CPU time 3.94 seconds
Started Jul 07 05:33:09 PM PDT 24
Finished Jul 07 05:33:13 PM PDT 24
Peak memory 204896 kb
Host smart-b3e9da67-0c75-4be4-b06c-efbdbf3ea259
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793217168 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.2793217168
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.81407209
Short name T810
Test name
Test status
Simulation time 634830384 ps
CPU time 1.32 seconds
Started Jul 07 05:33:04 PM PDT 24
Finished Jul 07 05:33:05 PM PDT 24
Peak memory 204984 kb
Host smart-0f4107fa-4858-4644-b740-9e86fc93a22f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81407209 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_fifo_reset_acq.81407209
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3407726876
Short name T465
Test name
Test status
Simulation time 853396690 ps
CPU time 1.63 seconds
Started Jul 07 05:33:10 PM PDT 24
Finished Jul 07 05:33:12 PM PDT 24
Peak memory 208884 kb
Host smart-3e7600e0-32a8-47fd-adbf-12fa76e99475
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407726876 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3407726876
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.1590248563
Short name T820
Test name
Test status
Simulation time 823805092 ps
CPU time 1.43 seconds
Started Jul 07 05:33:12 PM PDT 24
Finished Jul 07 05:33:14 PM PDT 24
Peak memory 204748 kb
Host smart-ee38fd3b-ed5d-410d-a6c4-7df84ee4575d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590248563 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.1590248563
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.3702729047
Short name T760
Test name
Test status
Simulation time 82816945 ps
CPU time 1.04 seconds
Started Jul 07 05:33:08 PM PDT 24
Finished Jul 07 05:33:09 PM PDT 24
Peak memory 204732 kb
Host smart-35ec05a6-a299-4a3a-8e44-ff8c8bf3854b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702729047 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.3702729047
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2162034655
Short name T842
Test name
Test status
Simulation time 1556783564 ps
CPU time 4.31 seconds
Started Jul 07 05:33:02 PM PDT 24
Finished Jul 07 05:33:07 PM PDT 24
Peak memory 204964 kb
Host smart-9b76c2cd-02ce-4328-bb30-5931fc203712
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162034655 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2162034655
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.808248353
Short name T1517
Test name
Test status
Simulation time 18771568510 ps
CPU time 285.7 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:37:48 PM PDT 24
Peak memory 2986228 kb
Host smart-59eaf6cd-8d9b-43b1-96d5-39fc265bbb1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808248353 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.808248353
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1811150375
Short name T1205
Test name
Test status
Simulation time 755328025 ps
CPU time 10.49 seconds
Started Jul 07 05:33:04 PM PDT 24
Finished Jul 07 05:33:15 PM PDT 24
Peak memory 209684 kb
Host smart-d3722152-5914-4fbc-9d72-4420e2f241ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811150375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1811150375
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.388172427
Short name T890
Test name
Test status
Simulation time 32880554496 ps
CPU time 42.01 seconds
Started Jul 07 05:33:01 PM PDT 24
Finished Jul 07 05:33:44 PM PDT 24
Peak memory 867216 kb
Host smart-937a246d-a595-42e3-bd34-a14e3b5761d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388172427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.388172427
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.10271576
Short name T71
Test name
Test status
Simulation time 5432749469 ps
CPU time 7.61 seconds
Started Jul 07 05:33:04 PM PDT 24
Finished Jul 07 05:33:12 PM PDT 24
Peak memory 221204 kb
Host smart-83acddfc-8b51-4257-988e-333e6543a08c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10271576 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_timeout.10271576
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.2917059567
Short name T1383
Test name
Test status
Simulation time 266760899 ps
CPU time 4.5 seconds
Started Jul 07 05:33:05 PM PDT 24
Finished Jul 07 05:33:10 PM PDT 24
Peak memory 204976 kb
Host smart-39c5e04e-80a6-43a7-a5e6-3f03d6555c2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917059567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.2917059567
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1795757696
Short name T1336
Test name
Test status
Simulation time 18151403 ps
CPU time 0.64 seconds
Started Jul 07 05:34:45 PM PDT 24
Finished Jul 07 05:34:46 PM PDT 24
Peak memory 204568 kb
Host smart-7eaf9237-2e4b-42c8-bb50-bbd266b0a7fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795757696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1795757696
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.2430047369
Short name T871
Test name
Test status
Simulation time 475490190 ps
CPU time 2.38 seconds
Started Jul 07 05:34:43 PM PDT 24
Finished Jul 07 05:34:45 PM PDT 24
Peak memory 216392 kb
Host smart-2e6b0e90-fdcc-42e4-b9c7-b91f6b3e68f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430047369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.2430047369
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.262548402
Short name T1368
Test name
Test status
Simulation time 505598561 ps
CPU time 21.57 seconds
Started Jul 07 05:34:44 PM PDT 24
Finished Jul 07 05:35:06 PM PDT 24
Peak memory 268924 kb
Host smart-2fa4c49f-156a-43bf-962c-8e38232f23c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262548402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empt
y.262548402
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.2868376036
Short name T362
Test name
Test status
Simulation time 2835841862 ps
CPU time 73.12 seconds
Started Jul 07 05:34:40 PM PDT 24
Finished Jul 07 05:35:53 PM PDT 24
Peak memory 672372 kb
Host smart-6d5c8ea7-8d35-45ff-b4a2-42b005e5b817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868376036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.2868376036
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.959707009
Short name T317
Test name
Test status
Simulation time 2572854066 ps
CPU time 87.69 seconds
Started Jul 07 05:34:41 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 848260 kb
Host smart-ca3ad64f-f0b9-4af3-abb3-ce6999c5dbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959707009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.959707009
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3128802468
Short name T832
Test name
Test status
Simulation time 717630777 ps
CPU time 1.23 seconds
Started Jul 07 05:34:42 PM PDT 24
Finished Jul 07 05:34:43 PM PDT 24
Peak memory 204760 kb
Host smart-dd761182-239a-4a05-b1f5-f55c7e8fa983
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128802468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3128802468
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.830482026
Short name T1315
Test name
Test status
Simulation time 174395499 ps
CPU time 3.78 seconds
Started Jul 07 05:34:42 PM PDT 24
Finished Jul 07 05:34:46 PM PDT 24
Peak memory 204932 kb
Host smart-9918d431-d405-474b-a741-26aeede92196
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830482026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.
830482026
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.161461252
Short name T274
Test name
Test status
Simulation time 21890731871 ps
CPU time 363.55 seconds
Started Jul 07 05:34:43 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 1409000 kb
Host smart-394e8fbf-a5bd-4e53-ac79-d198d47eacf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161461252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.161461252
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.450313774
Short name T35
Test name
Test status
Simulation time 2888863859 ps
CPU time 15.86 seconds
Started Jul 07 05:34:48 PM PDT 24
Finished Jul 07 05:35:04 PM PDT 24
Peak memory 205096 kb
Host smart-3fdbd499-3c0f-48a8-a921-356adb9c24bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450313774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.450313774
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3906978852
Short name T1067
Test name
Test status
Simulation time 1560778834 ps
CPU time 29.4 seconds
Started Jul 07 05:34:42 PM PDT 24
Finished Jul 07 05:35:12 PM PDT 24
Peak memory 428176 kb
Host smart-4f047a7c-a730-4db3-90d4-fb3ed2da0b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906978852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3906978852
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.67567354
Short name T133
Test name
Test status
Simulation time 230205974 ps
CPU time 0.66 seconds
Started Jul 07 05:34:44 PM PDT 24
Finished Jul 07 05:34:45 PM PDT 24
Peak memory 204688 kb
Host smart-9a01731d-c9ab-4ce4-bb0a-e44dcf414ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67567354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.67567354
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.1117748307
Short name T62
Test name
Test status
Simulation time 29941288292 ps
CPU time 31.4 seconds
Started Jul 07 05:34:40 PM PDT 24
Finished Jul 07 05:35:12 PM PDT 24
Peak memory 213300 kb
Host smart-f3f8106a-a734-43f0-891a-58d9e24b8f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117748307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.1117748307
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.2303206395
Short name T376
Test name
Test status
Simulation time 350763074 ps
CPU time 8.59 seconds
Started Jul 07 05:34:41 PM PDT 24
Finished Jul 07 05:34:50 PM PDT 24
Peak memory 235704 kb
Host smart-4a5590d7-a97a-41eb-ae24-b1d672e2e12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303206395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.2303206395
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.962781524
Short name T555
Test name
Test status
Simulation time 26888183271 ps
CPU time 85.2 seconds
Started Jul 07 05:34:43 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 415552 kb
Host smart-2b46f2f3-cd39-4a2e-bff3-e14dacf1c90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962781524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.962781524
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.2154474930
Short name T287
Test name
Test status
Simulation time 34394326291 ps
CPU time 825.84 seconds
Started Jul 07 05:34:39 PM PDT 24
Finished Jul 07 05:48:25 PM PDT 24
Peak memory 1788376 kb
Host smart-216a0a05-5c78-4daf-9d1d-75c52d1021f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154474930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.2154474930
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.2079891969
Short name T1489
Test name
Test status
Simulation time 520652870 ps
CPU time 21.83 seconds
Started Jul 07 05:34:42 PM PDT 24
Finished Jul 07 05:35:05 PM PDT 24
Peak memory 213136 kb
Host smart-78c92f18-9b38-4592-b863-e2db24279298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079891969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2079891969
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.1938112700
Short name T491
Test name
Test status
Simulation time 726333510 ps
CPU time 3.87 seconds
Started Jul 07 05:34:45 PM PDT 24
Finished Jul 07 05:34:49 PM PDT 24
Peak memory 204944 kb
Host smart-dbc9e8f5-d216-4222-a816-99ee77f43c92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938112700 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.1938112700
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.2827347430
Short name T379
Test name
Test status
Simulation time 513253587 ps
CPU time 1.16 seconds
Started Jul 07 05:34:46 PM PDT 24
Finished Jul 07 05:34:48 PM PDT 24
Peak memory 204788 kb
Host smart-21b81175-2a20-4473-a53f-5e80920bcd02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827347430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.2827347430
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.458915343
Short name T1102
Test name
Test status
Simulation time 161382899 ps
CPU time 1.06 seconds
Started Jul 07 05:34:43 PM PDT 24
Finished Jul 07 05:34:44 PM PDT 24
Peak memory 204816 kb
Host smart-7ded0e6d-f350-445b-ad77-fc9c70efc2af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458915343 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_tx.458915343
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.1635746694
Short name T1524
Test name
Test status
Simulation time 2335537465 ps
CPU time 2.86 seconds
Started Jul 07 05:34:53 PM PDT 24
Finished Jul 07 05:34:56 PM PDT 24
Peak memory 204992 kb
Host smart-4de99ad6-28d7-470b-ba80-3641ca7a608c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635746694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.1635746694
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.3611246430
Short name T488
Test name
Test status
Simulation time 503743472 ps
CPU time 1.16 seconds
Started Jul 07 05:34:57 PM PDT 24
Finished Jul 07 05:34:58 PM PDT 24
Peak memory 204800 kb
Host smart-d677e7b5-c1db-4e0d-8cb2-7e8e4fca7acf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611246430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.3611246430
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.3724299265
Short name T1415
Test name
Test status
Simulation time 1582497718 ps
CPU time 3.51 seconds
Started Jul 07 05:34:48 PM PDT 24
Finished Jul 07 05:34:51 PM PDT 24
Peak memory 205088 kb
Host smart-9c5bf39f-1231-49d3-8413-840f3ed9b75f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724299265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.3724299265
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.644495229
Short name T530
Test name
Test status
Simulation time 2628778231 ps
CPU time 3.7 seconds
Started Jul 07 05:34:48 PM PDT 24
Finished Jul 07 05:34:52 PM PDT 24
Peak memory 205732 kb
Host smart-fdcef7da-0b67-49f8-8921-42ca8762f4a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644495229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.644495229
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.214927981
Short name T1456
Test name
Test status
Simulation time 17441129576 ps
CPU time 41.09 seconds
Started Jul 07 05:34:45 PM PDT 24
Finished Jul 07 05:35:26 PM PDT 24
Peak memory 752080 kb
Host smart-3641ecdb-11ba-498f-8715-b850efa9ab1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214927981 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.214927981
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.1639162032
Short name T176
Test name
Test status
Simulation time 818763312 ps
CPU time 14.04 seconds
Started Jul 07 05:34:43 PM PDT 24
Finished Jul 07 05:34:58 PM PDT 24
Peak memory 204904 kb
Host smart-8784edad-1f5a-4bca-b0b5-09c98278ad9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639162032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.1639162032
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.4151109606
Short name T1108
Test name
Test status
Simulation time 3180908485 ps
CPU time 28.05 seconds
Started Jul 07 05:34:46 PM PDT 24
Finished Jul 07 05:35:14 PM PDT 24
Peak memory 230048 kb
Host smart-147e7264-1334-4949-98b2-062a4b56faa5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151109606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.4151109606
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.872698548
Short name T941
Test name
Test status
Simulation time 46590418519 ps
CPU time 96.17 seconds
Started Jul 07 05:34:48 PM PDT 24
Finished Jul 07 05:36:25 PM PDT 24
Peak memory 1480564 kb
Host smart-9400609e-42bf-4431-8a91-f4835f0f5ad3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872698548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_wr.872698548
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.4045370611
Short name T1266
Test name
Test status
Simulation time 4689970786 ps
CPU time 10.82 seconds
Started Jul 07 05:34:47 PM PDT 24
Finished Jul 07 05:34:58 PM PDT 24
Peak memory 333084 kb
Host smart-075d0959-c9b5-4822-9da7-3c2812854368
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045370611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.4045370611
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.3122350350
Short name T973
Test name
Test status
Simulation time 3084063879 ps
CPU time 8.51 seconds
Started Jul 07 05:34:44 PM PDT 24
Finished Jul 07 05:34:53 PM PDT 24
Peak memory 221168 kb
Host smart-0f1b02e1-0810-4624-aaf1-139a89a26bf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122350350 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.3122350350
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.2416583222
Short name T345
Test name
Test status
Simulation time 442144628 ps
CPU time 5.93 seconds
Started Jul 07 05:34:44 PM PDT 24
Finished Jul 07 05:34:50 PM PDT 24
Peak memory 205288 kb
Host smart-3ad8d2dc-3ffb-43c7-b360-f0f5f68fabb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416583222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.2416583222
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2572062971
Short name T1124
Test name
Test status
Simulation time 27835222 ps
CPU time 0.65 seconds
Started Jul 07 05:34:51 PM PDT 24
Finished Jul 07 05:34:52 PM PDT 24
Peak memory 204560 kb
Host smart-d693c8cf-c8ef-4fe4-bc46-49190534037a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572062971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2572062971
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.514346027
Short name T358
Test name
Test status
Simulation time 158700319 ps
CPU time 1.38 seconds
Started Jul 07 05:34:47 PM PDT 24
Finished Jul 07 05:34:49 PM PDT 24
Peak memory 213280 kb
Host smart-a7346dc8-d1b6-4bdf-82bd-569aafa31541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514346027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.514346027
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.3333183629
Short name T1300
Test name
Test status
Simulation time 212072157 ps
CPU time 4.59 seconds
Started Jul 07 05:34:44 PM PDT 24
Finished Jul 07 05:34:48 PM PDT 24
Peak memory 243576 kb
Host smart-6919a82d-b359-413c-b8ef-ff33674bea1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333183629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.3333183629
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.761001958
Short name T375
Test name
Test status
Simulation time 7741338039 ps
CPU time 104.33 seconds
Started Jul 07 05:34:50 PM PDT 24
Finished Jul 07 05:36:35 PM PDT 24
Peak memory 882052 kb
Host smart-ed6a430f-25f2-4e9c-9549-64348e1b7c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761001958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.761001958
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.2697750569
Short name T791
Test name
Test status
Simulation time 16347277284 ps
CPU time 163.19 seconds
Started Jul 07 05:34:45 PM PDT 24
Finished Jul 07 05:37:29 PM PDT 24
Peak memory 737000 kb
Host smart-a63ae38e-6e41-4443-8939-046d4b509828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697750569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2697750569
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.4262071624
Short name T1359
Test name
Test status
Simulation time 247330360 ps
CPU time 0.89 seconds
Started Jul 07 05:34:46 PM PDT 24
Finished Jul 07 05:34:47 PM PDT 24
Peak memory 204740 kb
Host smart-d2444ec6-9f80-4e1c-9ae5-fc6f43e823f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262071624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.4262071624
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3086631257
Short name T699
Test name
Test status
Simulation time 1847261532 ps
CPU time 5.28 seconds
Started Jul 07 05:34:52 PM PDT 24
Finished Jul 07 05:34:58 PM PDT 24
Peak memory 244832 kb
Host smart-7a15568f-e05b-4036-89c0-c443912ac025
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086631257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3086631257
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.1854823490
Short name T1141
Test name
Test status
Simulation time 16301006835 ps
CPU time 94.43 seconds
Started Jul 07 05:34:46 PM PDT 24
Finished Jul 07 05:36:21 PM PDT 24
Peak memory 1186852 kb
Host smart-4aa5ab4e-4aee-4533-9902-a3472cb98a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854823490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.1854823490
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.2407017256
Short name T692
Test name
Test status
Simulation time 560536769 ps
CPU time 3.89 seconds
Started Jul 07 05:34:52 PM PDT 24
Finished Jul 07 05:34:56 PM PDT 24
Peak memory 205068 kb
Host smart-9638da81-8747-44f8-85b2-e103db3447af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407017256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.2407017256
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.2185781487
Short name T994
Test name
Test status
Simulation time 3782492508 ps
CPU time 35.35 seconds
Started Jul 07 05:34:58 PM PDT 24
Finished Jul 07 05:35:33 PM PDT 24
Peak memory 388104 kb
Host smart-73fb64a9-8c76-4db4-9645-c8f401c09fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185781487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.2185781487
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.2860043801
Short name T73
Test name
Test status
Simulation time 17365190 ps
CPU time 0.66 seconds
Started Jul 07 05:34:53 PM PDT 24
Finished Jul 07 05:34:54 PM PDT 24
Peak memory 204688 kb
Host smart-6964f121-441b-4ffd-a757-50ae89ef22cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860043801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.2860043801
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.3070306206
Short name T796
Test name
Test status
Simulation time 1246574406 ps
CPU time 8.65 seconds
Started Jul 07 05:34:49 PM PDT 24
Finished Jul 07 05:34:58 PM PDT 24
Peak memory 235184 kb
Host smart-1eba379c-1ffd-44d7-bd12-a05c054a6076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070306206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.3070306206
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.576722917
Short name T1316
Test name
Test status
Simulation time 62435180 ps
CPU time 1.75 seconds
Started Jul 07 05:34:57 PM PDT 24
Finished Jul 07 05:35:00 PM PDT 24
Peak memory 213180 kb
Host smart-f6e3c0dc-93cf-4d31-b08b-5b7270f9f219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576722917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.576722917
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.2879820288
Short name T789
Test name
Test status
Simulation time 1657653842 ps
CPU time 22.92 seconds
Started Jul 07 05:34:42 PM PDT 24
Finished Jul 07 05:35:06 PM PDT 24
Peak memory 289940 kb
Host smart-0ebb47ac-57a0-4e46-a8a1-262451f8390c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879820288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.2879820288
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.2779190898
Short name T245
Test name
Test status
Simulation time 149563300078 ps
CPU time 1382.67 seconds
Started Jul 07 05:34:55 PM PDT 24
Finished Jul 07 05:57:58 PM PDT 24
Peak memory 2160896 kb
Host smart-e1e647d3-25c9-4471-addc-6106acc2cc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779190898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.2779190898
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.250456954
Short name T1317
Test name
Test status
Simulation time 1631232376 ps
CPU time 16.22 seconds
Started Jul 07 05:34:48 PM PDT 24
Finished Jul 07 05:35:05 PM PDT 24
Peak memory 221304 kb
Host smart-450e4872-83a5-4784-b6b8-9bf20f45e097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250456954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.250456954
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.1828256964
Short name T637
Test name
Test status
Simulation time 3233430585 ps
CPU time 3.91 seconds
Started Jul 07 05:34:51 PM PDT 24
Finished Jul 07 05:34:55 PM PDT 24
Peak memory 213276 kb
Host smart-604f2534-8460-4da0-ab48-a8bad7abb00f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828256964 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.1828256964
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.3524364730
Short name T301
Test name
Test status
Simulation time 322124298 ps
CPU time 0.83 seconds
Started Jul 07 05:34:52 PM PDT 24
Finished Jul 07 05:34:53 PM PDT 24
Peak memory 204796 kb
Host smart-b4bb889a-0af6-4c30-9eff-eae6d14d8255
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524364730 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.3524364730
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.2750987350
Short name T1515
Test name
Test status
Simulation time 447092223 ps
CPU time 0.98 seconds
Started Jul 07 05:34:48 PM PDT 24
Finished Jul 07 05:34:49 PM PDT 24
Peak memory 204776 kb
Host smart-311b94e0-f155-47fd-9aab-cc4dc80855cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750987350 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.2750987350
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.986687560
Short name T1008
Test name
Test status
Simulation time 3297717819 ps
CPU time 2.74 seconds
Started Jul 07 05:34:54 PM PDT 24
Finished Jul 07 05:34:58 PM PDT 24
Peak memory 205056 kb
Host smart-992d80f7-aa29-4e25-ab6e-6804c5d95c7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986687560 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.986687560
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.1478628433
Short name T942
Test name
Test status
Simulation time 108973906 ps
CPU time 1.13 seconds
Started Jul 07 05:34:51 PM PDT 24
Finished Jul 07 05:34:52 PM PDT 24
Peak memory 205088 kb
Host smart-a3962c4f-be3a-4e0a-9419-bf5d3b4c85ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478628433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.1478628433
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.2374095786
Short name T543
Test name
Test status
Simulation time 645838185 ps
CPU time 3.76 seconds
Started Jul 07 05:34:49 PM PDT 24
Finished Jul 07 05:34:53 PM PDT 24
Peak memory 205032 kb
Host smart-29b02932-62ea-4557-8092-654ee8922471
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374095786 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.2374095786
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.783046097
Short name T757
Test name
Test status
Simulation time 17965564695 ps
CPU time 126.75 seconds
Started Jul 07 05:34:50 PM PDT 24
Finished Jul 07 05:36:58 PM PDT 24
Peak memory 2245972 kb
Host smart-1b9362d6-0d0e-430a-9be0-59ab320c4c80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783046097 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.783046097
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.380686273
Short name T177
Test name
Test status
Simulation time 933577011 ps
CPU time 11.7 seconds
Started Jul 07 05:34:49 PM PDT 24
Finished Jul 07 05:35:01 PM PDT 24
Peak memory 204976 kb
Host smart-5d3935b9-7aaa-429e-9dd3-8a1b5da3df8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380686273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_tar
get_smoke.380686273
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.514078004
Short name T630
Test name
Test status
Simulation time 1223594100 ps
CPU time 11.5 seconds
Started Jul 07 05:34:52 PM PDT 24
Finished Jul 07 05:35:04 PM PDT 24
Peak memory 207516 kb
Host smart-f3eb4db7-a284-4c4a-8cfe-74c9eaff4f19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514078004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_rd.514078004
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.4045903404
Short name T1276
Test name
Test status
Simulation time 41790551761 ps
CPU time 119.02 seconds
Started Jul 07 05:34:48 PM PDT 24
Finished Jul 07 05:36:47 PM PDT 24
Peak memory 1824392 kb
Host smart-9cde5627-d262-4ae0-a0e9-5bbf4885f539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045903404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.4045903404
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.679951769
Short name T1478
Test name
Test status
Simulation time 1109903870 ps
CPU time 5.39 seconds
Started Jul 07 05:34:49 PM PDT 24
Finished Jul 07 05:34:55 PM PDT 24
Peak memory 210248 kb
Host smart-577261b7-68d1-4847-924e-0f8507ddef4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679951769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_t
arget_stretch.679951769
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.3956822381
Short name T1291
Test name
Test status
Simulation time 1630597330 ps
CPU time 7.57 seconds
Started Jul 07 05:34:51 PM PDT 24
Finished Jul 07 05:34:59 PM PDT 24
Peak memory 220776 kb
Host smart-c8bd8763-9dad-48ca-a029-20b1995e3728
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956822381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.3956822381
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.109078865
Short name T895
Test name
Test status
Simulation time 108776529 ps
CPU time 2.44 seconds
Started Jul 07 05:34:56 PM PDT 24
Finished Jul 07 05:34:58 PM PDT 24
Peak memory 205012 kb
Host smart-dc52cc16-26f9-4239-a0c5-98cb091e5961
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109078865 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.109078865
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.2318336048
Short name T390
Test name
Test status
Simulation time 102988447 ps
CPU time 0.67 seconds
Started Jul 07 05:34:56 PM PDT 24
Finished Jul 07 05:34:58 PM PDT 24
Peak memory 204524 kb
Host smart-608542c7-7681-4d84-9e98-e3780892689e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318336048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2318336048
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.1837960326
Short name T416
Test name
Test status
Simulation time 1007742192 ps
CPU time 2.94 seconds
Started Jul 07 05:34:51 PM PDT 24
Finished Jul 07 05:34:54 PM PDT 24
Peak memory 221308 kb
Host smart-cfedfb87-d6d8-4f78-a642-87e1b6824501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837960326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.1837960326
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.2176173721
Short name T602
Test name
Test status
Simulation time 730692860 ps
CPU time 16.05 seconds
Started Jul 07 05:34:52 PM PDT 24
Finished Jul 07 05:35:08 PM PDT 24
Peak memory 241128 kb
Host smart-1e0be082-019e-4ec5-90fd-488c2085cb69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176173721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.2176173721
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3035104248
Short name T1420
Test name
Test status
Simulation time 10864996885 ps
CPU time 216.51 seconds
Started Jul 07 05:34:51 PM PDT 24
Finished Jul 07 05:38:28 PM PDT 24
Peak memory 882196 kb
Host smart-dbe00491-ee8d-4f96-891d-80b71cf9e50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035104248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3035104248
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.3442702359
Short name T1474
Test name
Test status
Simulation time 2174005368 ps
CPU time 65.99 seconds
Started Jul 07 05:34:52 PM PDT 24
Finished Jul 07 05:35:59 PM PDT 24
Peak memory 699056 kb
Host smart-95256b65-c47f-46e9-8881-c4ba7fa41ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442702359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.3442702359
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.1757886317
Short name T1405
Test name
Test status
Simulation time 639025524 ps
CPU time 1.22 seconds
Started Jul 07 05:34:55 PM PDT 24
Finished Jul 07 05:34:57 PM PDT 24
Peak memory 204804 kb
Host smart-e863a86f-bfeb-41d0-95a5-6cce51f41f07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757886317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.1757886317
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1152134822
Short name T953
Test name
Test status
Simulation time 180628842 ps
CPU time 3.19 seconds
Started Jul 07 05:34:50 PM PDT 24
Finished Jul 07 05:34:54 PM PDT 24
Peak memory 223824 kb
Host smart-49012731-6c5a-4173-b794-fcf85e4bb888
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152134822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1152134822
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.3529266540
Short name T522
Test name
Test status
Simulation time 3788751748 ps
CPU time 106.96 seconds
Started Jul 07 05:34:52 PM PDT 24
Finished Jul 07 05:36:39 PM PDT 24
Peak memory 1110528 kb
Host smart-45634aca-d81c-4d45-8866-37def44fd36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529266540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3529266540
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.521008498
Short name T993
Test name
Test status
Simulation time 421625581 ps
CPU time 5.95 seconds
Started Jul 07 05:34:58 PM PDT 24
Finished Jul 07 05:35:05 PM PDT 24
Peak memory 204996 kb
Host smart-dcc55a18-92ff-42d7-93e3-3efffc562989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521008498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.521008498
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.2787940737
Short name T442
Test name
Test status
Simulation time 3259146503 ps
CPU time 76.43 seconds
Started Jul 07 05:34:57 PM PDT 24
Finished Jul 07 05:36:14 PM PDT 24
Peak memory 449396 kb
Host smart-ccad3aac-35f9-4e69-9a07-c49c0cc338ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787940737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.2787940737
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.3762652456
Short name T1307
Test name
Test status
Simulation time 94388766 ps
CPU time 0.67 seconds
Started Jul 07 05:34:51 PM PDT 24
Finished Jul 07 05:34:52 PM PDT 24
Peak memory 204704 kb
Host smart-6d832320-316c-4dcc-92a6-75bcaea067cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762652456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.3762652456
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.2956994426
Short name T1329
Test name
Test status
Simulation time 27041271041 ps
CPU time 1773.55 seconds
Started Jul 07 05:34:57 PM PDT 24
Finished Jul 07 06:04:31 PM PDT 24
Peak memory 4334316 kb
Host smart-242b96ef-b6b2-429f-90b5-58ac0594e5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956994426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2956994426
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.3618194179
Short name T1200
Test name
Test status
Simulation time 188539160 ps
CPU time 1.12 seconds
Started Jul 07 05:34:53 PM PDT 24
Finished Jul 07 05:34:55 PM PDT 24
Peak memory 222212 kb
Host smart-50e12767-011e-49dd-8d87-a1127357477b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618194179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.3618194179
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.641612885
Short name T493
Test name
Test status
Simulation time 3030824025 ps
CPU time 32.7 seconds
Started Jul 07 05:34:53 PM PDT 24
Finished Jul 07 05:35:26 PM PDT 24
Peak memory 382296 kb
Host smart-2853e1e6-79ff-42b7-bcd5-fbee20a69e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641612885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.641612885
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.3520100836
Short name T490
Test name
Test status
Simulation time 17560447392 ps
CPU time 48.63 seconds
Started Jul 07 05:34:52 PM PDT 24
Finished Jul 07 05:35:41 PM PDT 24
Peak memory 389756 kb
Host smart-c78c6a3d-6456-4bf4-a3b0-00ac55fa08b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520100836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.3520100836
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.3913559621
Short name T502
Test name
Test status
Simulation time 991961725 ps
CPU time 43.19 seconds
Started Jul 07 05:34:53 PM PDT 24
Finished Jul 07 05:35:36 PM PDT 24
Peak memory 221440 kb
Host smart-67250195-116a-4c6a-932d-797f80a1438a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913559621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3913559621
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.1412055748
Short name T1216
Test name
Test status
Simulation time 1385400694 ps
CPU time 3.88 seconds
Started Jul 07 05:34:54 PM PDT 24
Finished Jul 07 05:34:58 PM PDT 24
Peak memory 213220 kb
Host smart-d71e8ab5-d3e1-4b25-9bb2-34faf902c94b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412055748 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.1412055748
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.4243658911
Short name T964
Test name
Test status
Simulation time 173196120 ps
CPU time 1.08 seconds
Started Jul 07 05:34:56 PM PDT 24
Finished Jul 07 05:34:58 PM PDT 24
Peak memory 204796 kb
Host smart-a2df23b3-b55e-4d74-a6f1-fff98c004ef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243658911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.4243658911
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.2568498125
Short name T1395
Test name
Test status
Simulation time 208648485 ps
CPU time 0.94 seconds
Started Jul 07 05:35:02 PM PDT 24
Finished Jul 07 05:35:04 PM PDT 24
Peak memory 204772 kb
Host smart-4220ff94-2dbd-47e5-b308-fb6327e96cfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568498125 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.2568498125
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.4260104484
Short name T1021
Test name
Test status
Simulation time 2649096533 ps
CPU time 3.13 seconds
Started Jul 07 05:34:54 PM PDT 24
Finished Jul 07 05:34:57 PM PDT 24
Peak memory 205096 kb
Host smart-a9d517aa-b433-4911-a1fe-59cd916e24e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260104484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.4260104484
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.3568620515
Short name T878
Test name
Test status
Simulation time 116632737 ps
CPU time 1.11 seconds
Started Jul 07 05:34:56 PM PDT 24
Finished Jul 07 05:34:57 PM PDT 24
Peak memory 204784 kb
Host smart-0fad07c0-5bc8-4f16-99e6-5855fa66fba0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568620515 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.3568620515
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.1207380558
Short name T1313
Test name
Test status
Simulation time 704655436 ps
CPU time 3.81 seconds
Started Jul 07 05:34:57 PM PDT 24
Finished Jul 07 05:35:01 PM PDT 24
Peak memory 204976 kb
Host smart-09d8cf5f-907f-409c-9297-f55a6509e140
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207380558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.1207380558
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.2671857586
Short name T1525
Test name
Test status
Simulation time 2066749644 ps
CPU time 4.87 seconds
Started Jul 07 05:35:00 PM PDT 24
Finished Jul 07 05:35:05 PM PDT 24
Peak memory 206628 kb
Host smart-5f70a508-97cf-4626-b327-ac440bffcbd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671857586 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.2671857586
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.3120153370
Short name T303
Test name
Test status
Simulation time 12663041149 ps
CPU time 257.84 seconds
Started Jul 07 05:34:54 PM PDT 24
Finished Jul 07 05:39:13 PM PDT 24
Peak memory 3113580 kb
Host smart-c0b9d158-b992-48cb-9e2f-9baf87b4805d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120153370 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.3120153370
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.2775512758
Short name T472
Test name
Test status
Simulation time 1715396487 ps
CPU time 72.41 seconds
Started Jul 07 05:34:51 PM PDT 24
Finished Jul 07 05:36:04 PM PDT 24
Peak memory 208008 kb
Host smart-70f470aa-da4d-4f7f-8814-c82227e6d768
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775512758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.2775512758
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.3262928007
Short name T1169
Test name
Test status
Simulation time 51483835363 ps
CPU time 153.1 seconds
Started Jul 07 05:34:55 PM PDT 24
Finished Jul 07 05:37:28 PM PDT 24
Peak memory 2021516 kb
Host smart-8bc9c501-ddb8-44f1-9191-7e83542a7406
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262928007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.3262928007
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.1879202030
Short name T592
Test name
Test status
Simulation time 6031892899 ps
CPU time 278.55 seconds
Started Jul 07 05:34:51 PM PDT 24
Finished Jul 07 05:39:30 PM PDT 24
Peak memory 1242368 kb
Host smart-c00355b5-5961-4fae-b534-9e0f2d59a982
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879202030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.1879202030
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.1059226608
Short name T420
Test name
Test status
Simulation time 1331726134 ps
CPU time 7.57 seconds
Started Jul 07 05:34:55 PM PDT 24
Finished Jul 07 05:35:03 PM PDT 24
Peak memory 221196 kb
Host smart-1e3656f1-0e8b-4b68-a19a-653effae9787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059226608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.1059226608
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.1393351674
Short name T17
Test name
Test status
Simulation time 50118163 ps
CPU time 1.23 seconds
Started Jul 07 05:34:57 PM PDT 24
Finished Jul 07 05:34:58 PM PDT 24
Peak memory 205036 kb
Host smart-4c3f2108-144b-40ac-aa93-d7416855accd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393351674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.1393351674
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.164485733
Short name T1282
Test name
Test status
Simulation time 17665421 ps
CPU time 0.64 seconds
Started Jul 07 05:35:07 PM PDT 24
Finished Jul 07 05:35:08 PM PDT 24
Peak memory 204572 kb
Host smart-1e59bfb5-9c03-45f2-a092-9e9b4fdf606d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164485733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.164485733
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.1448182377
Short name T662
Test name
Test status
Simulation time 239115708 ps
CPU time 1.87 seconds
Started Jul 07 05:34:58 PM PDT 24
Finished Jul 07 05:35:01 PM PDT 24
Peak memory 213376 kb
Host smart-3edec7fa-f02c-4727-851f-d306f1658593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448182377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.1448182377
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.2433884534
Short name T1468
Test name
Test status
Simulation time 1622982827 ps
CPU time 9.89 seconds
Started Jul 07 05:35:02 PM PDT 24
Finished Jul 07 05:35:12 PM PDT 24
Peak memory 295456 kb
Host smart-2dd93ac3-1f66-4062-be00-8f57a957b484
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433884534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.2433884534
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.3346562974
Short name T542
Test name
Test status
Simulation time 9687062397 ps
CPU time 77.6 seconds
Started Jul 07 05:35:00 PM PDT 24
Finished Jul 07 05:36:18 PM PDT 24
Peak memory 788624 kb
Host smart-6b6b5d9a-008c-46cd-a540-66b07f07ff90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346562974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.3346562974
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.2789903408
Short name T471
Test name
Test status
Simulation time 9492261625 ps
CPU time 178.81 seconds
Started Jul 07 05:35:03 PM PDT 24
Finished Jul 07 05:38:03 PM PDT 24
Peak memory 772208 kb
Host smart-448ff77d-bd12-413f-a8ca-a86e7d04ea1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789903408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.2789903408
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2846604520
Short name T1106
Test name
Test status
Simulation time 1235058822 ps
CPU time 1.05 seconds
Started Jul 07 05:35:03 PM PDT 24
Finished Jul 07 05:35:06 PM PDT 24
Peak memory 204392 kb
Host smart-076d95e4-787e-425a-acd8-f2239a8c8c2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846604520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2846604520
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1810984269
Short name T569
Test name
Test status
Simulation time 218469852 ps
CPU time 5.48 seconds
Started Jul 07 05:34:59 PM PDT 24
Finished Jul 07 05:35:05 PM PDT 24
Peak memory 248176 kb
Host smart-707bec50-6ff0-4979-b3ed-2766adb31ef4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810984269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1810984269
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.1401923441
Short name T1192
Test name
Test status
Simulation time 4993007867 ps
CPU time 131.36 seconds
Started Jul 07 05:35:02 PM PDT 24
Finished Jul 07 05:37:13 PM PDT 24
Peak memory 1338764 kb
Host smart-08c56935-fa18-465c-89ad-9c14419a01a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401923441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1401923441
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.642199343
Short name T1343
Test name
Test status
Simulation time 2710187550 ps
CPU time 10.5 seconds
Started Jul 07 05:35:01 PM PDT 24
Finished Jul 07 05:35:12 PM PDT 24
Peak memory 205072 kb
Host smart-7a752472-ffe9-4755-a14e-bef7c51ce047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642199343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.642199343
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.1759774138
Short name T587
Test name
Test status
Simulation time 6121352700 ps
CPU time 65.35 seconds
Started Jul 07 05:35:00 PM PDT 24
Finished Jul 07 05:36:06 PM PDT 24
Peak memory 283816 kb
Host smart-44b01a7b-a173-4c13-b0dd-b05970e17b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759774138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.1759774138
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.818525981
Short name T1179
Test name
Test status
Simulation time 27957602 ps
CPU time 0.67 seconds
Started Jul 07 05:35:03 PM PDT 24
Finished Jul 07 05:35:04 PM PDT 24
Peak memory 204676 kb
Host smart-d91156a7-ef3f-4ac8-9e32-1bb8b4dd3d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818525981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.818525981
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1857478026
Short name T1113
Test name
Test status
Simulation time 7750200034 ps
CPU time 25.52 seconds
Started Jul 07 05:35:04 PM PDT 24
Finished Jul 07 05:35:30 PM PDT 24
Peak memory 466780 kb
Host smart-d25e867f-a662-4599-9589-caca4ab98347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857478026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1857478026
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.608965246
Short name T191
Test name
Test status
Simulation time 84666425 ps
CPU time 1.24 seconds
Started Jul 07 05:34:58 PM PDT 24
Finished Jul 07 05:35:00 PM PDT 24
Peak memory 222648 kb
Host smart-efe68aa6-18c6-4edf-a4f3-ca74a05e28fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608965246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.608965246
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3969090741
Short name T738
Test name
Test status
Simulation time 1303083866 ps
CPU time 21.91 seconds
Started Jul 07 05:35:02 PM PDT 24
Finished Jul 07 05:35:25 PM PDT 24
Peak memory 346576 kb
Host smart-8157e8ce-d043-4dfe-8f08-7a6bacb34ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969090741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3969090741
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.2726298780
Short name T1351
Test name
Test status
Simulation time 44024143535 ps
CPU time 3147.48 seconds
Started Jul 07 05:34:59 PM PDT 24
Finished Jul 07 06:27:27 PM PDT 24
Peak memory 3466596 kb
Host smart-8c838408-8e60-473b-bc0e-68c1d68054eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726298780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.2726298780
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.2579030319
Short name T453
Test name
Test status
Simulation time 673591848 ps
CPU time 10.45 seconds
Started Jul 07 05:35:02 PM PDT 24
Finished Jul 07 05:35:12 PM PDT 24
Peak memory 215436 kb
Host smart-3106007a-bd24-4256-a245-30c52d658095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579030319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2579030319
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.2260134838
Short name T1413
Test name
Test status
Simulation time 1906899105 ps
CPU time 4.58 seconds
Started Jul 07 05:34:58 PM PDT 24
Finished Jul 07 05:35:03 PM PDT 24
Peak memory 213612 kb
Host smart-a4585388-ac74-4738-baa5-83bcf432ac59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260134838 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.2260134838
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2086042260
Short name T1176
Test name
Test status
Simulation time 274406773 ps
CPU time 1.41 seconds
Started Jul 07 05:35:02 PM PDT 24
Finished Jul 07 05:35:04 PM PDT 24
Peak memory 204960 kb
Host smart-369e2d4a-f730-4ea8-bfc1-df7f71d9d23b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086042260 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2086042260
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.1555568958
Short name T483
Test name
Test status
Simulation time 162891148 ps
CPU time 0.98 seconds
Started Jul 07 05:35:03 PM PDT 24
Finished Jul 07 05:35:05 PM PDT 24
Peak memory 204768 kb
Host smart-26d36a2f-8475-41fc-9d5b-3a37e2633e01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555568958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.1555568958
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.2743083879
Short name T764
Test name
Test status
Simulation time 503251638 ps
CPU time 2.58 seconds
Started Jul 07 05:35:03 PM PDT 24
Finished Jul 07 05:35:07 PM PDT 24
Peak memory 204936 kb
Host smart-0fb74a40-bf34-4975-9384-db383110b603
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743083879 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.2743083879
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.3268143634
Short name T1003
Test name
Test status
Simulation time 585714188 ps
CPU time 1.34 seconds
Started Jul 07 05:35:03 PM PDT 24
Finished Jul 07 05:35:05 PM PDT 24
Peak memory 205088 kb
Host smart-b24ac1fc-d7bf-4809-9d07-231a4c0b8292
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268143634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.3268143634
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.2237628177
Short name T1131
Test name
Test status
Simulation time 407755396 ps
CPU time 4.12 seconds
Started Jul 07 05:34:58 PM PDT 24
Finished Jul 07 05:35:02 PM PDT 24
Peak memory 205064 kb
Host smart-9c5ca14a-7e9e-46a5-ad2d-4ad81647399c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237628177 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.2237628177
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.1515405762
Short name T146
Test name
Test status
Simulation time 976418159 ps
CPU time 5.74 seconds
Started Jul 07 05:34:58 PM PDT 24
Finished Jul 07 05:35:05 PM PDT 24
Peak memory 213160 kb
Host smart-dcbb4ed3-68ce-4a47-87cd-f026981d62c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515405762 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.1515405762
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.1827226892
Short name T704
Test name
Test status
Simulation time 3176309558 ps
CPU time 6.46 seconds
Started Jul 07 05:34:58 PM PDT 24
Finished Jul 07 05:35:05 PM PDT 24
Peak memory 204976 kb
Host smart-0e538096-6e39-44e9-b53c-be007b577c38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827226892 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.1827226892
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.4147983842
Short name T797
Test name
Test status
Simulation time 3246386377 ps
CPU time 33.76 seconds
Started Jul 07 05:35:00 PM PDT 24
Finished Jul 07 05:35:34 PM PDT 24
Peak memory 205064 kb
Host smart-bf709535-bf5f-4856-a784-073b310951f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147983842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.4147983842
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2294680059
Short name T350
Test name
Test status
Simulation time 399253502 ps
CPU time 5.62 seconds
Started Jul 07 05:35:02 PM PDT 24
Finished Jul 07 05:35:08 PM PDT 24
Peak memory 204968 kb
Host smart-fb4c7059-d05d-4352-8d95-d8b019e3907b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294680059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2294680059
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.3287672230
Short name T1048
Test name
Test status
Simulation time 12009089387 ps
CPU time 20.79 seconds
Started Jul 07 05:35:03 PM PDT 24
Finished Jul 07 05:35:24 PM PDT 24
Peak memory 205036 kb
Host smart-7bf535ed-e9bc-46c4-a337-b21fafa7d266
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287672230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.3287672230
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3357559308
Short name T123
Test name
Test status
Simulation time 2954167746 ps
CPU time 7.67 seconds
Started Jul 07 05:35:01 PM PDT 24
Finished Jul 07 05:35:09 PM PDT 24
Peak memory 205104 kb
Host smart-5eaa2a30-bb40-4d6b-9b14-751509416a0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357559308 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3357559308
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.3940863471
Short name T879
Test name
Test status
Simulation time 254060197 ps
CPU time 4.1 seconds
Started Jul 07 05:35:03 PM PDT 24
Finished Jul 07 05:35:08 PM PDT 24
Peak memory 204956 kb
Host smart-f855faf1-db9d-4bbb-8f60-961ed572c37e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940863471 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.3940863471
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.717998951
Short name T1125
Test name
Test status
Simulation time 23965295 ps
CPU time 0.63 seconds
Started Jul 07 05:35:08 PM PDT 24
Finished Jul 07 05:35:09 PM PDT 24
Peak memory 204600 kb
Host smart-b2eae0ac-af4e-4090-9a10-b616adccb9ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717998951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.717998951
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.943922861
Short name T948
Test name
Test status
Simulation time 560187194 ps
CPU time 4.85 seconds
Started Jul 07 05:35:03 PM PDT 24
Finished Jul 07 05:35:09 PM PDT 24
Peak memory 236512 kb
Host smart-1d081772-f394-4633-91bb-c00ebf858314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943922861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.943922861
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.2971461855
Short name T1314
Test name
Test status
Simulation time 900774079 ps
CPU time 12.81 seconds
Started Jul 07 05:35:01 PM PDT 24
Finished Jul 07 05:35:15 PM PDT 24
Peak memory 251440 kb
Host smart-dc9d8f3f-c025-400c-8e85-fb8e418fec8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971461855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.2971461855
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.1397114565
Short name T573
Test name
Test status
Simulation time 2819944773 ps
CPU time 84.05 seconds
Started Jul 07 05:35:03 PM PDT 24
Finished Jul 07 05:36:29 PM PDT 24
Peak memory 516440 kb
Host smart-032ff50e-7747-4500-b12d-2ecc8f092c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397114565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1397114565
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.1593777297
Short name T598
Test name
Test status
Simulation time 6632661392 ps
CPU time 44.52 seconds
Started Jul 07 05:35:01 PM PDT 24
Finished Jul 07 05:35:46 PM PDT 24
Peak memory 576016 kb
Host smart-ab6519a1-505a-4c55-a98f-451d60e45733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593777297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1593777297
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.649797336
Short name T952
Test name
Test status
Simulation time 122168109 ps
CPU time 1.19 seconds
Started Jul 07 05:35:01 PM PDT 24
Finished Jul 07 05:35:03 PM PDT 24
Peak memory 204784 kb
Host smart-04c86e6d-6404-41bf-acdc-17109639ea2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649797336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fm
t.649797336
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.3709042105
Short name T658
Test name
Test status
Simulation time 989837032 ps
CPU time 8.71 seconds
Started Jul 07 05:35:03 PM PDT 24
Finished Jul 07 05:35:13 PM PDT 24
Peak memory 204948 kb
Host smart-e36c9a07-35bb-4ef5-b671-2106d44613f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709042105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.3709042105
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.426263695
Short name T1303
Test name
Test status
Simulation time 4140532094 ps
CPU time 109.96 seconds
Started Jul 07 05:35:04 PM PDT 24
Finished Jul 07 05:36:55 PM PDT 24
Peak memory 1133060 kb
Host smart-48c8d4ea-103e-435b-9bde-a94009b7bff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426263695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.426263695
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.3154509972
Short name T1274
Test name
Test status
Simulation time 1994991128 ps
CPU time 20.7 seconds
Started Jul 07 05:35:05 PM PDT 24
Finished Jul 07 05:35:26 PM PDT 24
Peak memory 205064 kb
Host smart-438d37a9-fab4-437e-add6-a035eccc1a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154509972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3154509972
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.2549700682
Short name T1388
Test name
Test status
Simulation time 1044728402 ps
CPU time 17.89 seconds
Started Jul 07 05:35:09 PM PDT 24
Finished Jul 07 05:35:28 PM PDT 24
Peak memory 265104 kb
Host smart-64daee77-4be8-49e3-bb7b-ee9de6faf9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549700682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.2549700682
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.1042280273
Short name T1052
Test name
Test status
Simulation time 15118070 ps
CPU time 0.67 seconds
Started Jul 07 05:35:01 PM PDT 24
Finished Jul 07 05:35:02 PM PDT 24
Peak memory 204688 kb
Host smart-703dc27f-d682-4d2e-84a0-e1f08102f9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042280273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1042280273
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.555661051
Short name T1116
Test name
Test status
Simulation time 13064898696 ps
CPU time 142.13 seconds
Started Jul 07 05:35:05 PM PDT 24
Finished Jul 07 05:37:27 PM PDT 24
Peak memory 734664 kb
Host smart-d093754c-feb6-4215-a703-15a4f55df628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555661051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.555661051
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.3159809360
Short name T1135
Test name
Test status
Simulation time 78375573 ps
CPU time 1.63 seconds
Started Jul 07 05:35:04 PM PDT 24
Finished Jul 07 05:35:06 PM PDT 24
Peak memory 222768 kb
Host smart-4f2c5225-63b5-476d-b19b-e8ac7bac5702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159809360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.3159809360
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.2726939741
Short name T790
Test name
Test status
Simulation time 2006207271 ps
CPU time 100.98 seconds
Started Jul 07 05:35:02 PM PDT 24
Finished Jul 07 05:36:44 PM PDT 24
Peak memory 370920 kb
Host smart-779b5c68-ba38-4879-8ac4-ca45681e27b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726939741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2726939741
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.442577849
Short name T118
Test name
Test status
Simulation time 100656626231 ps
CPU time 1578.54 seconds
Started Jul 07 05:34:59 PM PDT 24
Finished Jul 07 06:01:19 PM PDT 24
Peak memory 4841864 kb
Host smart-6c9fb643-4a8b-45df-b146-09c6f725527e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442577849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.442577849
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.2325853495
Short name T1015
Test name
Test status
Simulation time 4576174641 ps
CPU time 26.61 seconds
Started Jul 07 05:35:03 PM PDT 24
Finished Jul 07 05:35:30 PM PDT 24
Peak memory 213312 kb
Host smart-c67514d3-819b-4607-894a-927d1f319d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325853495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.2325853495
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.4168568174
Short name T775
Test name
Test status
Simulation time 509453904 ps
CPU time 2.87 seconds
Started Jul 07 05:35:07 PM PDT 24
Finished Jul 07 05:35:10 PM PDT 24
Peak memory 205056 kb
Host smart-be65a4d9-68c0-4615-b27d-571d351f898e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168568174 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.4168568174
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1421153899
Short name T1095
Test name
Test status
Simulation time 189804640 ps
CPU time 1.13 seconds
Started Jul 07 05:35:08 PM PDT 24
Finished Jul 07 05:35:10 PM PDT 24
Peak memory 204768 kb
Host smart-31e8f18f-9a9b-444b-8b83-83482f806bcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421153899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1421153899
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.600489879
Short name T683
Test name
Test status
Simulation time 1620116652 ps
CPU time 2.52 seconds
Started Jul 07 05:35:06 PM PDT 24
Finished Jul 07 05:35:09 PM PDT 24
Peak memory 205068 kb
Host smart-f7bb3101-b82d-423e-acdd-c0df8fa69d19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600489879 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.600489879
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.71553220
Short name T178
Test name
Test status
Simulation time 598110175 ps
CPU time 1.37 seconds
Started Jul 07 05:35:12 PM PDT 24
Finished Jul 07 05:35:14 PM PDT 24
Peak memory 204788 kb
Host smart-69158f87-becc-4b2d-a09c-ba8292d2e3c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71553220 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.71553220
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.1252996243
Short name T427
Test name
Test status
Simulation time 1571399001 ps
CPU time 3.83 seconds
Started Jul 07 05:35:05 PM PDT 24
Finished Jul 07 05:35:09 PM PDT 24
Peak memory 205060 kb
Host smart-c66ef2bd-6c29-4343-ad0c-d4cff720d93b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252996243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.1252996243
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2090263699
Short name T913
Test name
Test status
Simulation time 1151034587 ps
CPU time 5.99 seconds
Started Jul 07 05:35:05 PM PDT 24
Finished Jul 07 05:35:11 PM PDT 24
Peak memory 214564 kb
Host smart-30aa19da-cf5b-408b-998e-37f4a189447c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090263699 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2090263699
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.1618734064
Short name T982
Test name
Test status
Simulation time 22395240096 ps
CPU time 174.74 seconds
Started Jul 07 05:35:07 PM PDT 24
Finished Jul 07 05:38:02 PM PDT 24
Peak memory 1956044 kb
Host smart-abbabab8-7592-4c4c-8c87-c653f3a67b08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618734064 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.1618734064
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.193441177
Short name T492
Test name
Test status
Simulation time 4090128494 ps
CPU time 15.97 seconds
Started Jul 07 05:35:05 PM PDT 24
Finished Jul 07 05:35:21 PM PDT 24
Peak memory 205140 kb
Host smart-aaf55446-af3b-47e7-ae03-d3ef69f0920b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193441177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_tar
get_smoke.193441177
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.1018240619
Short name T641
Test name
Test status
Simulation time 237272422 ps
CPU time 10.4 seconds
Started Jul 07 05:35:05 PM PDT 24
Finished Jul 07 05:35:16 PM PDT 24
Peak memory 204956 kb
Host smart-37009f43-a35e-4dae-8501-b6b6f4885b50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018240619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.1018240619
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.234355715
Short name T343
Test name
Test status
Simulation time 16936503926 ps
CPU time 8.9 seconds
Started Jul 07 05:35:04 PM PDT 24
Finished Jul 07 05:35:13 PM PDT 24
Peak memory 205060 kb
Host smart-08ee670b-06e7-40d5-adc5-cad04601fd9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234355715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_wr.234355715
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.302094361
Short name T718
Test name
Test status
Simulation time 2414696332 ps
CPU time 18.09 seconds
Started Jul 07 05:35:05 PM PDT 24
Finished Jul 07 05:35:23 PM PDT 24
Peak memory 270276 kb
Host smart-ce4d459b-8f41-4218-bb5e-a0c2c8160a12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302094361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_t
arget_stretch.302094361
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.4179075943
Short name T617
Test name
Test status
Simulation time 11891422080 ps
CPU time 7.2 seconds
Started Jul 07 05:35:13 PM PDT 24
Finished Jul 07 05:35:20 PM PDT 24
Peak memory 213600 kb
Host smart-41f230fb-1017-4f8f-80a9-33cacfcf0a32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179075943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.4179075943
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.1889027677
Short name T1055
Test name
Test status
Simulation time 119120238 ps
CPU time 2.3 seconds
Started Jul 07 05:35:11 PM PDT 24
Finished Jul 07 05:35:14 PM PDT 24
Peak memory 205008 kb
Host smart-ed0d0480-a7d4-4815-9f95-9fc03d5172b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889027677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.1889027677
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.61007084
Short name T526
Test name
Test status
Simulation time 47326104 ps
CPU time 0.64 seconds
Started Jul 07 05:35:20 PM PDT 24
Finished Jul 07 05:35:21 PM PDT 24
Peak memory 204596 kb
Host smart-42b8be38-c6ce-44c9-baac-cb30a01822d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61007084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.61007084
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.2613701300
Short name T839
Test name
Test status
Simulation time 115461506 ps
CPU time 2.49 seconds
Started Jul 07 05:35:09 PM PDT 24
Finished Jul 07 05:35:12 PM PDT 24
Peak memory 220844 kb
Host smart-3df4aec1-931b-4cb6-9e7e-e8bcc3098eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613701300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.2613701300
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.3274273669
Short name T1281
Test name
Test status
Simulation time 1397587065 ps
CPU time 6.35 seconds
Started Jul 07 05:35:12 PM PDT 24
Finished Jul 07 05:35:19 PM PDT 24
Peak memory 260256 kb
Host smart-fe08a7d4-542f-4f3c-93be-1c1b9d24937b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274273669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.3274273669
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.3576517160
Short name T1033
Test name
Test status
Simulation time 12191940886 ps
CPU time 68.27 seconds
Started Jul 07 05:35:10 PM PDT 24
Finished Jul 07 05:36:18 PM PDT 24
Peak memory 722396 kb
Host smart-50c521fb-78e0-42d8-827d-349708b99fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576517160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3576517160
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.3063999476
Short name T788
Test name
Test status
Simulation time 2239337536 ps
CPU time 65.73 seconds
Started Jul 07 05:35:09 PM PDT 24
Finished Jul 07 05:36:15 PM PDT 24
Peak memory 725520 kb
Host smart-442c9efe-aa1e-4dd4-9383-b527a77877a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063999476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3063999476
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2254682850
Short name T1365
Test name
Test status
Simulation time 265863070 ps
CPU time 1.09 seconds
Started Jul 07 05:35:10 PM PDT 24
Finished Jul 07 05:35:11 PM PDT 24
Peak memory 204680 kb
Host smart-4cf3a59c-6366-49be-a786-740617aa9faf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254682850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2254682850
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.3570767456
Short name T1374
Test name
Test status
Simulation time 529274541 ps
CPU time 3.83 seconds
Started Jul 07 05:35:06 PM PDT 24
Finished Jul 07 05:35:10 PM PDT 24
Peak memory 229336 kb
Host smart-ad59383b-28a6-41c2-aa55-d8e32999acd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570767456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.3570767456
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.1782756054
Short name T1038
Test name
Test status
Simulation time 4445888228 ps
CPU time 315.18 seconds
Started Jul 07 05:35:13 PM PDT 24
Finished Jul 07 05:40:29 PM PDT 24
Peak memory 1289444 kb
Host smart-832e4bbb-3a9d-488f-9848-930e1249a26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782756054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1782756054
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.3757720254
Short name T1260
Test name
Test status
Simulation time 4597556238 ps
CPU time 34.39 seconds
Started Jul 07 05:35:14 PM PDT 24
Finished Jul 07 05:35:49 PM PDT 24
Peak memory 372440 kb
Host smart-9e3b7a41-b9b0-46d9-b999-583afad76793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757720254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.3757720254
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.4138038149
Short name T139
Test name
Test status
Simulation time 88190926 ps
CPU time 0.67 seconds
Started Jul 07 05:35:13 PM PDT 24
Finished Jul 07 05:35:14 PM PDT 24
Peak memory 204680 kb
Host smart-f77b1f67-6dd2-4cd0-8ae2-b073d88d935a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138038149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.4138038149
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1747094936
Short name T962
Test name
Test status
Simulation time 12695181776 ps
CPU time 171.5 seconds
Started Jul 07 05:35:12 PM PDT 24
Finished Jul 07 05:38:04 PM PDT 24
Peak memory 205096 kb
Host smart-48053a62-5ad1-4287-bec6-5ce9cec5ee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747094936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1747094936
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.1850026071
Short name T907
Test name
Test status
Simulation time 221268571 ps
CPU time 2.07 seconds
Started Jul 07 05:35:12 PM PDT 24
Finished Jul 07 05:35:14 PM PDT 24
Peak memory 213224 kb
Host smart-b73f7662-b6cc-40e6-86c6-cad69845878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850026071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.1850026071
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.3502404221
Short name T966
Test name
Test status
Simulation time 6006831996 ps
CPU time 31.76 seconds
Started Jul 07 05:35:12 PM PDT 24
Finished Jul 07 05:35:44 PM PDT 24
Peak memory 379256 kb
Host smart-b2f6607b-6034-4eb4-a943-dde43b92c20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502404221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.3502404221
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.1574031662
Short name T120
Test name
Test status
Simulation time 40436858529 ps
CPU time 906.5 seconds
Started Jul 07 05:35:10 PM PDT 24
Finished Jul 07 05:50:17 PM PDT 24
Peak memory 3338592 kb
Host smart-af4c4977-0101-4141-930c-cea823f301f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574031662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.1574031662
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.3643964514
Short name T1503
Test name
Test status
Simulation time 719724566 ps
CPU time 14.48 seconds
Started Jul 07 05:35:08 PM PDT 24
Finished Jul 07 05:35:23 PM PDT 24
Peak memory 221348 kb
Host smart-98e4b3ba-fc96-4790-8c20-029b427b3707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643964514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.3643964514
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.2789684775
Short name T624
Test name
Test status
Simulation time 2109522816 ps
CPU time 3.07 seconds
Started Jul 07 05:35:08 PM PDT 24
Finished Jul 07 05:35:12 PM PDT 24
Peak memory 204896 kb
Host smart-1c875809-01b6-4a93-b923-cd0061872c9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789684775 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.2789684775
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.87533222
Short name T155
Test name
Test status
Simulation time 757848509 ps
CPU time 1.29 seconds
Started Jul 07 05:35:09 PM PDT 24
Finished Jul 07 05:35:11 PM PDT 24
Peak memory 205084 kb
Host smart-a54e3391-09cf-42af-b010-b5954e8fa87e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87533222 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_fifo_reset_acq.87533222
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1625974126
Short name T706
Test name
Test status
Simulation time 776674791 ps
CPU time 1.37 seconds
Started Jul 07 05:35:08 PM PDT 24
Finished Jul 07 05:35:10 PM PDT 24
Peak memory 204960 kb
Host smart-fedde0fa-c0cc-479b-b509-93e867d3cce9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625974126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1625974126
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.164432337
Short name T946
Test name
Test status
Simulation time 4941354403 ps
CPU time 2.85 seconds
Started Jul 07 05:35:14 PM PDT 24
Finished Jul 07 05:35:17 PM PDT 24
Peak memory 204916 kb
Host smart-3d7a59fa-7932-4539-9d66-3fe46f20c833
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164432337 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.164432337
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.2518824820
Short name T1392
Test name
Test status
Simulation time 284342822 ps
CPU time 1.26 seconds
Started Jul 07 05:35:17 PM PDT 24
Finished Jul 07 05:35:19 PM PDT 24
Peak memory 204808 kb
Host smart-580795d5-f9ce-4eb7-91a0-df22edffd0d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518824820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.2518824820
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.4136910852
Short name T308
Test name
Test status
Simulation time 280051904 ps
CPU time 2.7 seconds
Started Jul 07 05:35:13 PM PDT 24
Finished Jul 07 05:35:17 PM PDT 24
Peak memory 205068 kb
Host smart-262be374-9cd0-476c-854d-e87d3368d28a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136910852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.4136910852
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3719007707
Short name T13
Test name
Test status
Simulation time 1371931247 ps
CPU time 7.61 seconds
Started Jul 07 05:35:11 PM PDT 24
Finished Jul 07 05:35:19 PM PDT 24
Peak memory 213296 kb
Host smart-7dddb523-b681-4b3e-acbd-446e110ee426
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719007707 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3719007707
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.4289090341
Short name T910
Test name
Test status
Simulation time 5925463337 ps
CPU time 5.57 seconds
Started Jul 07 05:35:11 PM PDT 24
Finished Jul 07 05:35:17 PM PDT 24
Peak memory 205088 kb
Host smart-ab903929-b2ad-4c1c-9da6-abbcc1e5c754
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289090341 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.4289090341
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.3884191777
Short name T396
Test name
Test status
Simulation time 750622070 ps
CPU time 23.07 seconds
Started Jul 07 05:35:10 PM PDT 24
Finished Jul 07 05:35:34 PM PDT 24
Peak memory 205056 kb
Host smart-d61aa956-2593-40a9-aaec-7f216f4192ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884191777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.3884191777
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.561062350
Short name T881
Test name
Test status
Simulation time 451172252 ps
CPU time 16.61 seconds
Started Jul 07 05:35:14 PM PDT 24
Finished Jul 07 05:35:31 PM PDT 24
Peak memory 205056 kb
Host smart-f668dcd8-b2de-45a9-83e2-c224ec357137
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561062350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_rd.561062350
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.2633119314
Short name T418
Test name
Test status
Simulation time 55275910829 ps
CPU time 1443.45 seconds
Started Jul 07 05:35:13 PM PDT 24
Finished Jul 07 05:59:18 PM PDT 24
Peak memory 8696064 kb
Host smart-c0f8c375-f131-4a9f-9bff-82fca6b28a9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633119314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.2633119314
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.2208073560
Short name T747
Test name
Test status
Simulation time 1081716627 ps
CPU time 1.63 seconds
Started Jul 07 05:35:10 PM PDT 24
Finished Jul 07 05:35:11 PM PDT 24
Peak memory 205016 kb
Host smart-da924156-3b5d-4b5b-9533-74f4283d1253
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208073560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.2208073560
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2245207749
Short name T1396
Test name
Test status
Simulation time 5398172435 ps
CPU time 7.7 seconds
Started Jul 07 05:35:12 PM PDT 24
Finished Jul 07 05:35:20 PM PDT 24
Peak memory 213284 kb
Host smart-24b237e5-d734-4b8f-998b-d02f9b49c517
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245207749 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2245207749
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.3287700032
Short name T815
Test name
Test status
Simulation time 149675074 ps
CPU time 2.52 seconds
Started Jul 07 05:35:16 PM PDT 24
Finished Jul 07 05:35:19 PM PDT 24
Peak memory 213212 kb
Host smart-3725d3e7-f42d-43db-93bf-cdd01c1dcb36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287700032 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.3287700032
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.1207092087
Short name T1443
Test name
Test status
Simulation time 81449469 ps
CPU time 1.41 seconds
Started Jul 07 05:35:17 PM PDT 24
Finished Jul 07 05:35:19 PM PDT 24
Peak memory 221456 kb
Host smart-0f228d54-a985-425b-bbca-65262d9afc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207092087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1207092087
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2621050139
Short name T765
Test name
Test status
Simulation time 350519356 ps
CPU time 18.16 seconds
Started Jul 07 05:35:13 PM PDT 24
Finished Jul 07 05:35:31 PM PDT 24
Peak memory 274000 kb
Host smart-1dc486b1-4b35-41f6-a77e-92104c63e6c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621050139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2621050139
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.3919892439
Short name T211
Test name
Test status
Simulation time 21017949336 ps
CPU time 39.69 seconds
Started Jul 07 05:35:17 PM PDT 24
Finished Jul 07 05:35:57 PM PDT 24
Peak memory 369780 kb
Host smart-3c601976-eff6-4965-9b37-376b9c078683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919892439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.3919892439
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.815743018
Short name T181
Test name
Test status
Simulation time 4655179920 ps
CPU time 80 seconds
Started Jul 07 05:35:12 PM PDT 24
Finished Jul 07 05:36:33 PM PDT 24
Peak memory 764516 kb
Host smart-89b79c7f-fc97-4208-ad72-c2bdd110ff16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815743018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.815743018
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.1416248476
Short name T1522
Test name
Test status
Simulation time 140297832 ps
CPU time 1.16 seconds
Started Jul 07 05:35:12 PM PDT 24
Finished Jul 07 05:35:14 PM PDT 24
Peak memory 204760 kb
Host smart-9171734f-68c8-4db1-b7d3-2e312d4af7d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416248476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.1416248476
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.3207252451
Short name T534
Test name
Test status
Simulation time 126930708 ps
CPU time 3.18 seconds
Started Jul 07 05:35:13 PM PDT 24
Finished Jul 07 05:35:17 PM PDT 24
Peak memory 205032 kb
Host smart-26c01496-5089-4fbd-aaed-30f58a07090b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207252451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.3207252451
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.2365969246
Short name T1138
Test name
Test status
Simulation time 51239624360 ps
CPU time 129.45 seconds
Started Jul 07 05:35:16 PM PDT 24
Finished Jul 07 05:37:25 PM PDT 24
Peak memory 1447712 kb
Host smart-1bf451bf-f60e-4ca2-bb53-12d24b3154a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365969246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2365969246
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.333051743
Short name T721
Test name
Test status
Simulation time 1963164678 ps
CPU time 8.11 seconds
Started Jul 07 05:35:20 PM PDT 24
Finished Jul 07 05:35:29 PM PDT 24
Peak memory 205012 kb
Host smart-60d4b7b4-1f10-4e5d-9dd7-3bbcad26347c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333051743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.333051743
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.241241484
Short name T65
Test name
Test status
Simulation time 1734856662 ps
CPU time 32.65 seconds
Started Jul 07 05:35:18 PM PDT 24
Finished Jul 07 05:35:51 PM PDT 24
Peak memory 316408 kb
Host smart-da788cb5-2000-46fb-8513-75e14c12c418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241241484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.241241484
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2956813633
Short name T337
Test name
Test status
Simulation time 2794500394 ps
CPU time 71.95 seconds
Started Jul 07 05:35:13 PM PDT 24
Finished Jul 07 05:36:25 PM PDT 24
Peak memory 214364 kb
Host smart-d0a1fbb7-f88e-46bb-b8cf-49d64dd29e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956813633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2956813633
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.3703870300
Short name T188
Test name
Test status
Simulation time 51518531 ps
CPU time 1.26 seconds
Started Jul 07 05:35:13 PM PDT 24
Finished Jul 07 05:35:15 PM PDT 24
Peak memory 205540 kb
Host smart-08635cf6-de23-436a-b8ce-6beb225ac1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703870300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.3703870300
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1984218261
Short name T1180
Test name
Test status
Simulation time 1620068161 ps
CPU time 82.15 seconds
Started Jul 07 05:35:13 PM PDT 24
Finished Jul 07 05:36:36 PM PDT 24
Peak memory 390256 kb
Host smart-98881a4c-31f0-4424-837f-806a2f8ee19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984218261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1984218261
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.3125220203
Short name T291
Test name
Test status
Simulation time 58204955543 ps
CPU time 957.42 seconds
Started Jul 07 05:35:14 PM PDT 24
Finished Jul 07 05:51:12 PM PDT 24
Peak memory 2174548 kb
Host smart-8351c34d-e91a-44d4-b2ec-f03c1ce7ce34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125220203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.3125220203
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.569667641
Short name T389
Test name
Test status
Simulation time 5831141202 ps
CPU time 9.73 seconds
Started Jul 07 05:35:20 PM PDT 24
Finished Jul 07 05:35:30 PM PDT 24
Peak memory 213296 kb
Host smart-5310220a-3715-4b95-bcdb-dd4ed2f08671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569667641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.569667641
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.911291461
Short name T166
Test name
Test status
Simulation time 2665289949 ps
CPU time 3.5 seconds
Started Jul 07 05:35:17 PM PDT 24
Finished Jul 07 05:35:21 PM PDT 24
Peak memory 205088 kb
Host smart-e77bbeae-04bc-4a94-9a27-6e474b3e21b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911291461 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.911291461
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.829120223
Short name T1045
Test name
Test status
Simulation time 174385129 ps
CPU time 1.24 seconds
Started Jul 07 05:35:18 PM PDT 24
Finished Jul 07 05:35:20 PM PDT 24
Peak memory 213152 kb
Host smart-3cc58570-4a06-467d-8c58-55329096276f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829120223 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_acq.829120223
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.58028316
Short name T853
Test name
Test status
Simulation time 210951887 ps
CPU time 0.83 seconds
Started Jul 07 05:35:21 PM PDT 24
Finished Jul 07 05:35:23 PM PDT 24
Peak memory 212996 kb
Host smart-a3fd1a23-266b-40eb-958e-37c937b33632
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58028316 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_fifo_reset_tx.58028316
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.1300721321
Short name T1299
Test name
Test status
Simulation time 635047194 ps
CPU time 2.86 seconds
Started Jul 07 05:35:18 PM PDT 24
Finished Jul 07 05:35:21 PM PDT 24
Peak memory 204936 kb
Host smart-fdd2f01b-1728-48cb-90d9-2767f2ccb733
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300721321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.1300721321
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.1659050668
Short name T835
Test name
Test status
Simulation time 459717783 ps
CPU time 1.18 seconds
Started Jul 07 05:35:18 PM PDT 24
Finished Jul 07 05:35:20 PM PDT 24
Peak memory 204772 kb
Host smart-13ca9252-5f06-4043-95a9-7a20e4176673
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659050668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.1659050668
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.2036130633
Short name T1328
Test name
Test status
Simulation time 7546031482 ps
CPU time 6.13 seconds
Started Jul 07 05:35:21 PM PDT 24
Finished Jul 07 05:35:27 PM PDT 24
Peak memory 219004 kb
Host smart-d01e1f10-4ee9-4d3f-ab5e-8ad27fee46b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036130633 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.2036130633
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.2649850167
Short name T773
Test name
Test status
Simulation time 3867557876 ps
CPU time 2.98 seconds
Started Jul 07 05:35:16 PM PDT 24
Finished Jul 07 05:35:19 PM PDT 24
Peak memory 205092 kb
Host smart-4bb42dd8-bc41-451a-ae90-0ea0f6eafe0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649850167 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.2649850167
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.305758816
Short name T1384
Test name
Test status
Simulation time 752849062 ps
CPU time 5.15 seconds
Started Jul 07 05:35:13 PM PDT 24
Finished Jul 07 05:35:19 PM PDT 24
Peak memory 205016 kb
Host smart-b9cb06c0-8a7d-40fe-a374-e0dea9ccc1ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305758816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_tar
get_smoke.305758816
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3078976971
Short name T1120
Test name
Test status
Simulation time 768501317 ps
CPU time 6.66 seconds
Started Jul 07 05:35:20 PM PDT 24
Finished Jul 07 05:35:28 PM PDT 24
Peak memory 204984 kb
Host smart-70a00df4-de57-4929-bae5-909bb173b66e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078976971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3078976971
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.2258828428
Short name T20
Test name
Test status
Simulation time 64526239468 ps
CPU time 293.87 seconds
Started Jul 07 05:35:15 PM PDT 24
Finished Jul 07 05:40:10 PM PDT 24
Peak memory 2872036 kb
Host smart-9d12de08-39dd-4863-8f45-8213b606acd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258828428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.2258828428
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.2004593178
Short name T477
Test name
Test status
Simulation time 929162709 ps
CPU time 13.98 seconds
Started Jul 07 05:35:16 PM PDT 24
Finished Jul 07 05:35:31 PM PDT 24
Peak memory 358120 kb
Host smart-1768d5a5-70ca-470c-a3c0-488c40c7d0d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004593178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.2004593178
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.1634794579
Short name T656
Test name
Test status
Simulation time 2467442768 ps
CPU time 7.02 seconds
Started Jul 07 05:35:19 PM PDT 24
Finished Jul 07 05:35:27 PM PDT 24
Peak memory 213176 kb
Host smart-f4711c61-5ddd-41eb-9b46-8d53fe08c2a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634794579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.1634794579
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.1588122029
Short name T623
Test name
Test status
Simulation time 97284512 ps
CPU time 1.81 seconds
Started Jul 07 05:35:16 PM PDT 24
Finished Jul 07 05:35:19 PM PDT 24
Peak memory 205004 kb
Host smart-605a772b-094e-496c-8d35-91e415228e1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588122029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.1588122029
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3394066419
Short name T456
Test name
Test status
Simulation time 35080192 ps
CPU time 0.61 seconds
Started Jul 07 05:35:24 PM PDT 24
Finished Jul 07 05:35:25 PM PDT 24
Peak memory 204576 kb
Host smart-4b6009b5-e9d6-4d83-9200-1708128a07aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394066419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3394066419
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3498354860
Short name T1088
Test name
Test status
Simulation time 2216459848 ps
CPU time 2.94 seconds
Started Jul 07 05:35:24 PM PDT 24
Finished Jul 07 05:35:27 PM PDT 24
Peak memory 213356 kb
Host smart-c84e32c2-f0d3-4518-98b6-c4a1813931fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498354860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3498354860
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.3717862934
Short name T696
Test name
Test status
Simulation time 1616487311 ps
CPU time 8.68 seconds
Started Jul 07 05:35:18 PM PDT 24
Finished Jul 07 05:35:26 PM PDT 24
Peak memory 301536 kb
Host smart-bd8bdc50-54fa-43d6-8a69-dbba99cdad8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717862934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.3717862934
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.4271761576
Short name T959
Test name
Test status
Simulation time 5602364161 ps
CPU time 186.5 seconds
Started Jul 07 05:35:19 PM PDT 24
Finished Jul 07 05:38:26 PM PDT 24
Peak memory 770752 kb
Host smart-52656bc6-9e06-4552-9e71-ec29e3052e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271761576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.4271761576
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.246500366
Short name T1058
Test name
Test status
Simulation time 11298611910 ps
CPU time 109.09 seconds
Started Jul 07 05:35:17 PM PDT 24
Finished Jul 07 05:37:06 PM PDT 24
Peak memory 882856 kb
Host smart-b5a3d5ca-09aa-424b-b96f-15c20796510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246500366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.246500366
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.1383617741
Short name T1438
Test name
Test status
Simulation time 578705045 ps
CPU time 1.23 seconds
Started Jul 07 05:35:19 PM PDT 24
Finished Jul 07 05:35:21 PM PDT 24
Peak memory 204804 kb
Host smart-f824201a-e4dc-4072-aea8-ebe562a72c13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383617741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.1383617741
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2326232749
Short name T1246
Test name
Test status
Simulation time 117709917 ps
CPU time 6.46 seconds
Started Jul 07 05:35:17 PM PDT 24
Finished Jul 07 05:35:24 PM PDT 24
Peak memory 222652 kb
Host smart-85c064a9-549a-4936-8bd6-79a8369bad9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326232749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2326232749
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.4089424447
Short name T417
Test name
Test status
Simulation time 3317114480 ps
CPU time 185.32 seconds
Started Jul 07 05:35:17 PM PDT 24
Finished Jul 07 05:38:23 PM PDT 24
Peak memory 834684 kb
Host smart-baa3d36a-be72-460f-a564-bfef5dd1774a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089424447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.4089424447
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.1512039016
Short name T447
Test name
Test status
Simulation time 355622589 ps
CPU time 2.55 seconds
Started Jul 07 05:35:20 PM PDT 24
Finished Jul 07 05:35:23 PM PDT 24
Peak memory 205000 kb
Host smart-e6edafa4-38d9-4959-b57d-ebff820cfa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512039016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.1512039016
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.2417722415
Short name T1421
Test name
Test status
Simulation time 2679486653 ps
CPU time 27.47 seconds
Started Jul 07 05:35:19 PM PDT 24
Finished Jul 07 05:35:47 PM PDT 24
Peak memory 356304 kb
Host smart-6e17797d-bbc8-4cf9-ad99-1e4c9f0fd6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417722415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2417722415
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.3550164599
Short name T1248
Test name
Test status
Simulation time 27884253 ps
CPU time 0.67 seconds
Started Jul 07 05:35:20 PM PDT 24
Finished Jul 07 05:35:21 PM PDT 24
Peak memory 204688 kb
Host smart-17549f9d-e1e8-4593-85aa-1dc21a4e2fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550164599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3550164599
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.3749206047
Short name T651
Test name
Test status
Simulation time 210369482 ps
CPU time 4.73 seconds
Started Jul 07 05:35:18 PM PDT 24
Finished Jul 07 05:35:23 PM PDT 24
Peak memory 221200 kb
Host smart-221afee2-346b-468b-87e8-585371ac9b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749206047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.3749206047
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.1964089833
Short name T162
Test name
Test status
Simulation time 6095525935 ps
CPU time 47.67 seconds
Started Jul 07 05:35:21 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 204984 kb
Host smart-bbc3d3db-d06c-46b9-991c-6f3d04d117a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964089833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.1964089833
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.2623262541
Short name T868
Test name
Test status
Simulation time 5215224480 ps
CPU time 28.89 seconds
Started Jul 07 05:35:16 PM PDT 24
Finished Jul 07 05:35:45 PM PDT 24
Peak memory 388732 kb
Host smart-ded070f4-aaed-4848-916e-442a379136d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623262541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2623262541
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.3731648917
Short name T288
Test name
Test status
Simulation time 31618612949 ps
CPU time 618.53 seconds
Started Jul 07 05:35:27 PM PDT 24
Finished Jul 07 05:45:46 PM PDT 24
Peak memory 1566432 kb
Host smart-6931deee-2303-4658-9e8a-aedfa9263c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731648917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.3731648917
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3341240362
Short name T734
Test name
Test status
Simulation time 786842163 ps
CPU time 34.65 seconds
Started Jul 07 05:35:21 PM PDT 24
Finished Jul 07 05:35:56 PM PDT 24
Peak memory 213232 kb
Host smart-65698cf9-4a7e-4b44-9326-2ee3227dd936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341240362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3341240362
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.2307055160
Short name T1331
Test name
Test status
Simulation time 2570881506 ps
CPU time 3.54 seconds
Started Jul 07 05:35:21 PM PDT 24
Finished Jul 07 05:35:25 PM PDT 24
Peak memory 213248 kb
Host smart-7733e2ca-e796-4c58-89cf-e0cd6ba2e636
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307055160 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.2307055160
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3185799269
Short name T866
Test name
Test status
Simulation time 630843703 ps
CPU time 0.78 seconds
Started Jul 07 05:35:25 PM PDT 24
Finished Jul 07 05:35:26 PM PDT 24
Peak memory 205080 kb
Host smart-5f2d3846-9b79-4b2d-8196-0b7815c50498
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185799269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3185799269
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.1220162406
Short name T697
Test name
Test status
Simulation time 264753664 ps
CPU time 1.19 seconds
Started Jul 07 05:35:22 PM PDT 24
Finished Jul 07 05:35:23 PM PDT 24
Peak memory 205008 kb
Host smart-2f7209c0-1857-41d0-8eca-9b22d5bbc8ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220162406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.1220162406
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.1700683093
Short name T190
Test name
Test status
Simulation time 519784560 ps
CPU time 2.57 seconds
Started Jul 07 05:35:21 PM PDT 24
Finished Jul 07 05:35:24 PM PDT 24
Peak memory 205016 kb
Host smart-2dc41ad4-cb77-44bc-b8d7-9f78163fa2b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700683093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.1700683093
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.422518311
Short name T1358
Test name
Test status
Simulation time 134013451 ps
CPU time 1.23 seconds
Started Jul 07 05:35:23 PM PDT 24
Finished Jul 07 05:35:25 PM PDT 24
Peak memory 204792 kb
Host smart-5c585b76-42ac-472d-8246-d6c77c2efa03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422518311 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.422518311
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.2505609562
Short name T675
Test name
Test status
Simulation time 394763658 ps
CPU time 4.9 seconds
Started Jul 07 05:35:23 PM PDT 24
Finished Jul 07 05:35:28 PM PDT 24
Peak memory 204932 kb
Host smart-e431a99c-f5f4-4236-8b6c-5654ad446bb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505609562 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.2505609562
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2211377348
Short name T682
Test name
Test status
Simulation time 1692632539 ps
CPU time 4.2 seconds
Started Jul 07 05:35:25 PM PDT 24
Finished Jul 07 05:35:29 PM PDT 24
Peak memory 205924 kb
Host smart-6c45c8c1-9469-4022-922c-2d76a00bcab2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211377348 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2211377348
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.1642035668
Short name T899
Test name
Test status
Simulation time 7121396756 ps
CPU time 11.22 seconds
Started Jul 07 05:35:25 PM PDT 24
Finished Jul 07 05:35:36 PM PDT 24
Peak memory 205076 kb
Host smart-3ecd6da4-d8d1-44fb-88b1-c7ca55daaac1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642035668 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1642035668
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.1887575089
Short name T536
Test name
Test status
Simulation time 6525950885 ps
CPU time 13.82 seconds
Started Jul 07 05:35:21 PM PDT 24
Finished Jul 07 05:35:35 PM PDT 24
Peak memory 204956 kb
Host smart-961c10c9-c09b-4317-a2c4-c75e298ae579
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887575089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.1887575089
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.1475420815
Short name T314
Test name
Test status
Simulation time 4199067839 ps
CPU time 43.62 seconds
Started Jul 07 05:35:22 PM PDT 24
Finished Jul 07 05:36:06 PM PDT 24
Peak memory 206236 kb
Host smart-5ae5ff6b-8367-418f-bcd6-e495dfba24fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475420815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.1475420815
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.37463505
Short name T588
Test name
Test status
Simulation time 26690971301 ps
CPU time 19.89 seconds
Started Jul 07 05:35:21 PM PDT 24
Finished Jul 07 05:35:41 PM PDT 24
Peak memory 440360 kb
Host smart-0f1f1d6b-d9d2-49c3-a433-a3749374fc5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37463505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stress_wr.37463505
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2471164224
Short name T1484
Test name
Test status
Simulation time 1589631525 ps
CPU time 5.72 seconds
Started Jul 07 05:35:22 PM PDT 24
Finished Jul 07 05:35:28 PM PDT 24
Peak memory 258136 kb
Host smart-c33d89a7-a457-4840-89fb-4de694e6c7f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471164224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2471164224
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.2827992228
Short name T547
Test name
Test status
Simulation time 1401028171 ps
CPU time 7.64 seconds
Started Jul 07 05:35:22 PM PDT 24
Finished Jul 07 05:35:30 PM PDT 24
Peak memory 221220 kb
Host smart-d234a793-9f7a-4d61-b2e6-8426a1fe4b35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827992228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.2827992228
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.2948953685
Short name T1436
Test name
Test status
Simulation time 72727673 ps
CPU time 1.09 seconds
Started Jul 07 05:35:27 PM PDT 24
Finished Jul 07 05:35:29 PM PDT 24
Peak memory 205024 kb
Host smart-4734c2db-505f-4650-b078-5aed010d4ac4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948953685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.2948953685
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2088827925
Short name T1093
Test name
Test status
Simulation time 20802211 ps
CPU time 0.62 seconds
Started Jul 07 05:35:28 PM PDT 24
Finished Jul 07 05:35:29 PM PDT 24
Peak memory 204596 kb
Host smart-e73520c4-66b5-43a2-9f57-ded706ac7429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088827925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2088827925
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.616825906
Short name T687
Test name
Test status
Simulation time 191214669 ps
CPU time 3.21 seconds
Started Jul 07 05:35:23 PM PDT 24
Finished Jul 07 05:35:26 PM PDT 24
Peak memory 223260 kb
Host smart-4577198a-5f92-422b-8da8-55af6b98fb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616825906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.616825906
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.3634602278
Short name T372
Test name
Test status
Simulation time 1588247624 ps
CPU time 17.1 seconds
Started Jul 07 05:35:25 PM PDT 24
Finished Jul 07 05:35:43 PM PDT 24
Peak memory 211012 kb
Host smart-da98572b-37c2-4ac7-97b7-4759564eb499
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634602278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.3634602278
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.820166507
Short name T187
Test name
Test status
Simulation time 4129713629 ps
CPU time 147.62 seconds
Started Jul 07 05:35:22 PM PDT 24
Finished Jul 07 05:37:50 PM PDT 24
Peak memory 708536 kb
Host smart-24fb2550-62ee-4930-b906-0245657c3b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820166507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.820166507
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3643941265
Short name T1075
Test name
Test status
Simulation time 8316959148 ps
CPU time 72.8 seconds
Started Jul 07 05:35:32 PM PDT 24
Finished Jul 07 05:36:45 PM PDT 24
Peak memory 705572 kb
Host smart-b458899a-6957-454b-ad15-3c6986a72510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643941265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3643941265
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.3016461756
Short name T239
Test name
Test status
Simulation time 635228790 ps
CPU time 0.85 seconds
Started Jul 07 05:35:24 PM PDT 24
Finished Jul 07 05:35:25 PM PDT 24
Peak memory 204728 kb
Host smart-e2379346-5c7a-45c5-97fe-37ad53ab2429
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016461756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.3016461756
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.3951863399
Short name T1223
Test name
Test status
Simulation time 182848053 ps
CPU time 9.59 seconds
Started Jul 07 05:35:28 PM PDT 24
Finished Jul 07 05:35:38 PM PDT 24
Peak memory 235760 kb
Host smart-cbc86f4a-992f-4b49-a1b1-0f7c872a48d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951863399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.3951863399
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.708028555
Short name T1189
Test name
Test status
Simulation time 3869471301 ps
CPU time 91.51 seconds
Started Jul 07 05:35:25 PM PDT 24
Finished Jul 07 05:36:57 PM PDT 24
Peak memory 1122644 kb
Host smart-6e665c3b-90f3-4072-8bd3-246caca556fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708028555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.708028555
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.3991307992
Short name T1337
Test name
Test status
Simulation time 476999713 ps
CPU time 4.65 seconds
Started Jul 07 05:35:26 PM PDT 24
Finished Jul 07 05:35:31 PM PDT 24
Peak memory 205012 kb
Host smart-e934c851-d323-40f4-942d-566aa10138d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991307992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.3991307992
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.2749738199
Short name T672
Test name
Test status
Simulation time 2766588919 ps
CPU time 145.99 seconds
Started Jul 07 05:35:28 PM PDT 24
Finished Jul 07 05:37:55 PM PDT 24
Peak memory 471988 kb
Host smart-c44b328a-2123-4cdb-b749-477320d11971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749738199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.2749738199
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.1727216517
Short name T140
Test name
Test status
Simulation time 32974915 ps
CPU time 0.67 seconds
Started Jul 07 05:35:27 PM PDT 24
Finished Jul 07 05:35:28 PM PDT 24
Peak memory 204704 kb
Host smart-6f7e1ea0-df26-4feb-a116-b4e498b6fb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727216517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1727216517
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.4085711287
Short name T400
Test name
Test status
Simulation time 473478486 ps
CPU time 6.01 seconds
Started Jul 07 05:35:25 PM PDT 24
Finished Jul 07 05:35:32 PM PDT 24
Peak memory 237640 kb
Host smart-559cd400-9722-4c17-ba2b-535edeb2cf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085711287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.4085711287
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.3927603318
Short name T1389
Test name
Test status
Simulation time 23382720364 ps
CPU time 496.61 seconds
Started Jul 07 05:35:22 PM PDT 24
Finished Jul 07 05:43:39 PM PDT 24
Peak memory 205044 kb
Host smart-c33b0ccb-4c43-4167-b1d9-9c7a554df053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927603318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.3927603318
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.3840240114
Short name T305
Test name
Test status
Simulation time 5347880417 ps
CPU time 60.57 seconds
Started Jul 07 05:35:27 PM PDT 24
Finished Jul 07 05:36:28 PM PDT 24
Peak memory 301392 kb
Host smart-137e12d7-abca-4865-acfc-3e22cd860c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840240114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.3840240114
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.2617266060
Short name T356
Test name
Test status
Simulation time 708370458 ps
CPU time 12.53 seconds
Started Jul 07 05:35:25 PM PDT 24
Finished Jul 07 05:35:38 PM PDT 24
Peak memory 213220 kb
Host smart-07bfab08-3c01-419d-b7bb-f8e91493faa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617266060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2617266060
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3569120363
Short name T1308
Test name
Test status
Simulation time 4215654750 ps
CPU time 5.01 seconds
Started Jul 07 05:35:30 PM PDT 24
Finished Jul 07 05:35:35 PM PDT 24
Peak memory 213312 kb
Host smart-74b459b8-e3f1-49f6-9a40-bf9c1f150d79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569120363 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3569120363
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2573574929
Short name T507
Test name
Test status
Simulation time 421654673 ps
CPU time 1.5 seconds
Started Jul 07 05:35:37 PM PDT 24
Finished Jul 07 05:35:39 PM PDT 24
Peak memory 209972 kb
Host smart-2766ba29-7d00-4cf3-b61b-38b27c8685dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573574929 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2573574929
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.1190869273
Short name T85
Test name
Test status
Simulation time 1373656092 ps
CPU time 0.91 seconds
Started Jul 07 05:35:27 PM PDT 24
Finished Jul 07 05:35:28 PM PDT 24
Peak memory 204808 kb
Host smart-02ec9e27-74d8-45b7-b118-7b7167f21ef3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190869273 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.1190869273
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.410788064
Short name T357
Test name
Test status
Simulation time 447712444 ps
CPU time 2.34 seconds
Started Jul 07 05:35:34 PM PDT 24
Finished Jul 07 05:35:36 PM PDT 24
Peak memory 205016 kb
Host smart-c24bd62c-8573-4777-95b1-e0e64d4dda26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410788064 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.410788064
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.1151518220
Short name T904
Test name
Test status
Simulation time 184346576 ps
CPU time 1.05 seconds
Started Jul 07 05:35:29 PM PDT 24
Finished Jul 07 05:35:30 PM PDT 24
Peak memory 204680 kb
Host smart-013bc938-62ff-4268-a98d-bf39fd920155
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151518220 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.1151518220
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.919611623
Short name T988
Test name
Test status
Simulation time 1177170138 ps
CPU time 6.5 seconds
Started Jul 07 05:35:29 PM PDT 24
Finished Jul 07 05:35:35 PM PDT 24
Peak memory 213252 kb
Host smart-f7e3c565-5a38-4422-b8d5-b837dc4ac116
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919611623 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.919611623
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.4210300434
Short name T1455
Test name
Test status
Simulation time 2402630648 ps
CPU time 5.19 seconds
Started Jul 07 05:35:27 PM PDT 24
Finished Jul 07 05:35:33 PM PDT 24
Peak memory 205132 kb
Host smart-e9260c18-5fae-4f98-b2a1-f18871dd0015
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210300434 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.4210300434
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.3762903123
Short name T1505
Test name
Test status
Simulation time 1044989294 ps
CPU time 17.62 seconds
Started Jul 07 05:35:26 PM PDT 24
Finished Jul 07 05:35:44 PM PDT 24
Peak memory 204972 kb
Host smart-025f727f-55cd-40b5-8c89-eae43ae6020b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762903123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.3762903123
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.439024048
Short name T872
Test name
Test status
Simulation time 2694279932 ps
CPU time 20.99 seconds
Started Jul 07 05:35:28 PM PDT 24
Finished Jul 07 05:35:49 PM PDT 24
Peak memory 222040 kb
Host smart-fd4fb5ec-fad0-42f6-8595-37d21aeb49d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439024048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_rd.439024048
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.2196576880
Short name T857
Test name
Test status
Simulation time 12697003997 ps
CPU time 13.09 seconds
Started Jul 07 05:35:28 PM PDT 24
Finished Jul 07 05:35:41 PM PDT 24
Peak memory 205036 kb
Host smart-5d57980b-8054-46c2-84de-8efe60ddde18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196576880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.2196576880
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1786050253
Short name T167
Test name
Test status
Simulation time 1410894075 ps
CPU time 5.96 seconds
Started Jul 07 05:35:32 PM PDT 24
Finished Jul 07 05:35:38 PM PDT 24
Peak memory 211188 kb
Host smart-4890953f-dc0b-47d8-a24b-82955c7b7bd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786050253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1786050253
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.2037028304
Short name T1209
Test name
Test status
Simulation time 4832294765 ps
CPU time 7.77 seconds
Started Jul 07 05:35:28 PM PDT 24
Finished Jul 07 05:35:36 PM PDT 24
Peak memory 221376 kb
Host smart-21fe1f8a-ee7c-4819-8d5f-ca547723c8f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037028304 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.2037028304
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.1680822219
Short name T1040
Test name
Test status
Simulation time 223329610 ps
CPU time 3.37 seconds
Started Jul 07 05:35:34 PM PDT 24
Finished Jul 07 05:35:38 PM PDT 24
Peak memory 204992 kb
Host smart-028716d5-2ccf-4d59-827f-9842449c37b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680822219 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.1680822219
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3686989076
Short name T921
Test name
Test status
Simulation time 14864170 ps
CPU time 0.67 seconds
Started Jul 07 05:35:38 PM PDT 24
Finished Jul 07 05:35:39 PM PDT 24
Peak memory 204632 kb
Host smart-1c14e934-e6bf-40b6-bca1-e99517550d18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686989076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3686989076
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.3763469937
Short name T746
Test name
Test status
Simulation time 208877790 ps
CPU time 3.08 seconds
Started Jul 07 05:35:30 PM PDT 24
Finished Jul 07 05:35:33 PM PDT 24
Peak memory 218008 kb
Host smart-6eee0876-5715-4132-a95f-fa997de7f8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763469937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3763469937
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.1111316170
Short name T422
Test name
Test status
Simulation time 731041313 ps
CPU time 7.96 seconds
Started Jul 07 05:35:34 PM PDT 24
Finished Jul 07 05:35:43 PM PDT 24
Peak memory 290736 kb
Host smart-079771ce-9652-46b4-ac4f-2f7500eb4737
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111316170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.1111316170
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.109371376
Short name T82
Test name
Test status
Simulation time 10276793062 ps
CPU time 86.87 seconds
Started Jul 07 05:35:37 PM PDT 24
Finished Jul 07 05:37:05 PM PDT 24
Peak memory 765452 kb
Host smart-f5ef6958-9580-4f03-ab38-b9566c522919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109371376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.109371376
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1618221637
Short name T1155
Test name
Test status
Simulation time 10790891677 ps
CPU time 135.11 seconds
Started Jul 07 05:35:28 PM PDT 24
Finished Jul 07 05:37:44 PM PDT 24
Peak memory 660860 kb
Host smart-0c6f8848-4f21-4553-a58b-71b5047f381e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618221637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1618221637
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.3836913322
Short name T884
Test name
Test status
Simulation time 131595640 ps
CPU time 1.22 seconds
Started Jul 07 05:35:34 PM PDT 24
Finished Jul 07 05:35:36 PM PDT 24
Peak memory 205052 kb
Host smart-684fde6a-4338-44b0-90aa-1b05d6dd0b3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836913322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.3836913322
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.3339543818
Short name T383
Test name
Test status
Simulation time 430928038 ps
CPU time 6.84 seconds
Started Jul 07 05:35:34 PM PDT 24
Finished Jul 07 05:35:41 PM PDT 24
Peak memory 223496 kb
Host smart-e095e9f9-20d3-4ea6-b2ab-b8c924f9112c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339543818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.3339543818
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.2661866024
Short name T769
Test name
Test status
Simulation time 100224367425 ps
CPU time 394.74 seconds
Started Jul 07 05:35:29 PM PDT 24
Finished Jul 07 05:42:04 PM PDT 24
Peak memory 1486392 kb
Host smart-858ba63d-9cdd-4370-9d6a-e431ad7c3b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661866024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.2661866024
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.3814497001
Short name T168
Test name
Test status
Simulation time 417431543 ps
CPU time 16.16 seconds
Started Jul 07 05:35:37 PM PDT 24
Finished Jul 07 05:35:53 PM PDT 24
Peak memory 204972 kb
Host smart-c5a223a8-6193-4af7-895f-c8dd84535de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814497001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.3814497001
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.1987471363
Short name T66
Test name
Test status
Simulation time 1384222697 ps
CPU time 21.32 seconds
Started Jul 07 05:35:33 PM PDT 24
Finished Jul 07 05:35:54 PM PDT 24
Peak memory 304112 kb
Host smart-9bd6c27e-b29e-4440-b34a-9a287f2b746c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987471363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.1987471363
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.310885809
Short name T741
Test name
Test status
Simulation time 37967736 ps
CPU time 0.65 seconds
Started Jul 07 05:35:30 PM PDT 24
Finished Jul 07 05:35:31 PM PDT 24
Peak memory 204700 kb
Host smart-905cfc68-23bf-439a-9d2d-2ae4d890c609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310885809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.310885809
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.2708679318
Short name T680
Test name
Test status
Simulation time 6791578180 ps
CPU time 21.99 seconds
Started Jul 07 05:35:32 PM PDT 24
Finished Jul 07 05:35:55 PM PDT 24
Peak memory 213272 kb
Host smart-06cb08ee-efe8-4a78-845c-459010116060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708679318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.2708679318
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.173732103
Short name T1194
Test name
Test status
Simulation time 232829923 ps
CPU time 9.01 seconds
Started Jul 07 05:35:29 PM PDT 24
Finished Jul 07 05:35:38 PM PDT 24
Peak memory 216848 kb
Host smart-ebab355f-8dca-40e3-846a-d99ab9d5ac84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173732103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.173732103
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.4034487335
Short name T1029
Test name
Test status
Simulation time 8120902269 ps
CPU time 109.63 seconds
Started Jul 07 05:35:27 PM PDT 24
Finished Jul 07 05:37:17 PM PDT 24
Peak memory 469876 kb
Host smart-d3623a45-60ab-40c7-8d4b-00e8b92f1913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034487335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.4034487335
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.4099267936
Short name T236
Test name
Test status
Simulation time 36901054919 ps
CPU time 338.7 seconds
Started Jul 07 05:35:34 PM PDT 24
Finished Jul 07 05:41:13 PM PDT 24
Peak memory 637596 kb
Host smart-e385d9a8-f0c1-4b9b-ab57-5a32d6306f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099267936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.4099267936
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.2567678504
Short name T278
Test name
Test status
Simulation time 1842290728 ps
CPU time 14.44 seconds
Started Jul 07 05:35:34 PM PDT 24
Finished Jul 07 05:35:48 PM PDT 24
Peak memory 218144 kb
Host smart-86f0743d-885a-466c-b854-d04ae9a52850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567678504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2567678504
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.2857922448
Short name T1521
Test name
Test status
Simulation time 916641490 ps
CPU time 5.08 seconds
Started Jul 07 05:35:37 PM PDT 24
Finished Jul 07 05:35:42 PM PDT 24
Peak memory 215500 kb
Host smart-d0afc9d5-4121-43b4-80f9-bed636df18d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857922448 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.2857922448
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.2970216220
Short name T333
Test name
Test status
Simulation time 116633313 ps
CPU time 0.95 seconds
Started Jul 07 05:35:37 PM PDT 24
Finished Jul 07 05:35:39 PM PDT 24
Peak memory 212964 kb
Host smart-46c64df1-0ba4-4520-b544-75f2bbfa17be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970216220 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.2970216220
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.332725243
Short name T175
Test name
Test status
Simulation time 769253049 ps
CPU time 1.21 seconds
Started Jul 07 05:35:33 PM PDT 24
Finished Jul 07 05:35:34 PM PDT 24
Peak memory 204996 kb
Host smart-fd9f1d39-0886-4fe0-ac52-72a760187ef7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332725243 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_fifo_reset_tx.332725243
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.2284162809
Short name T1454
Test name
Test status
Simulation time 131716958 ps
CPU time 1.18 seconds
Started Jul 07 05:35:33 PM PDT 24
Finished Jul 07 05:35:35 PM PDT 24
Peak memory 204804 kb
Host smart-55c43cc5-9711-4314-a0b7-a4a168e5f8b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284162809 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.2284162809
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2803403565
Short name T1244
Test name
Test status
Simulation time 872609316 ps
CPU time 4.95 seconds
Started Jul 07 05:35:37 PM PDT 24
Finished Jul 07 05:35:42 PM PDT 24
Peak memory 213016 kb
Host smart-4caac893-7f93-47b4-89f5-f48bb17024ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803403565 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2803403565
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.2643002498
Short name T406
Test name
Test status
Simulation time 7177640129 ps
CPU time 11.99 seconds
Started Jul 07 05:35:38 PM PDT 24
Finished Jul 07 05:35:50 PM PDT 24
Peak memory 205032 kb
Host smart-45cc2b03-1efc-4ebf-a306-bd2fa7ce7a2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643002498 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.2643002498
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.3043765377
Short name T841
Test name
Test status
Simulation time 2339913881 ps
CPU time 16.83 seconds
Started Jul 07 05:35:34 PM PDT 24
Finished Jul 07 05:35:51 PM PDT 24
Peak memory 205060 kb
Host smart-0a2fac30-3845-4850-8421-54e2b4bfdc47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043765377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.3043765377
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3491478546
Short name T84
Test name
Test status
Simulation time 1579332504 ps
CPU time 41.03 seconds
Started Jul 07 05:35:30 PM PDT 24
Finished Jul 07 05:36:11 PM PDT 24
Peak memory 204940 kb
Host smart-eec8306b-d60d-488c-9762-ff71248c77f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491478546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3491478546
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.3131898297
Short name T19
Test name
Test status
Simulation time 59964668287 ps
CPU time 749.15 seconds
Started Jul 07 05:35:34 PM PDT 24
Finished Jul 07 05:48:03 PM PDT 24
Peak memory 5026524 kb
Host smart-68a2ba49-b76a-4ff1-9398-a0e33008fee2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131898297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.3131898297
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.543840963
Short name T519
Test name
Test status
Simulation time 209823044 ps
CPU time 1.43 seconds
Started Jul 07 05:35:38 PM PDT 24
Finished Jul 07 05:35:40 PM PDT 24
Peak memory 204964 kb
Host smart-2a159041-5002-47ef-86f2-4b74bbf649c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543840963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_t
arget_stretch.543840963
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.1198136047
Short name T827
Test name
Test status
Simulation time 5568815561 ps
CPU time 7.25 seconds
Started Jul 07 05:35:32 PM PDT 24
Finished Jul 07 05:35:39 PM PDT 24
Peak memory 219288 kb
Host smart-1cae8b95-7712-4c66-b1e8-cb3922f903d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198136047 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.1198136047
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.2691739153
Short name T990
Test name
Test status
Simulation time 223045871 ps
CPU time 3.66 seconds
Started Jul 07 05:35:37 PM PDT 24
Finished Jul 07 05:35:40 PM PDT 24
Peak memory 205036 kb
Host smart-88a995f1-0129-46d3-bb16-c739b8ebd1cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691739153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.2691739153
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.890588366
Short name T1304
Test name
Test status
Simulation time 17250086 ps
CPU time 0.65 seconds
Started Jul 07 05:33:16 PM PDT 24
Finished Jul 07 05:33:17 PM PDT 24
Peak memory 204584 kb
Host smart-f23bbc1c-31f5-4758-bb62-0f64aff1591c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890588366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.890588366
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3458572180
Short name T1032
Test name
Test status
Simulation time 833243450 ps
CPU time 4.89 seconds
Started Jul 07 05:33:11 PM PDT 24
Finished Jul 07 05:33:17 PM PDT 24
Peak memory 213256 kb
Host smart-c9f7a9e7-e1c4-4e98-af5b-3fc5a91a60e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458572180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3458572180
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.3428924920
Short name T393
Test name
Test status
Simulation time 1024789929 ps
CPU time 13.82 seconds
Started Jul 07 05:33:05 PM PDT 24
Finished Jul 07 05:33:20 PM PDT 24
Peak memory 257640 kb
Host smart-436d65d1-43f1-4fdd-afd8-8834f470cb89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428924920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.3428924920
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3516555051
Short name T48
Test name
Test status
Simulation time 48143764626 ps
CPU time 215.5 seconds
Started Jul 07 05:33:08 PM PDT 24
Finished Jul 07 05:36:44 PM PDT 24
Peak memory 926728 kb
Host smart-a88fd712-4656-40c3-9acc-6f07df89aa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516555051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3516555051
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.1558602244
Short name T628
Test name
Test status
Simulation time 5060257264 ps
CPU time 92.99 seconds
Started Jul 07 05:33:13 PM PDT 24
Finished Jul 07 05:34:46 PM PDT 24
Peak memory 811240 kb
Host smart-e3733c06-50cc-42ff-afd0-985b47bb6e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558602244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1558602244
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3761466725
Short name T1487
Test name
Test status
Simulation time 1364431501 ps
CPU time 1.07 seconds
Started Jul 07 05:33:15 PM PDT 24
Finished Jul 07 05:33:16 PM PDT 24
Peak memory 204736 kb
Host smart-4af2661a-770b-4c29-80b8-a30f5d4e886c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761466725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3761466725
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.2539097458
Short name T449
Test name
Test status
Simulation time 180795991 ps
CPU time 8.91 seconds
Started Jul 07 05:33:12 PM PDT 24
Finished Jul 07 05:33:22 PM PDT 24
Peak memory 205032 kb
Host smart-a23e6b1d-e3e9-4cec-90d7-53240a5ff61f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539097458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
2539097458
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.772480071
Short name T1425
Test name
Test status
Simulation time 2605569689 ps
CPU time 140.94 seconds
Started Jul 07 05:33:09 PM PDT 24
Finished Jul 07 05:35:31 PM PDT 24
Peak memory 718940 kb
Host smart-5738c72e-2623-47c7-b90a-499ac47446a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772480071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.772480071
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.2815474898
Short name T694
Test name
Test status
Simulation time 351359095 ps
CPU time 14.05 seconds
Started Jul 07 05:33:11 PM PDT 24
Finished Jul 07 05:33:25 PM PDT 24
Peak memory 204972 kb
Host smart-369dd281-e427-4493-8d3d-63a8f258ad20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815474898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.2815474898
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.4245343263
Short name T260
Test name
Test status
Simulation time 2102084510 ps
CPU time 31.37 seconds
Started Jul 07 05:33:12 PM PDT 24
Finished Jul 07 05:33:44 PM PDT 24
Peak memory 378228 kb
Host smart-4b105921-7167-41c3-9e87-9d59c7959af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245343263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.4245343263
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.387838143
Short name T695
Test name
Test status
Simulation time 18220523 ps
CPU time 0.71 seconds
Started Jul 07 05:33:12 PM PDT 24
Finished Jul 07 05:33:13 PM PDT 24
Peak memory 204736 kb
Host smart-2a05afa5-fff0-4636-b2e3-88ce356d7528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387838143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.387838143
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.452094572
Short name T1512
Test name
Test status
Simulation time 8263200311 ps
CPU time 66.23 seconds
Started Jul 07 05:33:12 PM PDT 24
Finished Jul 07 05:34:19 PM PDT 24
Peak memory 464548 kb
Host smart-4836fc9e-0482-451f-b3ee-25a4cd9e1af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452094572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.452094572
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.3318006754
Short name T399
Test name
Test status
Simulation time 2495892999 ps
CPU time 55.93 seconds
Started Jul 07 05:33:10 PM PDT 24
Finished Jul 07 05:34:07 PM PDT 24
Peak memory 599764 kb
Host smart-fcc291cf-c715-447a-b6d9-71baf5ef710d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318006754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.3318006754
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1477559757
Short name T364
Test name
Test status
Simulation time 6354608404 ps
CPU time 32.06 seconds
Started Jul 07 05:33:11 PM PDT 24
Finished Jul 07 05:33:43 PM PDT 24
Peak memory 411588 kb
Host smart-332530d2-f6d1-43f7-ae46-4b83dfb76f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477559757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1477559757
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.133917500
Short name T117
Test name
Test status
Simulation time 30763830116 ps
CPU time 220.37 seconds
Started Jul 07 05:33:10 PM PDT 24
Finished Jul 07 05:36:51 PM PDT 24
Peak memory 1314544 kb
Host smart-28539ae7-c15c-43f2-96d5-df0712b3ebc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133917500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.133917500
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.2233790269
Short name T1354
Test name
Test status
Simulation time 875776270 ps
CPU time 13.34 seconds
Started Jul 07 05:33:09 PM PDT 24
Finished Jul 07 05:33:23 PM PDT 24
Peak memory 218288 kb
Host smart-91f8a481-505a-4028-b82d-4af954c9996e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233790269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.2233790269
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.2905977284
Short name T170
Test name
Test status
Simulation time 39206682 ps
CPU time 0.87 seconds
Started Jul 07 05:33:13 PM PDT 24
Finished Jul 07 05:33:14 PM PDT 24
Peak memory 223104 kb
Host smart-f05d9199-0011-4527-a04d-883983cadcc9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905977284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.2905977284
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.3955370113
Short name T971
Test name
Test status
Simulation time 637247283 ps
CPU time 3.94 seconds
Started Jul 07 05:33:08 PM PDT 24
Finished Jul 07 05:33:12 PM PDT 24
Peak memory 204992 kb
Host smart-c69defc5-21ce-4d5a-9381-326fc1590c68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955370113 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3955370113
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3447235206
Short name T1385
Test name
Test status
Simulation time 278962163 ps
CPU time 0.97 seconds
Started Jul 07 05:33:12 PM PDT 24
Finished Jul 07 05:33:14 PM PDT 24
Peak memory 204768 kb
Host smart-9d0aaee2-fb8d-4777-afc9-2df71df4d2bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447235206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3447235206
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1130278898
Short name T888
Test name
Test status
Simulation time 370056585 ps
CPU time 1.01 seconds
Started Jul 07 05:33:13 PM PDT 24
Finished Jul 07 05:33:14 PM PDT 24
Peak memory 204768 kb
Host smart-de2910e0-80c4-427e-85a2-e1416be37ae9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130278898 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1130278898
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.4132778358
Short name T1326
Test name
Test status
Simulation time 399225523 ps
CPU time 2.09 seconds
Started Jul 07 05:33:12 PM PDT 24
Finished Jul 07 05:33:14 PM PDT 24
Peak memory 204944 kb
Host smart-ba45f200-b8ff-4db0-9153-5ab5f1a96e1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132778358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.4132778358
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.1381824720
Short name T1201
Test name
Test status
Simulation time 540229319 ps
CPU time 1.28 seconds
Started Jul 07 05:33:10 PM PDT 24
Finished Jul 07 05:33:11 PM PDT 24
Peak memory 204804 kb
Host smart-6575d5e8-6bd7-4f34-aee4-745c85de1e38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381824720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.1381824720
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.1402655558
Short name T681
Test name
Test status
Simulation time 921422048 ps
CPU time 4.97 seconds
Started Jul 07 05:33:10 PM PDT 24
Finished Jul 07 05:33:16 PM PDT 24
Peak memory 207296 kb
Host smart-46880623-96bd-41a5-8679-5b29189ea12d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402655558 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.1402655558
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.11114058
Short name T164
Test name
Test status
Simulation time 12982904280 ps
CPU time 18.57 seconds
Started Jul 07 05:33:12 PM PDT 24
Finished Jul 07 05:33:31 PM PDT 24
Peak memory 460916 kb
Host smart-361794da-1864-4c70-9df8-95072f5acb27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11114058 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.11114058
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.4269314714
Short name T861
Test name
Test status
Simulation time 4776343779 ps
CPU time 47.82 seconds
Started Jul 07 05:33:10 PM PDT 24
Finished Jul 07 05:33:58 PM PDT 24
Peak memory 205004 kb
Host smart-7e826540-b7b1-4ce9-806f-7a68f1b4854c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269314714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.4269314714
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.435057662
Short name T671
Test name
Test status
Simulation time 466674620 ps
CPU time 18.58 seconds
Started Jul 07 05:33:11 PM PDT 24
Finished Jul 07 05:33:30 PM PDT 24
Peak memory 204928 kb
Host smart-499c5c0d-409c-4e86-a9be-92546ab58208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435057662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_rd.435057662
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.151696281
Short name T1245
Test name
Test status
Simulation time 53071935814 ps
CPU time 114.54 seconds
Started Jul 07 05:33:13 PM PDT 24
Finished Jul 07 05:35:08 PM PDT 24
Peak memory 1496756 kb
Host smart-8ca013cb-89b6-4b51-9614-50c83c5b11c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151696281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_wr.151696281
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.3102291199
Short name T438
Test name
Test status
Simulation time 4158897903 ps
CPU time 6.52 seconds
Started Jul 07 05:33:08 PM PDT 24
Finished Jul 07 05:33:15 PM PDT 24
Peak memory 221320 kb
Host smart-e41eb8a2-7b77-4a1c-bb1d-cd870ccbd5d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102291199 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.3102291199
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.1513264131
Short name T1130
Test name
Test status
Simulation time 131419075 ps
CPU time 2.73 seconds
Started Jul 07 05:33:10 PM PDT 24
Finished Jul 07 05:33:13 PM PDT 24
Peak memory 205016 kb
Host smart-7d2be642-8121-4dd1-bed1-6f88989db57d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513264131 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.1513264131
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1327272578
Short name T1013
Test name
Test status
Simulation time 22979059 ps
CPU time 0.64 seconds
Started Jul 07 05:35:38 PM PDT 24
Finished Jul 07 05:35:39 PM PDT 24
Peak memory 204596 kb
Host smart-3722beb1-ef76-456f-8391-361a115a90a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327272578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1327272578
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.4115332330
Short name T1471
Test name
Test status
Simulation time 254982422 ps
CPU time 1.68 seconds
Started Jul 07 05:35:40 PM PDT 24
Finished Jul 07 05:35:42 PM PDT 24
Peak memory 213284 kb
Host smart-f18a34b5-3de4-468a-8ff6-451a93c0aeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115332330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.4115332330
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.2242218032
Short name T571
Test name
Test status
Simulation time 849538066 ps
CPU time 7.65 seconds
Started Jul 07 05:35:34 PM PDT 24
Finished Jul 07 05:35:42 PM PDT 24
Peak memory 291812 kb
Host smart-85ccc7fd-b0c5-4f3f-86ce-dd49fd67b460
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242218032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.2242218032
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.111844788
Short name T606
Test name
Test status
Simulation time 2187791785 ps
CPU time 138.78 seconds
Started Jul 07 05:35:41 PM PDT 24
Finished Jul 07 05:38:00 PM PDT 24
Peak memory 588260 kb
Host smart-66923f53-123d-4380-a5b8-1cfe4de84822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111844788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.111844788
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.1030508552
Short name T448
Test name
Test status
Simulation time 4989771917 ps
CPU time 85.38 seconds
Started Jul 07 05:35:37 PM PDT 24
Finished Jul 07 05:37:03 PM PDT 24
Peak memory 822116 kb
Host smart-ef2141b9-8e6b-4ec8-911b-089bf090dedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030508552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.1030508552
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.1176257958
Short name T1144
Test name
Test status
Simulation time 181103202 ps
CPU time 0.88 seconds
Started Jul 07 05:35:41 PM PDT 24
Finished Jul 07 05:35:42 PM PDT 24
Peak memory 204740 kb
Host smart-cb945219-f242-465f-a075-9b58c42e3cda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176257958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.1176257958
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3027068804
Short name T1506
Test name
Test status
Simulation time 235756958 ps
CPU time 5.41 seconds
Started Jul 07 05:35:35 PM PDT 24
Finished Jul 07 05:35:40 PM PDT 24
Peak memory 205016 kb
Host smart-f166622b-79d0-4cd4-acd2-0c6fdcb02d89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027068804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.3027068804
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.945968723
Short name T107
Test name
Test status
Simulation time 44434076512 ps
CPU time 148.13 seconds
Started Jul 07 05:35:37 PM PDT 24
Finished Jul 07 05:38:06 PM PDT 24
Peak memory 1564736 kb
Host smart-3697a94b-a7e3-42cd-b229-84f7ea0477f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945968723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.945968723
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.2899555803
Short name T1296
Test name
Test status
Simulation time 457752236 ps
CPU time 5.74 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:35:57 PM PDT 24
Peak memory 205020 kb
Host smart-7b2f4673-82aa-4708-97a9-548d79d885a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899555803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.2899555803
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.1494548200
Short name T1399
Test name
Test status
Simulation time 1846785495 ps
CPU time 79.76 seconds
Started Jul 07 05:35:40 PM PDT 24
Finished Jul 07 05:37:00 PM PDT 24
Peak memory 432176 kb
Host smart-e5475fb2-26c4-4636-8bd1-bb7976c2cd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494548200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.1494548200
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.107440097
Short name T1412
Test name
Test status
Simulation time 18505834 ps
CPU time 0.69 seconds
Started Jul 07 05:35:38 PM PDT 24
Finished Jul 07 05:35:39 PM PDT 24
Peak memory 204712 kb
Host smart-696154b9-44f1-4f2d-be25-61e3af97589d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107440097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.107440097
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.1606731555
Short name T484
Test name
Test status
Simulation time 5835143660 ps
CPU time 21.33 seconds
Started Jul 07 05:35:37 PM PDT 24
Finished Jul 07 05:35:59 PM PDT 24
Peak memory 365796 kb
Host smart-867c2e75-4750-4417-8d55-4212f6b64567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606731555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.1606731555
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.1800267030
Short name T344
Test name
Test status
Simulation time 2445135602 ps
CPU time 18.65 seconds
Started Jul 07 05:35:38 PM PDT 24
Finished Jul 07 05:35:57 PM PDT 24
Peak memory 205040 kb
Host smart-35ec95b1-329e-486e-8f56-a1890bcc1bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800267030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.1800267030
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2263538500
Short name T593
Test name
Test status
Simulation time 9532818955 ps
CPU time 55.52 seconds
Started Jul 07 05:35:35 PM PDT 24
Finished Jul 07 05:36:31 PM PDT 24
Peak memory 289696 kb
Host smart-094a90e2-d123-49ea-868a-6db15909902e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263538500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2263538500
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.3580949861
Short name T436
Test name
Test status
Simulation time 462368040 ps
CPU time 8.92 seconds
Started Jul 07 05:35:38 PM PDT 24
Finished Jul 07 05:35:47 PM PDT 24
Peak memory 213244 kb
Host smart-c049304a-4684-43a0-9f2f-556a90fe76d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580949861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.3580949861
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3175058369
Short name T1406
Test name
Test status
Simulation time 889022762 ps
CPU time 4.3 seconds
Started Jul 07 05:35:47 PM PDT 24
Finished Jul 07 05:35:52 PM PDT 24
Peak memory 213200 kb
Host smart-d95d74b7-cfa1-41bf-9ea5-970660b0394e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175058369 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3175058369
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2658505348
Short name T268
Test name
Test status
Simulation time 1457774221 ps
CPU time 1.26 seconds
Started Jul 07 05:35:39 PM PDT 24
Finished Jul 07 05:35:41 PM PDT 24
Peak memory 204988 kb
Host smart-e66ea510-3452-407b-8445-d41494550692
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658505348 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2658505348
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.3670179015
Short name T1072
Test name
Test status
Simulation time 221812293 ps
CPU time 0.83 seconds
Started Jul 07 05:35:40 PM PDT 24
Finished Jul 07 05:35:42 PM PDT 24
Peak memory 204848 kb
Host smart-7fc03eb0-6ba1-477d-a986-90c0def989f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670179015 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.3670179015
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.3018925122
Short name T1501
Test name
Test status
Simulation time 1402149300 ps
CPU time 1.89 seconds
Started Jul 07 05:35:51 PM PDT 24
Finished Jul 07 05:35:54 PM PDT 24
Peak memory 204840 kb
Host smart-d029be30-2fa8-44d7-8a45-a1969b9611ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018925122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.3018925122
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.4170158588
Short name T1362
Test name
Test status
Simulation time 579887021 ps
CPU time 1.34 seconds
Started Jul 07 05:35:41 PM PDT 24
Finished Jul 07 05:35:43 PM PDT 24
Peak memory 204764 kb
Host smart-9687da64-d591-42d9-9f86-4b9cd6e87311
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170158588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.4170158588
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.3849258443
Short name T348
Test name
Test status
Simulation time 4332287826 ps
CPU time 2.09 seconds
Started Jul 07 05:35:39 PM PDT 24
Finished Jul 07 05:35:42 PM PDT 24
Peak memory 205072 kb
Host smart-664640c0-2449-4891-90e2-864c2f0505e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849258443 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.3849258443
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.534833652
Short name T567
Test name
Test status
Simulation time 3682041769 ps
CPU time 4.08 seconds
Started Jul 07 05:35:40 PM PDT 24
Finished Jul 07 05:35:44 PM PDT 24
Peak memory 205072 kb
Host smart-2eee4dd8-f447-4f50-b81e-edfe40ed3641
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534833652 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.534833652
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.2865489029
Short name T774
Test name
Test status
Simulation time 1933655607 ps
CPU time 13.14 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:36:04 PM PDT 24
Peak memory 632768 kb
Host smart-12d9df4d-0aec-45f4-930b-dd15d2ae47a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865489029 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.2865489029
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.305435065
Short name T1157
Test name
Test status
Simulation time 2032106962 ps
CPU time 5.84 seconds
Started Jul 07 05:35:38 PM PDT 24
Finished Jul 07 05:35:45 PM PDT 24
Peak memory 204996 kb
Host smart-727c0e59-54e1-4ea2-9c16-7a8625b4a16a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305435065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_tar
get_smoke.305435065
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.2805569472
Short name T867
Test name
Test status
Simulation time 615807788 ps
CPU time 26.73 seconds
Started Jul 07 05:35:37 PM PDT 24
Finished Jul 07 05:36:04 PM PDT 24
Peak memory 204896 kb
Host smart-5e3dc7d6-7fe4-452d-9a09-8e0905a0eb34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805569472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.2805569472
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3616637408
Short name T1177
Test name
Test status
Simulation time 45696870856 ps
CPU time 45.21 seconds
Started Jul 07 05:35:36 PM PDT 24
Finished Jul 07 05:36:21 PM PDT 24
Peak memory 802812 kb
Host smart-b13a18dc-07bc-4faf-a09e-049be2f08e3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616637408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3616637408
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.1111482835
Short name T1092
Test name
Test status
Simulation time 4076751508 ps
CPU time 80.96 seconds
Started Jul 07 05:35:38 PM PDT 24
Finished Jul 07 05:36:59 PM PDT 24
Peak memory 565680 kb
Host smart-81b636a8-51a8-4449-97a3-63b3d1a771c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111482835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.1111482835
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1326480771
Short name T1373
Test name
Test status
Simulation time 1352910067 ps
CPU time 8.39 seconds
Started Jul 07 05:35:43 PM PDT 24
Finished Jul 07 05:35:52 PM PDT 24
Peak memory 217688 kb
Host smart-93412342-6ddc-4730-a324-e74dec94bfba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326480771 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1326480771
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.4064763552
Short name T649
Test name
Test status
Simulation time 146108019 ps
CPU time 2.68 seconds
Started Jul 07 05:35:42 PM PDT 24
Finished Jul 07 05:35:45 PM PDT 24
Peak memory 205016 kb
Host smart-7e6ce9d1-a3a1-4629-b494-7e6b7263f42a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064763552 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.4064763552
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.504392197
Short name T128
Test name
Test status
Simulation time 51656967 ps
CPU time 0.66 seconds
Started Jul 07 05:35:54 PM PDT 24
Finished Jul 07 05:35:55 PM PDT 24
Peak memory 204580 kb
Host smart-790c3cfa-2970-4ae8-bbef-c15310b792ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504392197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.504392197
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3133997128
Short name T439
Test name
Test status
Simulation time 314790436 ps
CPU time 4.47 seconds
Started Jul 07 05:35:48 PM PDT 24
Finished Jul 07 05:35:53 PM PDT 24
Peak memory 213268 kb
Host smart-9877a659-6e36-44a0-9665-c407df1c5d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133997128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3133997128
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2364252193
Short name T705
Test name
Test status
Simulation time 1344566301 ps
CPU time 4.86 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:35:56 PM PDT 24
Peak memory 224764 kb
Host smart-969fc296-f1d0-4d60-ba00-c98238e983fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364252193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2364252193
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.1736003429
Short name T435
Test name
Test status
Simulation time 1291912920 ps
CPU time 83.64 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:37:15 PM PDT 24
Peak memory 524300 kb
Host smart-7db75921-6808-4fc7-8cd2-f4ac08c83813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736003429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.1736003429
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2528431604
Short name T363
Test name
Test status
Simulation time 4210240507 ps
CPU time 163.93 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:38:35 PM PDT 24
Peak memory 702644 kb
Host smart-2b248022-8eb6-4914-a337-3427475697c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528431604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2528431604
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1819640113
Short name T1071
Test name
Test status
Simulation time 414487054 ps
CPU time 1.09 seconds
Started Jul 07 05:35:40 PM PDT 24
Finished Jul 07 05:35:41 PM PDT 24
Peak memory 204744 kb
Host smart-7fb74093-c3e3-4185-a6fa-7880689da3a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819640113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1819640113
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3151772161
Short name T1163
Test name
Test status
Simulation time 7402149607 ps
CPU time 378.17 seconds
Started Jul 07 05:35:40 PM PDT 24
Finished Jul 07 05:41:59 PM PDT 24
Peak memory 1488932 kb
Host smart-9b73cb72-a3e9-4282-8fb8-d08a1382bd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151772161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3151772161
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.665146421
Short name T1432
Test name
Test status
Simulation time 228336589 ps
CPU time 8.94 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:36:00 PM PDT 24
Peak memory 204892 kb
Host smart-88c9d9da-7d75-4b8e-a68d-7ae769f08fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665146421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.665146421
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.3169106629
Short name T923
Test name
Test status
Simulation time 4150063181 ps
CPU time 35.13 seconds
Started Jul 07 05:35:44 PM PDT 24
Finished Jul 07 05:36:19 PM PDT 24
Peak memory 424072 kb
Host smart-37b47d2c-1043-4a37-8634-f3e518fd9aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169106629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.3169106629
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.2832067337
Short name T382
Test name
Test status
Simulation time 16994094 ps
CPU time 0.64 seconds
Started Jul 07 05:35:38 PM PDT 24
Finished Jul 07 05:35:39 PM PDT 24
Peak memory 204700 kb
Host smart-4a667603-3c94-44b1-8630-e32318ccfc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832067337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2832067337
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.490632321
Short name T1086
Test name
Test status
Simulation time 5573656736 ps
CPU time 60.42 seconds
Started Jul 07 05:35:39 PM PDT 24
Finished Jul 07 05:36:40 PM PDT 24
Peak memory 205280 kb
Host smart-a2530d09-e1a7-4435-a89e-6859d6f7f8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490632321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.490632321
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.1802863122
Short name T855
Test name
Test status
Simulation time 235967617 ps
CPU time 3.64 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:35:54 PM PDT 24
Peak memory 204884 kb
Host smart-0eeb005b-b222-45a5-9987-7697e7d66889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802863122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.1802863122
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.3942384028
Short name T1428
Test name
Test status
Simulation time 7384183268 ps
CPU time 69.33 seconds
Started Jul 07 05:35:44 PM PDT 24
Finished Jul 07 05:36:54 PM PDT 24
Peak memory 369436 kb
Host smart-d246a2ef-5942-4523-9ec8-25395b61993b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942384028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3942384028
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.3766274160
Short name T849
Test name
Test status
Simulation time 11302128917 ps
CPU time 18.11 seconds
Started Jul 07 05:35:51 PM PDT 24
Finished Jul 07 05:36:10 PM PDT 24
Peak memory 221048 kb
Host smart-dc6f91eb-5611-4c58-89dc-4f44551a1c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766274160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.3766274160
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.1768323471
Short name T25
Test name
Test status
Simulation time 625514130 ps
CPU time 3.42 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:35:54 PM PDT 24
Peak memory 213208 kb
Host smart-59efa631-560f-407f-a894-1ccdf6f6dd3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768323471 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.1768323471
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.2483679743
Short name T869
Test name
Test status
Simulation time 360226133 ps
CPU time 1.35 seconds
Started Jul 07 05:35:41 PM PDT 24
Finished Jul 07 05:35:43 PM PDT 24
Peak memory 204952 kb
Host smart-3212eda9-4306-4f11-b30d-e40fb3c9af63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483679743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.2483679743
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.4122546186
Short name T194
Test name
Test status
Simulation time 308338653 ps
CPU time 0.96 seconds
Started Jul 07 05:35:44 PM PDT 24
Finished Jul 07 05:35:46 PM PDT 24
Peak memory 204808 kb
Host smart-ce1298b1-f6ee-478f-8b87-4b66d56ac9d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122546186 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.4122546186
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.1245527317
Short name T1379
Test name
Test status
Simulation time 993689649 ps
CPU time 1.02 seconds
Started Jul 07 05:35:43 PM PDT 24
Finished Jul 07 05:35:45 PM PDT 24
Peak memory 204740 kb
Host smart-ed2f7c3f-aa45-4872-b94d-571d61fb858a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245527317 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.1245527317
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.168885035
Short name T689
Test name
Test status
Simulation time 613992974 ps
CPU time 1.3 seconds
Started Jul 07 05:35:43 PM PDT 24
Finished Jul 07 05:35:45 PM PDT 24
Peak memory 204808 kb
Host smart-0c84c9b6-4feb-4db8-82ba-6f4c42a6e0ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168885035 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.168885035
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.1260185334
Short name T758
Test name
Test status
Simulation time 382701028 ps
CPU time 2.91 seconds
Started Jul 07 05:35:44 PM PDT 24
Finished Jul 07 05:35:47 PM PDT 24
Peak memory 205044 kb
Host smart-6421fe92-9203-499d-8cb0-799077cb88c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260185334 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.1260185334
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.548873431
Short name T1439
Test name
Test status
Simulation time 693237891 ps
CPU time 3.98 seconds
Started Jul 07 05:35:45 PM PDT 24
Finished Jul 07 05:35:50 PM PDT 24
Peak memory 205056 kb
Host smart-ba5213c5-2205-4358-aa37-b980794b51d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548873431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_intr_smoke.548873431
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.467535302
Short name T1418
Test name
Test status
Simulation time 8749717102 ps
CPU time 11.32 seconds
Started Jul 07 05:35:47 PM PDT 24
Finished Jul 07 05:35:58 PM PDT 24
Peak memory 329124 kb
Host smart-5e68c52b-ca83-4213-9036-0ba638af769b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467535302 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.467535302
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.3174720374
Short name T1350
Test name
Test status
Simulation time 12605412045 ps
CPU time 22.87 seconds
Started Jul 07 05:35:45 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 205092 kb
Host smart-4ffd0e46-7696-4551-adef-dae1ee765b70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174720374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.3174720374
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1189035486
Short name T433
Test name
Test status
Simulation time 3188132752 ps
CPU time 34.45 seconds
Started Jul 07 05:35:51 PM PDT 24
Finished Jul 07 05:36:26 PM PDT 24
Peak memory 204920 kb
Host smart-9d99d597-1581-412a-98e2-304c7728189a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189035486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1189035486
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.1260066856
Short name T487
Test name
Test status
Simulation time 49244374910 ps
CPU time 302.37 seconds
Started Jul 07 05:35:43 PM PDT 24
Finished Jul 07 05:40:46 PM PDT 24
Peak memory 3291048 kb
Host smart-e584ee1b-b2e1-4583-8aa1-da69f26a5173
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260066856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.1260066856
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.98866188
Short name T1147
Test name
Test status
Simulation time 5891883486 ps
CPU time 21.3 seconds
Started Jul 07 05:35:42 PM PDT 24
Finished Jul 07 05:36:04 PM PDT 24
Peak memory 280988 kb
Host smart-2ebd4d39-bb4f-433f-ba7a-d28bf0bc42f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98866188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_stretch.98866188
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3394644420
Short name T446
Test name
Test status
Simulation time 1298227588 ps
CPU time 7.95 seconds
Started Jul 07 05:35:46 PM PDT 24
Finished Jul 07 05:35:54 PM PDT 24
Peak memory 221208 kb
Host smart-fdd546ce-6e64-48ef-bad3-6d9e519c2fd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394644420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3394644420
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.3640189255
Short name T192
Test name
Test status
Simulation time 101034498 ps
CPU time 2.32 seconds
Started Jul 07 05:35:44 PM PDT 24
Finished Jul 07 05:35:47 PM PDT 24
Peak memory 205316 kb
Host smart-393cb710-4506-4778-84e4-143e3bfb2092
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640189255 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.3640189255
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.2685021538
Short name T742
Test name
Test status
Simulation time 49142599 ps
CPU time 0.61 seconds
Started Jul 07 05:35:56 PM PDT 24
Finished Jul 07 05:35:57 PM PDT 24
Peak memory 204604 kb
Host smart-c107606f-fad7-48bd-b8b1-a16f741fc706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685021538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2685021538
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.813966143
Short name T459
Test name
Test status
Simulation time 285127685 ps
CPU time 4.04 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:35:54 PM PDT 24
Peak memory 229540 kb
Host smart-9fb17e07-961f-42e0-b8b2-72b591473240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813966143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.813966143
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.3114499591
Short name T391
Test name
Test status
Simulation time 365106909 ps
CPU time 9.11 seconds
Started Jul 07 05:35:46 PM PDT 24
Finished Jul 07 05:35:55 PM PDT 24
Peak memory 237504 kb
Host smart-9da473de-cdcb-4cfb-90f5-fc9c0fbf0c04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114499591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.3114499591
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.1303539595
Short name T78
Test name
Test status
Simulation time 10347988232 ps
CPU time 121.18 seconds
Started Jul 07 05:35:47 PM PDT 24
Finished Jul 07 05:37:48 PM PDT 24
Peak memory 616484 kb
Host smart-764336e0-ba58-49db-92d1-2e0a8e0baa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303539595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.1303539595
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2421890950
Short name T58
Test name
Test status
Simulation time 2599678518 ps
CPU time 95.8 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:37:26 PM PDT 24
Peak memory 822192 kb
Host smart-f6b9d835-9585-4c21-9019-b50df1a97e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421890950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2421890950
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.2411388336
Short name T1010
Test name
Test status
Simulation time 79874586 ps
CPU time 0.97 seconds
Started Jul 07 05:35:47 PM PDT 24
Finished Jul 07 05:35:48 PM PDT 24
Peak memory 204732 kb
Host smart-39456506-fce9-43c5-808a-77a75a528291
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411388336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.2411388336
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.350369926
Short name T161
Test name
Test status
Simulation time 496774484 ps
CPU time 6.86 seconds
Started Jul 07 05:35:49 PM PDT 24
Finished Jul 07 05:35:56 PM PDT 24
Peak memory 256124 kb
Host smart-147b8051-48fb-4667-9e89-29c2bf19dd6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350369926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.
350369926
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2095502103
Short name T812
Test name
Test status
Simulation time 17212743208 ps
CPU time 299.31 seconds
Started Jul 07 05:35:48 PM PDT 24
Finished Jul 07 05:40:48 PM PDT 24
Peak memory 1207884 kb
Host smart-44bd79cc-9bd5-42a7-94e6-a556d59eb977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095502103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2095502103
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.3830501716
Short name T111
Test name
Test status
Simulation time 1207342148 ps
CPU time 9.83 seconds
Started Jul 07 05:35:49 PM PDT 24
Finished Jul 07 05:36:00 PM PDT 24
Peak memory 204916 kb
Host smart-6ba87ed4-5d45-40ce-a4ec-d09cbe1985fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830501716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.3830501716
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_override.2210750859
Short name T1446
Test name
Test status
Simulation time 25555146 ps
CPU time 0.7 seconds
Started Jul 07 05:35:49 PM PDT 24
Finished Jul 07 05:35:50 PM PDT 24
Peak memory 204748 kb
Host smart-5a6cddc3-e7ac-463f-83e5-425d33a13ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210750859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.2210750859
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1161725016
Short name T509
Test name
Test status
Simulation time 2842035489 ps
CPU time 77.76 seconds
Started Jul 07 05:35:48 PM PDT 24
Finished Jul 07 05:37:06 PM PDT 24
Peak memory 813080 kb
Host smart-ff17d792-8250-430a-9378-57d443f76311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161725016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1161725016
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.2099253626
Short name T478
Test name
Test status
Simulation time 89236503 ps
CPU time 1.88 seconds
Started Jul 07 05:35:48 PM PDT 24
Finished Jul 07 05:35:51 PM PDT 24
Peak memory 222420 kb
Host smart-849c40e8-b2c4-46b1-a761-6b34130f8e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099253626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.2099253626
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.1685544303
Short name T735
Test name
Test status
Simulation time 2019963889 ps
CPU time 38.42 seconds
Started Jul 07 05:35:51 PM PDT 24
Finished Jul 07 05:36:30 PM PDT 24
Peak memory 370560 kb
Host smart-87793897-a20a-4cb3-8d3e-f1a93332883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685544303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.1685544303
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.419635350
Short name T856
Test name
Test status
Simulation time 1636685307 ps
CPU time 14.01 seconds
Started Jul 07 05:35:45 PM PDT 24
Finished Jul 07 05:36:00 PM PDT 24
Peak memory 220760 kb
Host smart-923db7d2-2ec4-422f-9afa-96a494c6b107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419635350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.419635350
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.2626810988
Short name T23
Test name
Test status
Simulation time 498931459 ps
CPU time 2.55 seconds
Started Jul 07 05:35:53 PM PDT 24
Finished Jul 07 05:35:56 PM PDT 24
Peak memory 205068 kb
Host smart-e67815aa-eefa-4dce-92cd-9b7bb2338591
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626810988 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.2626810988
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.488172861
Short name T426
Test name
Test status
Simulation time 389316905 ps
CPU time 1.39 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:35:52 PM PDT 24
Peak memory 205008 kb
Host smart-8766b943-18cf-40bf-b7a3-3c916ef8ff2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488172861 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_acq.488172861
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1397018357
Short name T560
Test name
Test status
Simulation time 760635593 ps
CPU time 0.81 seconds
Started Jul 07 05:35:59 PM PDT 24
Finished Jul 07 05:36:00 PM PDT 24
Peak memory 204736 kb
Host smart-cf2f7fb8-6fc1-4534-8f8c-fffb9f725c69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397018357 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1397018357
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.4214001140
Short name T1277
Test name
Test status
Simulation time 5866472670 ps
CPU time 1.94 seconds
Started Jul 07 05:35:56 PM PDT 24
Finished Jul 07 05:35:58 PM PDT 24
Peak memory 205060 kb
Host smart-c3ab00cc-2f39-428d-b1af-0dc527b0d923
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214001140 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.4214001140
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.3866422721
Short name T432
Test name
Test status
Simulation time 206766590 ps
CPU time 1.12 seconds
Started Jul 07 05:35:55 PM PDT 24
Finished Jul 07 05:35:56 PM PDT 24
Peak memory 204772 kb
Host smart-d8536303-250f-4188-9805-f1c4839e31d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866422721 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.3866422721
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.2021756415
Short name T1073
Test name
Test status
Simulation time 609896872 ps
CPU time 2.57 seconds
Started Jul 07 05:35:51 PM PDT 24
Finished Jul 07 05:35:54 PM PDT 24
Peak memory 205108 kb
Host smart-11e5f218-f4cc-4815-bcdd-54e350506c17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021756415 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.2021756415
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.3441378091
Short name T532
Test name
Test status
Simulation time 6959030436 ps
CPU time 7.18 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:35:59 PM PDT 24
Peak memory 205068 kb
Host smart-5fb973a7-e24f-488a-9b3c-e58c4cae08d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441378091 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.3441378091
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.3339802313
Short name T611
Test name
Test status
Simulation time 11242051787 ps
CPU time 17.01 seconds
Started Jul 07 05:35:59 PM PDT 24
Finished Jul 07 05:36:17 PM PDT 24
Peak memory 569148 kb
Host smart-79ff83be-ac97-4141-b3b0-b47e8bfbc7d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339802313 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.3339802313
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3200470579
Short name T1312
Test name
Test status
Simulation time 2404273014 ps
CPU time 10.84 seconds
Started Jul 07 05:35:49 PM PDT 24
Finished Jul 07 05:36:00 PM PDT 24
Peak memory 205032 kb
Host smart-81569cfc-570b-401a-9afe-d597d62e2a1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200470579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3200470579
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3983374734
Short name T591
Test name
Test status
Simulation time 2129578565 ps
CPU time 46.12 seconds
Started Jul 07 05:35:51 PM PDT 24
Finished Jul 07 05:36:38 PM PDT 24
Peak memory 205048 kb
Host smart-1bfe86b2-945a-4b85-81e6-abc81855cf4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983374734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3983374734
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1956054011
Short name T326
Test name
Test status
Simulation time 2802538754 ps
CPU time 5.72 seconds
Started Jul 07 05:35:48 PM PDT 24
Finished Jul 07 05:35:54 PM PDT 24
Peak memory 205392 kb
Host smart-53ba9dab-fec4-435d-864d-4c63b2f6b535
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956054011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1956054011
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2856499743
Short name T297
Test name
Test status
Simulation time 5069778892 ps
CPU time 6.99 seconds
Started Jul 07 05:35:54 PM PDT 24
Finished Jul 07 05:36:01 PM PDT 24
Peak memory 220620 kb
Host smart-a71d0088-b625-4126-b3fd-e2cf7b12bca4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856499743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2856499743
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.29839518
Short name T920
Test name
Test status
Simulation time 166531543 ps
CPU time 2.76 seconds
Started Jul 07 05:35:56 PM PDT 24
Finished Jul 07 05:35:59 PM PDT 24
Peak memory 204936 kb
Host smart-b71d6934-3e23-4652-a0b9-3fb7653ddf41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29839518 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.29839518
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3356475755
Short name T309
Test name
Test status
Simulation time 16379336 ps
CPU time 0.64 seconds
Started Jul 07 05:35:57 PM PDT 24
Finished Jul 07 05:35:58 PM PDT 24
Peak memory 204564 kb
Host smart-bdd7ea8f-7686-44e9-b65a-f4c954269df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356475755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3356475755
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.3059258755
Short name T1132
Test name
Test status
Simulation time 270710218 ps
CPU time 1.37 seconds
Started Jul 07 05:35:55 PM PDT 24
Finished Jul 07 05:35:57 PM PDT 24
Peak memory 221504 kb
Host smart-044a6cae-d0bd-4a68-be6e-6985e4e30dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059258755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.3059258755
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.2946910577
Short name T950
Test name
Test status
Simulation time 978498544 ps
CPU time 16.67 seconds
Started Jul 07 05:35:51 PM PDT 24
Finished Jul 07 05:36:08 PM PDT 24
Peak memory 274564 kb
Host smart-848c50e3-b1a0-407f-9990-426d99e4d39a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946910577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.2946910577
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.101339476
Short name T1178
Test name
Test status
Simulation time 5393716333 ps
CPU time 98.16 seconds
Started Jul 07 05:35:56 PM PDT 24
Finished Jul 07 05:37:35 PM PDT 24
Peak memory 780724 kb
Host smart-acf0f936-c079-4625-ab2f-24b03676916f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101339476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.101339476
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.4139485061
Short name T1191
Test name
Test status
Simulation time 5417279233 ps
CPU time 101.44 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:37:32 PM PDT 24
Peak memory 867648 kb
Host smart-00b5be7f-c0b5-4d36-9de2-d3454fee1718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139485061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.4139485061
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.905345270
Short name T897
Test name
Test status
Simulation time 86301300 ps
CPU time 1.08 seconds
Started Jul 07 05:35:56 PM PDT 24
Finished Jul 07 05:35:57 PM PDT 24
Peak memory 204756 kb
Host smart-e1338f0d-1b81-4e69-abe2-9e494dd4f4d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905345270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.905345270
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2394224078
Short name T846
Test name
Test status
Simulation time 649057154 ps
CPU time 8.66 seconds
Started Jul 07 05:35:51 PM PDT 24
Finished Jul 07 05:36:00 PM PDT 24
Peak memory 204992 kb
Host smart-b55257a1-063d-4fa5-aed7-05bda4ab836a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394224078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2394224078
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.2726027634
Short name T1492
Test name
Test status
Simulation time 7900408067 ps
CPU time 273.04 seconds
Started Jul 07 05:35:50 PM PDT 24
Finished Jul 07 05:40:23 PM PDT 24
Peak memory 1136168 kb
Host smart-7f481592-4dca-4233-a22c-b5dd44cc8f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726027634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2726027634
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.3319419065
Short name T748
Test name
Test status
Simulation time 537614548 ps
CPU time 22.12 seconds
Started Jul 07 05:35:58 PM PDT 24
Finished Jul 07 05:36:20 PM PDT 24
Peak memory 205088 kb
Host smart-d7a35491-3ddf-4164-9cd0-32a6144a225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319419065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.3319419065
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1332057098
Short name T1369
Test name
Test status
Simulation time 3973511695 ps
CPU time 104.86 seconds
Started Jul 07 05:36:02 PM PDT 24
Finished Jul 07 05:37:47 PM PDT 24
Peak memory 451564 kb
Host smart-7f0ea18b-b92a-4df7-bd6f-0e2652fa3a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332057098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1332057098
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.4199255567
Short name T132
Test name
Test status
Simulation time 50552150 ps
CPU time 0.7 seconds
Started Jul 07 05:35:52 PM PDT 24
Finished Jul 07 05:35:53 PM PDT 24
Peak memory 204688 kb
Host smart-df6a60b5-6bad-44f7-bdc8-af53a00880b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199255567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.4199255567
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3064128512
Short name T474
Test name
Test status
Simulation time 291281468 ps
CPU time 1.62 seconds
Started Jul 07 05:35:51 PM PDT 24
Finished Jul 07 05:35:53 PM PDT 24
Peak memory 213412 kb
Host smart-eb80e368-1fe4-4e5a-b9e6-32833d63b827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064128512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3064128512
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.2073663709
Short name T1498
Test name
Test status
Simulation time 143094455 ps
CPU time 1.16 seconds
Started Jul 07 05:35:53 PM PDT 24
Finished Jul 07 05:35:55 PM PDT 24
Peak memory 213180 kb
Host smart-803fa0a2-d42d-4a27-b587-33e395381a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073663709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.2073663709
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2368915084
Short name T1295
Test name
Test status
Simulation time 1197556494 ps
CPU time 21.79 seconds
Started Jul 07 05:35:56 PM PDT 24
Finished Jul 07 05:36:19 PM PDT 24
Peak memory 289232 kb
Host smart-7cae9c77-0ba4-4fef-bd5e-478ff8b8109a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368915084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2368915084
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.3546546027
Short name T289
Test name
Test status
Simulation time 13812891171 ps
CPU time 208.69 seconds
Started Jul 07 05:35:57 PM PDT 24
Finished Jul 07 05:39:26 PM PDT 24
Peak memory 915576 kb
Host smart-06599b92-e6b5-4f57-92bc-0dbb92fecf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546546027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.3546546027
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2597451738
Short name T1094
Test name
Test status
Simulation time 2432770261 ps
CPU time 11.41 seconds
Started Jul 07 05:35:58 PM PDT 24
Finished Jul 07 05:36:10 PM PDT 24
Peak memory 213268 kb
Host smart-23c6acd9-7d21-47c8-931b-dedcec0d710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597451738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2597451738
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.1406590905
Short name T711
Test name
Test status
Simulation time 2667136706 ps
CPU time 4.06 seconds
Started Jul 07 05:35:59 PM PDT 24
Finished Jul 07 05:36:04 PM PDT 24
Peak memory 213256 kb
Host smart-cf0fe5a2-8e40-4126-aba6-3fc0c944c93b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406590905 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.1406590905
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.4230959307
Short name T1320
Test name
Test status
Simulation time 201581417 ps
CPU time 1.02 seconds
Started Jul 07 05:35:55 PM PDT 24
Finished Jul 07 05:35:57 PM PDT 24
Peak memory 204732 kb
Host smart-76d11e75-a65b-4b55-9869-cb6935af64a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230959307 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.4230959307
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3269093240
Short name T961
Test name
Test status
Simulation time 136224213 ps
CPU time 0.96 seconds
Started Jul 07 05:35:59 PM PDT 24
Finished Jul 07 05:36:01 PM PDT 24
Peak memory 204764 kb
Host smart-83733678-6c69-4b11-94c5-f5d44b5ca862
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269093240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.3269093240
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.3690243650
Short name T785
Test name
Test status
Simulation time 463234032 ps
CPU time 2.69 seconds
Started Jul 07 05:35:59 PM PDT 24
Finished Jul 07 05:36:02 PM PDT 24
Peak memory 204868 kb
Host smart-311ce15e-7b17-45cd-89a9-2369ed3bfb9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690243650 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.3690243650
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.516816120
Short name T1087
Test name
Test status
Simulation time 141345913 ps
CPU time 1.23 seconds
Started Jul 07 05:35:59 PM PDT 24
Finished Jul 07 05:36:01 PM PDT 24
Peak memory 204760 kb
Host smart-90b3d35a-c8f0-4a2b-a005-43f6363b4a4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516816120 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.516816120
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2958738691
Short name T622
Test name
Test status
Simulation time 4761477514 ps
CPU time 6.19 seconds
Started Jul 07 05:36:02 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 209468 kb
Host smart-f49fd4e2-69bb-4ac1-9410-28e717ac5156
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958738691 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2958738691
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.864584904
Short name T514
Test name
Test status
Simulation time 8421686334 ps
CPU time 38.3 seconds
Started Jul 07 05:35:58 PM PDT 24
Finished Jul 07 05:36:37 PM PDT 24
Peak memory 1030716 kb
Host smart-a711367c-9fe0-4334-b77a-da3d466a874d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864584904 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.864584904
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.3640216073
Short name T679
Test name
Test status
Simulation time 4701577982 ps
CPU time 34.36 seconds
Started Jul 07 05:35:58 PM PDT 24
Finished Jul 07 05:36:33 PM PDT 24
Peak memory 204996 kb
Host smart-0da76756-816f-4aec-92ea-d084ab5e9e5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640216073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.3640216073
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3869197751
Short name T957
Test name
Test status
Simulation time 484563831 ps
CPU time 7.83 seconds
Started Jul 07 05:35:56 PM PDT 24
Finished Jul 07 05:36:04 PM PDT 24
Peak memory 205024 kb
Host smart-496579d4-42ee-479a-aedc-28c8d4f41e14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869197751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3869197751
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.902613164
Short name T1288
Test name
Test status
Simulation time 70471017150 ps
CPU time 435.97 seconds
Started Jul 07 05:35:56 PM PDT 24
Finished Jul 07 05:43:13 PM PDT 24
Peak memory 3256472 kb
Host smart-50e08a49-e61f-44a2-8a76-a917498e8c6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902613164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_wr.902613164
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.3083157123
Short name T1393
Test name
Test status
Simulation time 2531265873 ps
CPU time 24.73 seconds
Started Jul 07 05:35:54 PM PDT 24
Finished Jul 07 05:36:19 PM PDT 24
Peak memory 304372 kb
Host smart-63941c91-dc77-4916-ad52-364613b6a6ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083157123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.3083157123
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1071582257
Short name T1401
Test name
Test status
Simulation time 6877148498 ps
CPU time 7.3 seconds
Started Jul 07 05:35:53 PM PDT 24
Finished Jul 07 05:36:01 PM PDT 24
Peak memory 205112 kb
Host smart-9cc66c10-9c9f-46c9-80a2-d4a69468bcf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071582257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1071582257
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.3957619885
Short name T304
Test name
Test status
Simulation time 100154202 ps
CPU time 2.19 seconds
Started Jul 07 05:35:53 PM PDT 24
Finished Jul 07 05:35:55 PM PDT 24
Peak memory 205020 kb
Host smart-2c0d6752-b9d1-455f-81ea-3a0e14a30534
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957619885 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.3957619885
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.3868747868
Short name T891
Test name
Test status
Simulation time 15511351 ps
CPU time 0.65 seconds
Started Jul 07 05:36:08 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 204640 kb
Host smart-e810501f-5a22-4c1b-be24-6c976a8a771b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868747868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.3868747868
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.1769224334
Short name T1333
Test name
Test status
Simulation time 155719748 ps
CPU time 5.24 seconds
Started Jul 07 05:36:01 PM PDT 24
Finished Jul 07 05:36:07 PM PDT 24
Peak memory 213284 kb
Host smart-0e1d1cfd-eed7-4fb6-aaed-23327b152791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769224334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.1769224334
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.2643661288
Short name T771
Test name
Test status
Simulation time 333242909 ps
CPU time 17.01 seconds
Started Jul 07 05:35:56 PM PDT 24
Finished Jul 07 05:36:14 PM PDT 24
Peak memory 270756 kb
Host smart-0e0443ce-62c8-4098-929c-fb92e28aea62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643661288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.2643661288
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.3297688229
Short name T882
Test name
Test status
Simulation time 3142450064 ps
CPU time 53.82 seconds
Started Jul 07 05:36:01 PM PDT 24
Finished Jul 07 05:36:55 PM PDT 24
Peak memory 596168 kb
Host smart-d391071e-2015-451b-8d42-2aea756ec8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297688229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.3297688229
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2579575169
Short name T510
Test name
Test status
Simulation time 1737383973 ps
CPU time 49.38 seconds
Started Jul 07 05:35:59 PM PDT 24
Finished Jul 07 05:36:49 PM PDT 24
Peak memory 618484 kb
Host smart-2d7191b2-16b8-4b6e-8e25-da3b1b46253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579575169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2579575169
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3221374534
Short name T781
Test name
Test status
Simulation time 125638798 ps
CPU time 1.03 seconds
Started Jul 07 05:35:56 PM PDT 24
Finished Jul 07 05:35:58 PM PDT 24
Peak memory 204732 kb
Host smart-9bc54ee3-3a84-4e10-a9f6-785fa239eb1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221374534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3221374534
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.3502212967
Short name T970
Test name
Test status
Simulation time 446555477 ps
CPU time 5.09 seconds
Started Jul 07 05:35:53 PM PDT 24
Finished Jul 07 05:35:59 PM PDT 24
Peak memory 204952 kb
Host smart-d919e717-ca63-4fc5-9a4d-a429047bb034
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502212967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.3502212967
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.1932098803
Short name T1069
Test name
Test status
Simulation time 10870565468 ps
CPU time 139.41 seconds
Started Jul 07 05:35:57 PM PDT 24
Finished Jul 07 05:38:17 PM PDT 24
Peak memory 1556872 kb
Host smart-7067c470-928a-43ef-832f-c3ed57ff4567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932098803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1932098803
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.2587254596
Short name T485
Test name
Test status
Simulation time 358626325 ps
CPU time 14.43 seconds
Started Jul 07 05:36:06 PM PDT 24
Finished Jul 07 05:36:21 PM PDT 24
Peak memory 205060 kb
Host smart-9762009d-6a68-4fc4-856b-7cf493f2c4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587254596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.2587254596
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.1124676649
Short name T1012
Test name
Test status
Simulation time 1264037972 ps
CPU time 18.55 seconds
Started Jul 07 05:36:04 PM PDT 24
Finished Jul 07 05:36:23 PM PDT 24
Peak memory 317796 kb
Host smart-725f6628-3665-4154-a367-1f0f914cb3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124676649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.1124676649
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.3779448589
Short name T1363
Test name
Test status
Simulation time 49996638 ps
CPU time 0.71 seconds
Started Jul 07 05:35:54 PM PDT 24
Finished Jul 07 05:35:55 PM PDT 24
Peak memory 204688 kb
Host smart-caadb7c7-ba7b-46ae-b257-42d904d23b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779448589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3779448589
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.2075415870
Short name T733
Test name
Test status
Simulation time 4678018784 ps
CPU time 53.16 seconds
Started Jul 07 05:36:01 PM PDT 24
Finished Jul 07 05:36:54 PM PDT 24
Peak memory 713376 kb
Host smart-641e78bd-ac35-4b89-b534-81a29ff7d09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075415870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2075415870
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.1112121578
Short name T32
Test name
Test status
Simulation time 827349122 ps
CPU time 8.73 seconds
Started Jul 07 05:36:00 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 204948 kb
Host smart-76764620-de81-4cb2-a062-768afb673383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112121578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.1112121578
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.1782178077
Short name T939
Test name
Test status
Simulation time 1735386633 ps
CPU time 28.4 seconds
Started Jul 07 05:35:59 PM PDT 24
Finished Jul 07 05:36:28 PM PDT 24
Peak memory 361572 kb
Host smart-7dde68e1-cc6d-4202-b01a-45c1b101afa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782178077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.1782178077
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.1035106688
Short name T1360
Test name
Test status
Simulation time 2917252475 ps
CPU time 12.57 seconds
Started Jul 07 05:36:04 PM PDT 24
Finished Jul 07 05:36:17 PM PDT 24
Peak memory 221484 kb
Host smart-c75c47a4-7d3b-4551-a52e-d17505765868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035106688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.1035106688
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.1636008563
Short name T673
Test name
Test status
Simulation time 4590621846 ps
CPU time 4.19 seconds
Started Jul 07 05:36:04 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 213252 kb
Host smart-9e751429-340a-4ee0-932e-81200672eb4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636008563 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.1636008563
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.3079473660
Short name T1378
Test name
Test status
Simulation time 226593611 ps
CPU time 1.43 seconds
Started Jul 07 05:36:02 PM PDT 24
Finished Jul 07 05:36:04 PM PDT 24
Peak memory 204960 kb
Host smart-0b6e1e4a-c677-486e-b293-a6cafcd3ff0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079473660 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.3079473660
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.806934477
Short name T1305
Test name
Test status
Simulation time 171637239 ps
CPU time 1.23 seconds
Started Jul 07 05:36:04 PM PDT 24
Finished Jul 07 05:36:06 PM PDT 24
Peak memory 204804 kb
Host smart-4d2d7920-c255-446e-a352-d135eac0308b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806934477 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_fifo_reset_tx.806934477
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.1098167500
Short name T976
Test name
Test status
Simulation time 2326849322 ps
CPU time 2.75 seconds
Started Jul 07 05:36:07 PM PDT 24
Finished Jul 07 05:36:10 PM PDT 24
Peak memory 205048 kb
Host smart-23260f40-3fe6-4b5d-8d2f-05879bd90306
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098167500 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.1098167500
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.3580023525
Short name T677
Test name
Test status
Simulation time 221770292 ps
CPU time 0.81 seconds
Started Jul 07 05:36:06 PM PDT 24
Finished Jul 07 05:36:07 PM PDT 24
Peak memory 204800 kb
Host smart-7234efb9-1663-45a4-bee2-8766ec99ae0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580023525 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.3580023525
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.3648923571
Short name T259
Test name
Test status
Simulation time 289063227 ps
CPU time 2.62 seconds
Started Jul 07 05:36:04 PM PDT 24
Finished Jul 07 05:36:07 PM PDT 24
Peak memory 205388 kb
Host smart-e397aae3-384a-439d-95a2-3171f9c64d0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648923571 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.3648923571
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.4107774567
Short name T619
Test name
Test status
Simulation time 3570892432 ps
CPU time 6.22 seconds
Started Jul 07 05:36:04 PM PDT 24
Finished Jul 07 05:36:10 PM PDT 24
Peak memory 218468 kb
Host smart-b90620b3-3504-4d1b-b80a-c34eb0b39179
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107774567 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.4107774567
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1512319953
Short name T1183
Test name
Test status
Simulation time 20993691168 ps
CPU time 185.27 seconds
Started Jul 07 05:36:00 PM PDT 24
Finished Jul 07 05:39:05 PM PDT 24
Peak memory 2932624 kb
Host smart-1438f783-4db3-44a0-b32b-1b9afae6a7fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512319953 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1512319953
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.3949909798
Short name T460
Test name
Test status
Simulation time 926472484 ps
CPU time 16.19 seconds
Started Jul 07 05:35:59 PM PDT 24
Finished Jul 07 05:36:15 PM PDT 24
Peak memory 205072 kb
Host smart-0fd138f2-3fb9-4f39-ad21-0b538e7ecc71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949909798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.3949909798
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.161805209
Short name T1230
Test name
Test status
Simulation time 708350406 ps
CPU time 14.21 seconds
Started Jul 07 05:36:04 PM PDT 24
Finished Jul 07 05:36:18 PM PDT 24
Peak memory 205012 kb
Host smart-85403990-46c7-491a-8724-102ad3c65304
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161805209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_rd.161805209
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.1235457342
Short name T1114
Test name
Test status
Simulation time 19955115260 ps
CPU time 8.03 seconds
Started Jul 07 05:36:02 PM PDT 24
Finished Jul 07 05:36:11 PM PDT 24
Peak memory 205020 kb
Host smart-31298e3e-4abf-4f5a-aaac-3b40bd8573fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235457342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.1235457342
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.1669640440
Short name T520
Test name
Test status
Simulation time 2754667548 ps
CPU time 109.96 seconds
Started Jul 07 05:35:59 PM PDT 24
Finished Jul 07 05:37:49 PM PDT 24
Peak memory 693424 kb
Host smart-68f47aba-9456-43ca-a391-ee447cdd4d00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669640440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.1669640440
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.1705561722
Short name T1036
Test name
Test status
Simulation time 4744644034 ps
CPU time 6.44 seconds
Started Jul 07 05:36:08 PM PDT 24
Finished Jul 07 05:36:14 PM PDT 24
Peak memory 217564 kb
Host smart-adf524d4-0854-42de-839d-8074d04c03cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705561722 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.1705561722
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.2347973564
Short name T387
Test name
Test status
Simulation time 391181173 ps
CPU time 5.57 seconds
Started Jul 07 05:36:03 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 204968 kb
Host smart-84ee79f0-5bcb-4446-876f-94e098a9db21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347973564 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.2347973564
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.391165116
Short name T9
Test name
Test status
Simulation time 41612922 ps
CPU time 0.64 seconds
Started Jul 07 05:36:11 PM PDT 24
Finished Jul 07 05:36:12 PM PDT 24
Peak memory 204592 kb
Host smart-f21e698d-a263-47ed-8ff0-ca38704065b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391165116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.391165116
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.2083648643
Short name T1476
Test name
Test status
Simulation time 418047176 ps
CPU time 4.22 seconds
Started Jul 07 05:36:03 PM PDT 24
Finished Jul 07 05:36:07 PM PDT 24
Peak memory 215456 kb
Host smart-e5db5dbf-f610-45a4-a495-5fe0870ea23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083648643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.2083648643
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.2165098216
Short name T723
Test name
Test status
Simulation time 211644965 ps
CPU time 10.37 seconds
Started Jul 07 05:36:05 PM PDT 24
Finished Jul 07 05:36:15 PM PDT 24
Peak memory 217920 kb
Host smart-8bbe9de0-8e3c-4aa2-914c-ad9314594f57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165098216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.2165098216
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.219989385
Short name T1023
Test name
Test status
Simulation time 3937651449 ps
CPU time 101.75 seconds
Started Jul 07 05:36:02 PM PDT 24
Finished Jul 07 05:37:45 PM PDT 24
Peak memory 873056 kb
Host smart-10bd8b93-46c9-42ae-a16d-5a1467df3dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219989385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.219989385
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.2447215627
Short name T516
Test name
Test status
Simulation time 2270249612 ps
CPU time 61.59 seconds
Started Jul 07 05:36:01 PM PDT 24
Finished Jul 07 05:37:03 PM PDT 24
Peak memory 645512 kb
Host smart-95c6412a-3ab2-4a7c-a6f2-f059b60981d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447215627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2447215627
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.2068961090
Short name T431
Test name
Test status
Simulation time 259039087 ps
CPU time 1.14 seconds
Started Jul 07 05:36:03 PM PDT 24
Finished Jul 07 05:36:05 PM PDT 24
Peak memory 204724 kb
Host smart-c69f2a89-7e02-48f4-b445-a36600e248f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068961090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.2068961090
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2512121908
Short name T347
Test name
Test status
Simulation time 799643266 ps
CPU time 10.09 seconds
Started Jul 07 05:36:02 PM PDT 24
Finished Jul 07 05:36:12 PM PDT 24
Peak memory 205060 kb
Host smart-11bd9bb4-4e54-46e5-a2e3-bb10328e036a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512121908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2512121908
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.4066939551
Short name T103
Test name
Test status
Simulation time 22249007735 ps
CPU time 119.6 seconds
Started Jul 07 05:36:02 PM PDT 24
Finished Jul 07 05:38:02 PM PDT 24
Peak memory 1337352 kb
Host smart-6e319fc2-9bda-4aab-aa7e-af308054cd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066939551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.4066939551
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.3047877855
Short name T745
Test name
Test status
Simulation time 430609020 ps
CPU time 6.29 seconds
Started Jul 07 05:36:08 PM PDT 24
Finished Jul 07 05:36:14 PM PDT 24
Peak memory 205048 kb
Host smart-57d7ebf5-3751-4d84-b765-60a1ea839bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047877855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.3047877855
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.3711359724
Short name T974
Test name
Test status
Simulation time 16544904938 ps
CPU time 23.31 seconds
Started Jul 07 05:36:06 PM PDT 24
Finished Jul 07 05:36:29 PM PDT 24
Peak memory 362988 kb
Host smart-6b5182ff-6678-491a-aef4-67d097dc7ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711359724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3711359724
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.3731911219
Short name T134
Test name
Test status
Simulation time 28255053 ps
CPU time 0.73 seconds
Started Jul 07 05:36:04 PM PDT 24
Finished Jul 07 05:36:05 PM PDT 24
Peak memory 204744 kb
Host smart-b42d318d-6fc5-44a1-848d-15f650952c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731911219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3731911219
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.2168142194
Short name T991
Test name
Test status
Simulation time 49697205312 ps
CPU time 747.5 seconds
Started Jul 07 05:36:06 PM PDT 24
Finished Jul 07 05:48:34 PM PDT 24
Peak memory 1583320 kb
Host smart-45b91293-780f-48eb-96c0-0e345b68606e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168142194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2168142194
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.361812843
Short name T504
Test name
Test status
Simulation time 95792244 ps
CPU time 1.11 seconds
Started Jul 07 05:36:08 PM PDT 24
Finished Jul 07 05:36:10 PM PDT 24
Peak memory 222576 kb
Host smart-c3e7b38d-3fcc-4d66-a8f4-ec7cb898351c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361812843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.361812843
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.194370211
Short name T548
Test name
Test status
Simulation time 10088473049 ps
CPU time 79.6 seconds
Started Jul 07 05:36:07 PM PDT 24
Finished Jul 07 05:37:27 PM PDT 24
Peak memory 406424 kb
Host smart-1e2f2441-58d7-4f7d-a482-7dba2a6a2f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194370211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.194370211
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.1109205378
Short name T643
Test name
Test status
Simulation time 2328361658 ps
CPU time 11.85 seconds
Started Jul 07 05:36:07 PM PDT 24
Finished Jul 07 05:36:19 PM PDT 24
Peak memory 215564 kb
Host smart-0764729d-e2a1-4796-aedd-120babbd474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109205378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.1109205378
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.21581857
Short name T318
Test name
Test status
Simulation time 1323767683 ps
CPU time 3.83 seconds
Started Jul 07 05:36:05 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 213092 kb
Host smart-bfa9bb72-e20d-4638-998e-4be8d742ad07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21581857 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_bad_addr.21581857
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.180836195
Short name T1377
Test name
Test status
Simulation time 422274477 ps
CPU time 1.49 seconds
Started Jul 07 05:36:09 PM PDT 24
Finished Jul 07 05:36:11 PM PDT 24
Peak memory 204988 kb
Host smart-ac01e91e-d095-41d7-873d-732994d7e3b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180836195 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_acq.180836195
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.977411583
Short name T905
Test name
Test status
Simulation time 256867407 ps
CPU time 1.42 seconds
Started Jul 07 05:36:07 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 206692 kb
Host smart-31f069be-70d3-40a4-82a3-0a0edcb3719f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977411583 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.977411583
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.3058506236
Short name T262
Test name
Test status
Simulation time 8425227745 ps
CPU time 2.87 seconds
Started Jul 07 05:36:08 PM PDT 24
Finished Jul 07 05:36:11 PM PDT 24
Peak memory 205124 kb
Host smart-d0ae678a-adc8-4b25-b9d2-c65e5a20cbea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058506236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.3058506236
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.2100981950
Short name T409
Test name
Test status
Simulation time 260587224 ps
CPU time 0.99 seconds
Started Jul 07 05:36:06 PM PDT 24
Finished Jul 07 05:36:08 PM PDT 24
Peak memory 204804 kb
Host smart-9268c9b7-c5f4-463a-b63a-129d58182ce0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100981950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.2100981950
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.2057707889
Short name T521
Test name
Test status
Simulation time 803149905 ps
CPU time 4.73 seconds
Started Jul 07 05:36:07 PM PDT 24
Finished Jul 07 05:36:12 PM PDT 24
Peak memory 206548 kb
Host smart-a3c76cb3-99ea-4d2e-8d82-5b40465dfbbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057707889 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.2057707889
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.914819176
Short name T401
Test name
Test status
Simulation time 4676483118 ps
CPU time 43.19 seconds
Started Jul 07 05:36:03 PM PDT 24
Finished Jul 07 05:36:46 PM PDT 24
Peak memory 1232204 kb
Host smart-bc56273b-b466-4458-b098-ae810f55ff19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914819176 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.914819176
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3491281325
Short name T830
Test name
Test status
Simulation time 7516412198 ps
CPU time 46.5 seconds
Started Jul 07 05:36:03 PM PDT 24
Finished Jul 07 05:36:50 PM PDT 24
Peak memory 205056 kb
Host smart-99f7e4cf-4a61-443d-8250-92e0d6d4bf20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491281325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3491281325
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.2553559998
Short name T1142
Test name
Test status
Simulation time 8903855372 ps
CPU time 33.56 seconds
Started Jul 07 05:36:02 PM PDT 24
Finished Jul 07 05:36:36 PM PDT 24
Peak memory 205048 kb
Host smart-56e38197-55dc-4d93-bc4b-fc60789308a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553559998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.2553559998
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2162656085
Short name T1445
Test name
Test status
Simulation time 20899848863 ps
CPU time 20.4 seconds
Started Jul 07 05:36:05 PM PDT 24
Finished Jul 07 05:36:26 PM PDT 24
Peak memory 205084 kb
Host smart-eb75bce2-ca42-4956-b1e0-a7aa71d246d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162656085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2162656085
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.3430984822
Short name T717
Test name
Test status
Simulation time 3678424838 ps
CPU time 55.52 seconds
Started Jul 07 05:36:08 PM PDT 24
Finished Jul 07 05:37:04 PM PDT 24
Peak memory 889496 kb
Host smart-72649264-3012-42d5-96b1-2b2251e31a73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430984822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.3430984822
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.1513275267
Short name T327
Test name
Test status
Simulation time 5999250490 ps
CPU time 7.02 seconds
Started Jul 07 05:36:01 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 213660 kb
Host smart-88b4f3ea-da05-4d7f-9ceb-4d7d27692db9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513275267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.1513275267
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.4022515240
Short name T712
Test name
Test status
Simulation time 149866449 ps
CPU time 3.28 seconds
Started Jul 07 05:36:06 PM PDT 24
Finished Jul 07 05:36:10 PM PDT 24
Peak memory 204976 kb
Host smart-e564e9ad-122b-411f-82c5-e2cc1b6e911f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022515240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.4022515240
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2049599364
Short name T863
Test name
Test status
Simulation time 22314539 ps
CPU time 0.62 seconds
Started Jul 07 05:36:14 PM PDT 24
Finished Jul 07 05:36:15 PM PDT 24
Peak memory 204528 kb
Host smart-b7ea1b4a-f89c-4b46-bf2c-cc2f8103fe1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049599364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2049599364
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.1771353725
Short name T1204
Test name
Test status
Simulation time 91689006 ps
CPU time 3.07 seconds
Started Jul 07 05:36:12 PM PDT 24
Finished Jul 07 05:36:16 PM PDT 24
Peak memory 213356 kb
Host smart-885b918e-f4fe-4b56-b576-6a12c8505d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771353725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.1771353725
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3303946257
Short name T495
Test name
Test status
Simulation time 3288257753 ps
CPU time 8.97 seconds
Started Jul 07 05:36:09 PM PDT 24
Finished Jul 07 05:36:19 PM PDT 24
Peak memory 285680 kb
Host smart-560d4c74-26b5-47c7-8eb9-a3d876b59e81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303946257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3303946257
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.477015452
Short name T754
Test name
Test status
Simulation time 23838181005 ps
CPU time 40.59 seconds
Started Jul 07 05:36:07 PM PDT 24
Finished Jul 07 05:36:48 PM PDT 24
Peak memory 326524 kb
Host smart-8de4783b-8412-477b-8761-689baa5cfff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477015452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.477015452
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.2825253169
Short name T537
Test name
Test status
Simulation time 4794171771 ps
CPU time 193.09 seconds
Started Jul 07 05:36:08 PM PDT 24
Finished Jul 07 05:39:21 PM PDT 24
Peak memory 803716 kb
Host smart-26bf16d3-6999-432b-8f05-b4fdd945364e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825253169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.2825253169
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.1106913641
Short name T784
Test name
Test status
Simulation time 754822319 ps
CPU time 10.33 seconds
Started Jul 07 05:36:12 PM PDT 24
Finished Jul 07 05:36:23 PM PDT 24
Peak memory 205056 kb
Host smart-3f70d251-6086-43c7-ad29-a360a4a2bc47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106913641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.1106913641
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.3152836048
Short name T1463
Test name
Test status
Simulation time 24190980098 ps
CPU time 147.14 seconds
Started Jul 07 05:36:09 PM PDT 24
Finished Jul 07 05:38:36 PM PDT 24
Peak memory 1354572 kb
Host smart-c0cab36e-85f2-4c45-ad65-9294228c03a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152836048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.3152836048
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.3291592827
Short name T1068
Test name
Test status
Simulation time 1975345628 ps
CPU time 5.79 seconds
Started Jul 07 05:36:10 PM PDT 24
Finished Jul 07 05:36:16 PM PDT 24
Peak memory 205080 kb
Host smart-33e085b6-78b6-4a4a-b0b4-33573b2c5d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291592827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.3291592827
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.3203818685
Short name T1215
Test name
Test status
Simulation time 2796305721 ps
CPU time 47.71 seconds
Started Jul 07 05:36:17 PM PDT 24
Finished Jul 07 05:37:05 PM PDT 24
Peak memory 455660 kb
Host smart-f3a42efe-3a9e-4cd8-be10-8a347b5ae73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203818685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.3203818685
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.2642779425
Short name T1220
Test name
Test status
Simulation time 41825292 ps
CPU time 0.63 seconds
Started Jul 07 05:36:08 PM PDT 24
Finished Jul 07 05:36:10 PM PDT 24
Peak memory 204712 kb
Host smart-7ffaf8ec-bcb3-4d0b-b3c3-900f430adc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642779425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2642779425
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3142739393
Short name T1243
Test name
Test status
Simulation time 4767096461 ps
CPU time 48.68 seconds
Started Jul 07 05:36:08 PM PDT 24
Finished Jul 07 05:36:57 PM PDT 24
Peak memory 237756 kb
Host smart-eaf6a910-fbc0-4ccd-b0b4-bd64ac20675c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142739393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3142739393
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.1670868913
Short name T601
Test name
Test status
Simulation time 5819422978 ps
CPU time 41.67 seconds
Started Jul 07 05:36:12 PM PDT 24
Finished Jul 07 05:36:55 PM PDT 24
Peak memory 205028 kb
Host smart-265aba9c-6af0-4c1b-8cec-ca182eeec4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670868913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.1670868913
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.878474575
Short name T1022
Test name
Test status
Simulation time 1557825072 ps
CPU time 23.41 seconds
Started Jul 07 05:36:12 PM PDT 24
Finished Jul 07 05:36:36 PM PDT 24
Peak memory 345480 kb
Host smart-02b906af-791d-459e-98eb-be0ab445ea67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878474575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.878474575
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.611364911
Short name T105
Test name
Test status
Simulation time 227486593733 ps
CPU time 512.06 seconds
Started Jul 07 05:36:14 PM PDT 24
Finished Jul 07 05:44:47 PM PDT 24
Peak memory 2753004 kb
Host smart-6de799db-98b3-4121-8c54-b507de4bcc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611364911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.611364911
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.887186379
Short name T645
Test name
Test status
Simulation time 4292806082 ps
CPU time 19.67 seconds
Started Jul 07 05:36:13 PM PDT 24
Finished Jul 07 05:36:33 PM PDT 24
Peak memory 229692 kb
Host smart-11d91d2a-7b4a-4149-9822-9d61fdb29f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887186379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.887186379
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2219793154
Short name T1422
Test name
Test status
Simulation time 1146524149 ps
CPU time 3 seconds
Started Jul 07 05:36:09 PM PDT 24
Finished Jul 07 05:36:12 PM PDT 24
Peak memory 205016 kb
Host smart-e367cc7d-2c4d-41db-b586-bc47f7745e06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219793154 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2219793154
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.416261656
Short name T756
Test name
Test status
Simulation time 1529807416 ps
CPU time 1.39 seconds
Started Jul 07 05:36:13 PM PDT 24
Finished Jul 07 05:36:15 PM PDT 24
Peak memory 213220 kb
Host smart-21d9c6c1-be53-4bd3-83fe-c6d27cd07db6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416261656 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_acq.416261656
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.1029819236
Short name T634
Test name
Test status
Simulation time 240860884 ps
CPU time 1.36 seconds
Started Jul 07 05:36:08 PM PDT 24
Finished Jul 07 05:36:10 PM PDT 24
Peak memory 213012 kb
Host smart-aaec32f8-ccb1-4982-8df1-fe316c3fbdaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029819236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.1029819236
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.1702266827
Short name T1158
Test name
Test status
Simulation time 402697549 ps
CPU time 2.42 seconds
Started Jul 07 05:36:11 PM PDT 24
Finished Jul 07 05:36:14 PM PDT 24
Peak memory 204996 kb
Host smart-fbec0554-70eb-4f14-9bc2-da79d604128b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702266827 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.1702266827
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.505265638
Short name T486
Test name
Test status
Simulation time 281780659 ps
CPU time 1.32 seconds
Started Jul 07 05:36:17 PM PDT 24
Finished Jul 07 05:36:19 PM PDT 24
Peak memory 204804 kb
Host smart-8fe2c58c-2bb1-4f66-a512-67f9908ea915
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505265638 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.505265638
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.2292153504
Short name T778
Test name
Test status
Simulation time 767957674 ps
CPU time 2.73 seconds
Started Jul 07 05:36:13 PM PDT 24
Finished Jul 07 05:36:16 PM PDT 24
Peak memory 205060 kb
Host smart-cb2094e7-4c06-42d8-83f5-936b12d59d43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292153504 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.2292153504
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.3622011389
Short name T1085
Test name
Test status
Simulation time 1660799964 ps
CPU time 5.21 seconds
Started Jul 07 05:36:13 PM PDT 24
Finished Jul 07 05:36:19 PM PDT 24
Peak memory 216480 kb
Host smart-1042ba52-cbf8-4887-b1aa-e99385d4473b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622011389 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.3622011389
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.976414393
Short name T425
Test name
Test status
Simulation time 14680040124 ps
CPU time 67.38 seconds
Started Jul 07 05:36:14 PM PDT 24
Finished Jul 07 05:37:22 PM PDT 24
Peak memory 1043356 kb
Host smart-e683ba1b-67ec-40a4-a5ed-0e8141d17bc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976414393 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.976414393
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.3120259546
Short name T464
Test name
Test status
Simulation time 830665187 ps
CPU time 12.32 seconds
Started Jul 07 05:36:09 PM PDT 24
Finished Jul 07 05:36:22 PM PDT 24
Peak memory 204952 kb
Host smart-cd8e9dc9-d2d7-4200-9b25-6cea13b7f923
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120259546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.3120259546
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.666807052
Short name T499
Test name
Test status
Simulation time 2221136428 ps
CPU time 45.62 seconds
Started Jul 07 05:36:11 PM PDT 24
Finished Jul 07 05:36:57 PM PDT 24
Peak memory 205832 kb
Host smart-f5efcaef-f994-499e-91fc-42c27674c7b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666807052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.666807052
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.523982232
Short name T360
Test name
Test status
Simulation time 37733123786 ps
CPU time 69.72 seconds
Started Jul 07 05:36:09 PM PDT 24
Finished Jul 07 05:37:20 PM PDT 24
Peak memory 1223372 kb
Host smart-068bf17e-a42a-47a6-afbf-b449feadb406
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523982232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_wr.523982232
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.709246386
Short name T1056
Test name
Test status
Simulation time 1880615720 ps
CPU time 43.65 seconds
Started Jul 07 05:36:14 PM PDT 24
Finished Jul 07 05:36:58 PM PDT 24
Peak memory 412752 kb
Host smart-ce222baf-b743-4c25-a381-aa0d9a0b48b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709246386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_t
arget_stretch.709246386
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2264899934
Short name T557
Test name
Test status
Simulation time 1140688100 ps
CPU time 6.59 seconds
Started Jul 07 05:36:14 PM PDT 24
Finished Jul 07 05:36:21 PM PDT 24
Peak memory 220416 kb
Host smart-3b9744b1-a6ed-4a69-bee7-d8bc6472bd61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264899934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2264899934
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.1062974992
Short name T313
Test name
Test status
Simulation time 16967761 ps
CPU time 0.66 seconds
Started Jul 07 05:36:20 PM PDT 24
Finished Jul 07 05:36:21 PM PDT 24
Peak memory 204456 kb
Host smart-0ee67f2e-67b2-48f0-bdf8-a93417f836ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062974992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.1062974992
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.1992247899
Short name T983
Test name
Test status
Simulation time 132021164 ps
CPU time 1.47 seconds
Started Jul 07 05:36:16 PM PDT 24
Finished Jul 07 05:36:17 PM PDT 24
Peak memory 213316 kb
Host smart-4e42f2ab-fe6a-4330-809b-6d3267fde2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992247899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1992247899
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.1768475216
Short name T311
Test name
Test status
Simulation time 1968515272 ps
CPU time 11.03 seconds
Started Jul 07 05:36:16 PM PDT 24
Finished Jul 07 05:36:28 PM PDT 24
Peak memory 309860 kb
Host smart-cdc18992-78cf-4bf5-961a-d1f2ac787dba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768475216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.1768475216
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.97165418
Short name T76
Test name
Test status
Simulation time 1464015912 ps
CPU time 90.94 seconds
Started Jul 07 05:36:16 PM PDT 24
Finished Jul 07 05:37:47 PM PDT 24
Peak memory 554652 kb
Host smart-72a6ebfa-0098-47f4-9347-725218d50b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97165418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.97165418
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.2756056194
Short name T1187
Test name
Test status
Simulation time 9627379537 ps
CPU time 85.2 seconds
Started Jul 07 05:36:13 PM PDT 24
Finished Jul 07 05:37:39 PM PDT 24
Peak memory 740568 kb
Host smart-e8fbade4-3052-4058-93ef-086d7206c25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756056194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2756056194
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.2841364630
Short name T960
Test name
Test status
Simulation time 341862242 ps
CPU time 1.07 seconds
Started Jul 07 05:36:17 PM PDT 24
Finished Jul 07 05:36:18 PM PDT 24
Peak memory 204716 kb
Host smart-7cc7ae86-bdf4-412b-b795-2d7b7d417dda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841364630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.2841364630
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.1167549976
Short name T554
Test name
Test status
Simulation time 238251676 ps
CPU time 4.94 seconds
Started Jul 07 05:36:12 PM PDT 24
Finished Jul 07 05:36:18 PM PDT 24
Peak memory 235344 kb
Host smart-658aacda-6f56-4601-9027-09601fb7d134
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167549976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.1167549976
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1089901846
Short name T1064
Test name
Test status
Simulation time 83340888242 ps
CPU time 369.64 seconds
Started Jul 07 05:36:18 PM PDT 24
Finished Jul 07 05:42:28 PM PDT 24
Peak memory 1357980 kb
Host smart-5c01df8f-b6ce-4f6b-9d1f-e66df6ad87d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089901846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1089901846
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.134664992
Short name T986
Test name
Test status
Simulation time 501804961 ps
CPU time 7.46 seconds
Started Jul 07 05:36:20 PM PDT 24
Finished Jul 07 05:36:28 PM PDT 24
Peak memory 205044 kb
Host smart-6af5aeff-80eb-46ca-a89a-517fc82149ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134664992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.134664992
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.341276757
Short name T69
Test name
Test status
Simulation time 16512992994 ps
CPU time 64.18 seconds
Started Jul 07 05:36:19 PM PDT 24
Finished Jul 07 05:37:23 PM PDT 24
Peak memory 278272 kb
Host smart-57a35551-4c57-49c2-9969-7b134cd80313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341276757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.341276757
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.3466721539
Short name T828
Test name
Test status
Simulation time 48411112 ps
CPU time 0.66 seconds
Started Jul 07 05:36:17 PM PDT 24
Finished Jul 07 05:36:18 PM PDT 24
Peak memory 204680 kb
Host smart-7639547c-2918-4958-802c-9d811ace6f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466721539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3466721539
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3180723821
Short name T720
Test name
Test status
Simulation time 3648556165 ps
CPU time 21.36 seconds
Started Jul 07 05:36:16 PM PDT 24
Finished Jul 07 05:36:38 PM PDT 24
Peak memory 229612 kb
Host smart-f3f7e890-c834-44b1-87b9-1d99596f2981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180723821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3180723821
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.1727813738
Short name T968
Test name
Test status
Simulation time 171381011 ps
CPU time 5.93 seconds
Started Jul 07 05:36:15 PM PDT 24
Finished Jul 07 05:36:21 PM PDT 24
Peak memory 222720 kb
Host smart-f2c5addd-c713-43dd-a55e-2692cd2d2f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727813738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.1727813738
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1112373200
Short name T1528
Test name
Test status
Simulation time 3339199037 ps
CPU time 34.61 seconds
Started Jul 07 05:36:18 PM PDT 24
Finished Jul 07 05:36:53 PM PDT 24
Peak memory 398056 kb
Host smart-243a3163-8751-4389-a35f-7f0151bf037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112373200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1112373200
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.311800591
Short name T1448
Test name
Test status
Simulation time 246566125803 ps
CPU time 1465.77 seconds
Started Jul 07 05:36:18 PM PDT 24
Finished Jul 07 06:00:44 PM PDT 24
Peak memory 2242692 kb
Host smart-00c48157-9b7d-4bdd-9801-69d484d5b6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311800591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.311800591
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.3157086340
Short name T1435
Test name
Test status
Simulation time 1564202210 ps
CPU time 24.95 seconds
Started Jul 07 05:36:14 PM PDT 24
Finished Jul 07 05:36:40 PM PDT 24
Peak memory 229496 kb
Host smart-350c3749-8a3a-4153-82c3-6602f331e533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157086340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3157086340
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2136921360
Short name T1494
Test name
Test status
Simulation time 1451105935 ps
CPU time 3.73 seconds
Started Jul 07 05:36:17 PM PDT 24
Finished Jul 07 05:36:22 PM PDT 24
Peak memory 213208 kb
Host smart-a1c11c91-e866-47e7-8602-ce96394656b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136921360 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2136921360
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.2915365559
Short name T1441
Test name
Test status
Simulation time 152707416 ps
CPU time 1.04 seconds
Started Jul 07 05:36:25 PM PDT 24
Finished Jul 07 05:36:26 PM PDT 24
Peak memory 204788 kb
Host smart-636374c7-a182-4d77-9804-dd7afdb79e12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915365559 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.2915365559
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.1545326406
Short name T917
Test name
Test status
Simulation time 376915945 ps
CPU time 1.35 seconds
Started Jul 07 05:36:17 PM PDT 24
Finished Jul 07 05:36:18 PM PDT 24
Peak memory 204968 kb
Host smart-21c15e28-3d53-453a-bb93-5f4b20844270
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545326406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.1545326406
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.1569994722
Short name T1509
Test name
Test status
Simulation time 967781855 ps
CPU time 2.55 seconds
Started Jul 07 05:36:19 PM PDT 24
Finished Jul 07 05:36:22 PM PDT 24
Peak memory 205024 kb
Host smart-a1588ef1-9358-4f3c-8603-a81d43c63cd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569994722 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.1569994722
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.888167565
Short name T887
Test name
Test status
Simulation time 175720388 ps
CPU time 1.31 seconds
Started Jul 07 05:36:22 PM PDT 24
Finished Jul 07 05:36:24 PM PDT 24
Peak memory 204788 kb
Host smart-3deea6ae-13f6-4d55-be49-5ac850ed8627
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888167565 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.888167565
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1300459958
Short name T1046
Test name
Test status
Simulation time 793850650 ps
CPU time 3.34 seconds
Started Jul 07 05:36:21 PM PDT 24
Finished Jul 07 05:36:25 PM PDT 24
Peak memory 205052 kb
Host smart-fc3d949a-4e9f-4e4c-9218-f6bbea0f7978
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300459958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.1300459958
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.832994296
Short name T1218
Test name
Test status
Simulation time 1755082389 ps
CPU time 4.87 seconds
Started Jul 07 05:36:19 PM PDT 24
Finished Jul 07 05:36:24 PM PDT 24
Peak memory 214524 kb
Host smart-019a8596-3ea0-4607-90ce-90eb85d73411
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832994296 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_intr_smoke.832994296
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.2856307328
Short name T1061
Test name
Test status
Simulation time 17503971217 ps
CPU time 324.47 seconds
Started Jul 07 05:36:19 PM PDT 24
Finished Jul 07 05:41:44 PM PDT 24
Peak memory 4169004 kb
Host smart-9c1b29d5-1e4d-4934-a73f-45e5999a531e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856307328 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.2856307328
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.507108884
Short name T441
Test name
Test status
Simulation time 635500933 ps
CPU time 7.67 seconds
Started Jul 07 05:36:15 PM PDT 24
Finished Jul 07 05:36:23 PM PDT 24
Peak memory 204996 kb
Host smart-e0126d99-f17b-4aeb-88ee-5719c8fe153d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507108884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_tar
get_smoke.507108884
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.2583222254
Short name T410
Test name
Test status
Simulation time 1384990788 ps
CPU time 29.22 seconds
Started Jul 07 05:36:16 PM PDT 24
Finished Jul 07 05:36:46 PM PDT 24
Peak memory 204952 kb
Host smart-3ec3e140-44ac-4971-bc1d-b5350cd30400
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583222254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.2583222254
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.1082518708
Short name T806
Test name
Test status
Simulation time 13776336379 ps
CPU time 26.19 seconds
Started Jul 07 05:36:14 PM PDT 24
Finished Jul 07 05:36:41 PM PDT 24
Peak memory 205036 kb
Host smart-825bc742-2955-4721-abb9-17c190ef77bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082518708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.1082518708
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.1971952000
Short name T444
Test name
Test status
Simulation time 3802356151 ps
CPU time 82.68 seconds
Started Jul 07 05:36:18 PM PDT 24
Finished Jul 07 05:37:42 PM PDT 24
Peak memory 565556 kb
Host smart-86c1ecaa-c5ee-4f07-970c-426f46645896
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971952000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.1971952000
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.1946931181
Short name T269
Test name
Test status
Simulation time 5985652963 ps
CPU time 7.78 seconds
Started Jul 07 05:36:15 PM PDT 24
Finished Jul 07 05:36:23 PM PDT 24
Peak memory 221288 kb
Host smart-5c304c4f-1c9c-4f54-b87b-a496d972f71d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946931181 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.1946931181
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.4170987262
Short name T411
Test name
Test status
Simulation time 277064754 ps
CPU time 3.85 seconds
Started Jul 07 05:36:27 PM PDT 24
Finished Jul 07 05:36:31 PM PDT 24
Peak memory 205024 kb
Host smart-6a1a8184-70dd-4af3-b45c-dbd8fd0276e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170987262 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.4170987262
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1734377681
Short name T87
Test name
Test status
Simulation time 18071244 ps
CPU time 0.63 seconds
Started Jul 07 05:36:27 PM PDT 24
Finished Jul 07 05:36:28 PM PDT 24
Peak memory 204456 kb
Host smart-3fb6c84f-1467-40ab-a806-8c8b56997e24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734377681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1734377681
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3637019410
Short name T43
Test name
Test status
Simulation time 167426919 ps
CPU time 2.11 seconds
Started Jul 07 05:36:27 PM PDT 24
Finished Jul 07 05:36:30 PM PDT 24
Peak memory 213296 kb
Host smart-16632b60-9cc8-4ebc-82b7-36bdaf1c02c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637019410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3637019410
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2558681787
Short name T1397
Test name
Test status
Simulation time 891878198 ps
CPU time 20.61 seconds
Started Jul 07 05:36:20 PM PDT 24
Finished Jul 07 05:36:40 PM PDT 24
Peak memory 283584 kb
Host smart-4ef242f8-8ecb-4f36-85b4-e2f32b9b2239
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558681787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2558681787
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.4067181009
Short name T943
Test name
Test status
Simulation time 5586985060 ps
CPU time 41.41 seconds
Started Jul 07 05:36:18 PM PDT 24
Finished Jul 07 05:36:59 PM PDT 24
Peak memory 537748 kb
Host smart-02b3c66f-f48b-4693-b76e-7dd90dd44126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067181009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.4067181009
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.1384071429
Short name T728
Test name
Test status
Simulation time 1441729415 ps
CPU time 41.91 seconds
Started Jul 07 05:36:21 PM PDT 24
Finished Jul 07 05:37:03 PM PDT 24
Peak memory 463748 kb
Host smart-7d0db629-3197-424a-b588-373b64750b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384071429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.1384071429
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.1010603415
Short name T1170
Test name
Test status
Simulation time 409341093 ps
CPU time 1.17 seconds
Started Jul 07 05:36:25 PM PDT 24
Finished Jul 07 05:36:27 PM PDT 24
Peak memory 204752 kb
Host smart-e34cb809-680f-4073-a930-398e8931f6f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010603415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.1010603415
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.3566291638
Short name T445
Test name
Test status
Simulation time 567539262 ps
CPU time 8.28 seconds
Started Jul 07 05:36:21 PM PDT 24
Finished Jul 07 05:36:30 PM PDT 24
Peak memory 229592 kb
Host smart-09103b3c-2022-408c-a8b7-9469ef85a5dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566291638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.3566291638
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.3987309896
Short name T934
Test name
Test status
Simulation time 16778898029 ps
CPU time 109.88 seconds
Started Jul 07 05:36:22 PM PDT 24
Finished Jul 07 05:38:12 PM PDT 24
Peak memory 1221504 kb
Host smart-6463c702-6a8f-4b95-a061-f37cdea2edde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987309896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.3987309896
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.2801982577
Short name T1334
Test name
Test status
Simulation time 1830665965 ps
CPU time 19.69 seconds
Started Jul 07 05:36:30 PM PDT 24
Finished Jul 07 05:36:50 PM PDT 24
Peak memory 205028 kb
Host smart-013a6674-12b0-44a4-85c5-1cdf5199ad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801982577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.2801982577
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.2145819
Short name T989
Test name
Test status
Simulation time 1888283436 ps
CPU time 83.02 seconds
Started Jul 07 05:36:27 PM PDT 24
Finished Jul 07 05:37:51 PM PDT 24
Peak memory 270124 kb
Host smart-a745966a-3448-4b16-a2b2-cd7f2314b09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.2145819
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.2628945383
Short name T1265
Test name
Test status
Simulation time 30303276 ps
CPU time 0.71 seconds
Started Jul 07 05:36:21 PM PDT 24
Finished Jul 07 05:36:23 PM PDT 24
Peak memory 204716 kb
Host smart-f677e146-51f8-473c-ac30-7824d7e3f07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628945383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2628945383
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.2284638107
Short name T590
Test name
Test status
Simulation time 511743080 ps
CPU time 9.41 seconds
Started Jul 07 05:36:24 PM PDT 24
Finished Jul 07 05:36:33 PM PDT 24
Peak memory 317664 kb
Host smart-7002112e-fd77-49d4-8140-c9dfec7af21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284638107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.2284638107
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.4065483304
Short name T726
Test name
Test status
Simulation time 2779874357 ps
CPU time 17.3 seconds
Started Jul 07 05:36:25 PM PDT 24
Finished Jul 07 05:36:43 PM PDT 24
Peak memory 366124 kb
Host smart-0a3de214-f4a0-47b6-8a94-27607eadf29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065483304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.4065483304
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1581357596
Short name T1037
Test name
Test status
Simulation time 2391194716 ps
CPU time 63.88 seconds
Started Jul 07 05:36:19 PM PDT 24
Finished Jul 07 05:37:23 PM PDT 24
Peak memory 310456 kb
Host smart-a77f30a0-36af-45ca-ad63-59599c9fc75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581357596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1581357596
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.1028522729
Short name T64
Test name
Test status
Simulation time 111389484526 ps
CPU time 2131.48 seconds
Started Jul 07 05:36:21 PM PDT 24
Finished Jul 07 06:11:53 PM PDT 24
Peak memory 2900592 kb
Host smart-623357d8-4de3-4eee-a69b-a825e30bf84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028522729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.1028522729
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.3198536875
Short name T1400
Test name
Test status
Simulation time 5459862275 ps
CPU time 35.13 seconds
Started Jul 07 05:36:18 PM PDT 24
Finished Jul 07 05:36:54 PM PDT 24
Peak memory 213216 kb
Host smart-c246cce5-1cba-4008-9a74-faea8305d56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198536875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3198536875
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1038468959
Short name T1233
Test name
Test status
Simulation time 1059450748 ps
CPU time 5.09 seconds
Started Jul 07 05:36:23 PM PDT 24
Finished Jul 07 05:36:29 PM PDT 24
Peak memory 213248 kb
Host smart-e4f29838-4ffc-4f5e-a461-47843a31dc8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038468959 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1038468959
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.630023212
Short name T539
Test name
Test status
Simulation time 286585099 ps
CPU time 1.23 seconds
Started Jul 07 05:36:24 PM PDT 24
Finished Jul 07 05:36:26 PM PDT 24
Peak memory 204988 kb
Host smart-75fa42f4-d826-4348-8adf-ace368f4f2c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630023212 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_acq.630023212
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1075220826
Short name T1475
Test name
Test status
Simulation time 638376586 ps
CPU time 1.31 seconds
Started Jul 07 05:36:22 PM PDT 24
Finished Jul 07 05:36:24 PM PDT 24
Peak memory 205056 kb
Host smart-7c01758a-5bae-4260-9b04-77f399fbff14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075220826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1075220826
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.3309086431
Short name T1257
Test name
Test status
Simulation time 177317161 ps
CPU time 1.29 seconds
Started Jul 07 05:36:27 PM PDT 24
Finished Jul 07 05:36:28 PM PDT 24
Peak memory 204744 kb
Host smart-a0f0d177-3399-4973-9ab4-5ddc3059a6a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309086431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.3309086431
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.2523310247
Short name T1159
Test name
Test status
Simulation time 331802003 ps
CPU time 1.3 seconds
Started Jul 07 05:36:28 PM PDT 24
Finished Jul 07 05:36:30 PM PDT 24
Peak memory 204792 kb
Host smart-731ba930-de54-45a0-98cd-081a39721824
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523310247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.2523310247
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.1505865858
Short name T335
Test name
Test status
Simulation time 2114592677 ps
CPU time 5.54 seconds
Started Jul 07 05:36:21 PM PDT 24
Finished Jul 07 05:36:27 PM PDT 24
Peak memory 204992 kb
Host smart-23fa7450-0d8f-4389-88be-2e0e4a86447d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505865858 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.1505865858
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.3293380448
Short name T88
Test name
Test status
Simulation time 5882671938 ps
CPU time 23.55 seconds
Started Jul 07 05:36:21 PM PDT 24
Finished Jul 07 05:36:46 PM PDT 24
Peak memory 852588 kb
Host smart-0a8b1987-b230-468b-abea-b6951f19c184
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293380448 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.3293380448
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.174868825
Short name T394
Test name
Test status
Simulation time 925711431 ps
CPU time 12.3 seconds
Started Jul 07 05:36:23 PM PDT 24
Finished Jul 07 05:36:35 PM PDT 24
Peak memory 204908 kb
Host smart-604c369d-608d-4ead-accf-49ba0c1a7661
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174868825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_tar
get_smoke.174868825
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.705237
Short name T1042
Test name
Test status
Simulation time 415184741 ps
CPU time 17.34 seconds
Started Jul 07 05:36:22 PM PDT 24
Finished Jul 07 05:36:40 PM PDT 24
Peak memory 205048 kb
Host smart-13152472-faf4-475a-afcb-737b921a0f94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2
c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_stress_rd.705237
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.1380691028
Short name T124
Test name
Test status
Simulation time 25419187623 ps
CPU time 72.08 seconds
Started Jul 07 05:36:25 PM PDT 24
Finished Jul 07 05:37:38 PM PDT 24
Peak memory 1158584 kb
Host smart-24c04b65-0e07-4d25-9d47-9b4d1d02923b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380691028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.1380691028
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.852976045
Short name T1143
Test name
Test status
Simulation time 1046911146 ps
CPU time 16.12 seconds
Started Jul 07 05:36:22 PM PDT 24
Finished Jul 07 05:36:38 PM PDT 24
Peak memory 402000 kb
Host smart-b28fab99-334f-4de2-bb10-ff7b022d5108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852976045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.852976045
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.792221025
Short name T618
Test name
Test status
Simulation time 5283673763 ps
CPU time 7.31 seconds
Started Jul 07 05:36:22 PM PDT 24
Finished Jul 07 05:36:30 PM PDT 24
Peak memory 219940 kb
Host smart-b580c38f-38dc-4403-896c-d37625c09cd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792221025 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_timeout.792221025
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.95805741
Short name T22
Test name
Test status
Simulation time 297823970 ps
CPU time 4.97 seconds
Started Jul 07 05:36:28 PM PDT 24
Finished Jul 07 05:36:33 PM PDT 24
Peak memory 205028 kb
Host smart-12fc56be-a671-47c7-a4de-fd298cb0505d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95805741 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.95805741
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1323494861
Short name T1231
Test name
Test status
Simulation time 27149975 ps
CPU time 0.62 seconds
Started Jul 07 05:36:28 PM PDT 24
Finished Jul 07 05:36:29 PM PDT 24
Peak memory 204524 kb
Host smart-ecc7c5a4-315b-44c6-8530-79b1bc0a5bff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323494861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1323494861
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.549997137
Short name T984
Test name
Test status
Simulation time 694266414 ps
CPU time 2.61 seconds
Started Jul 07 05:36:27 PM PDT 24
Finished Jul 07 05:36:30 PM PDT 24
Peak memory 213316 kb
Host smart-886d1ca1-2145-4a81-bdd3-7c51415c9680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549997137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.549997137
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.94840170
Short name T443
Test name
Test status
Simulation time 291718773 ps
CPU time 5.54 seconds
Started Jul 07 05:36:25 PM PDT 24
Finished Jul 07 05:36:31 PM PDT 24
Peak memory 257896 kb
Host smart-0783821e-5d92-4a36-b433-edf123b49ea9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94840170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empty
.94840170
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.2248403162
Short name T83
Test name
Test status
Simulation time 15044283219 ps
CPU time 62.31 seconds
Started Jul 07 05:36:29 PM PDT 24
Finished Jul 07 05:37:32 PM PDT 24
Peak memory 696028 kb
Host smart-b4b213a6-8375-4c67-be4e-a264c472d1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248403162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.2248403162
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.3328157803
Short name T334
Test name
Test status
Simulation time 4429619909 ps
CPU time 160.73 seconds
Started Jul 07 05:36:30 PM PDT 24
Finished Jul 07 05:39:11 PM PDT 24
Peak memory 744812 kb
Host smart-cbe8c623-1ca9-418a-82ac-3940b58e9804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328157803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.3328157803
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.904030512
Short name T903
Test name
Test status
Simulation time 787742779 ps
CPU time 0.92 seconds
Started Jul 07 05:36:30 PM PDT 24
Finished Jul 07 05:36:32 PM PDT 24
Peak memory 204724 kb
Host smart-088e810a-98aa-4eb7-b880-10296061ce26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904030512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fm
t.904030512
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.67460445
Short name T1129
Test name
Test status
Simulation time 510970679 ps
CPU time 3.26 seconds
Started Jul 07 05:36:29 PM PDT 24
Finished Jul 07 05:36:33 PM PDT 24
Peak memory 226384 kb
Host smart-35d84267-ad25-4f13-9300-e111efc26fd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67460445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.67460445
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.4267882986
Short name T316
Test name
Test status
Simulation time 15705804205 ps
CPU time 98.42 seconds
Started Jul 07 05:36:31 PM PDT 24
Finished Jul 07 05:38:10 PM PDT 24
Peak memory 1066324 kb
Host smart-530034e3-2c55-4a0e-ac24-5fc7bce1e65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267882986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.4267882986
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.2155808218
Short name T1327
Test name
Test status
Simulation time 422841611 ps
CPU time 17 seconds
Started Jul 07 05:36:32 PM PDT 24
Finished Jul 07 05:36:49 PM PDT 24
Peak memory 204996 kb
Host smart-e18642ce-99b0-4102-a44f-b86b5d078ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155808218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2155808218
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.1906391947
Short name T1219
Test name
Test status
Simulation time 24654867894 ps
CPU time 87.69 seconds
Started Jul 07 05:36:29 PM PDT 24
Finished Jul 07 05:37:57 PM PDT 24
Peak memory 342252 kb
Host smart-ddcaa289-3b48-4073-947e-3e5cb34634ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906391947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.1906391947
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.4025533461
Short name T660
Test name
Test status
Simulation time 43663216 ps
CPU time 0.65 seconds
Started Jul 07 05:36:28 PM PDT 24
Finished Jul 07 05:36:29 PM PDT 24
Peak memory 204708 kb
Host smart-2cb8c827-2c1c-486b-9a02-854de891c483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025533461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.4025533461
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.4285246512
Short name T906
Test name
Test status
Simulation time 7806367216 ps
CPU time 60.88 seconds
Started Jul 07 05:36:31 PM PDT 24
Finished Jul 07 05:37:32 PM PDT 24
Peak memory 520720 kb
Host smart-80936653-49de-4a0d-adee-68a11bd78d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285246512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.4285246512
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.3551043632
Short name T1467
Test name
Test status
Simulation time 1455035697 ps
CPU time 27.87 seconds
Started Jul 07 05:36:29 PM PDT 24
Finished Jul 07 05:36:57 PM PDT 24
Peak memory 438980 kb
Host smart-65c629f4-29df-4a61-8f8a-8bd94a34fa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551043632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.3551043632
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.3666365255
Short name T894
Test name
Test status
Simulation time 1533621364 ps
CPU time 77.63 seconds
Started Jul 07 05:36:27 PM PDT 24
Finished Jul 07 05:37:45 PM PDT 24
Peak memory 365896 kb
Host smart-05bfbd5b-404f-44d6-9243-f881e68ee4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666365255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.3666365255
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.1901406937
Short name T116
Test name
Test status
Simulation time 9277498772 ps
CPU time 335.35 seconds
Started Jul 07 05:36:26 PM PDT 24
Finished Jul 07 05:42:02 PM PDT 24
Peak memory 1779000 kb
Host smart-79c87ae7-ae5f-423c-8a05-0cbeb5df841f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901406937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.1901406937
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.3827437605
Short name T636
Test name
Test status
Simulation time 4693041018 ps
CPU time 19.79 seconds
Started Jul 07 05:36:33 PM PDT 24
Finished Jul 07 05:36:53 PM PDT 24
Peak memory 213300 kb
Host smart-4595c110-9916-4bf1-87b2-9c615a9b8948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827437605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.3827437605
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.3020834212
Short name T1451
Test name
Test status
Simulation time 7444366540 ps
CPU time 4.08 seconds
Started Jul 07 05:36:31 PM PDT 24
Finished Jul 07 05:36:36 PM PDT 24
Peak memory 213284 kb
Host smart-63918ba9-79b3-4e33-b8f3-28068dfbd53c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020834212 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.3020834212
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2571287167
Short name T1508
Test name
Test status
Simulation time 1180369331 ps
CPU time 1.64 seconds
Started Jul 07 05:36:34 PM PDT 24
Finished Jul 07 05:36:36 PM PDT 24
Peak memory 211660 kb
Host smart-ee404521-d432-43c9-b236-56af05122811
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571287167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2571287167
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.1984487629
Short name T324
Test name
Test status
Simulation time 794114458 ps
CPU time 1.34 seconds
Started Jul 07 05:36:31 PM PDT 24
Finished Jul 07 05:36:32 PM PDT 24
Peak memory 204952 kb
Host smart-82f6f776-3b3b-4c6e-9095-b1fd0089a3e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984487629 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.1984487629
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.2951468892
Short name T1030
Test name
Test status
Simulation time 543214723 ps
CPU time 2.81 seconds
Started Jul 07 05:36:31 PM PDT 24
Finished Jul 07 05:36:34 PM PDT 24
Peak memory 204952 kb
Host smart-0e2ede9d-f986-4246-be03-8607e3ebac15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951468892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.2951468892
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.2471234437
Short name T1121
Test name
Test status
Simulation time 277924144 ps
CPU time 0.96 seconds
Started Jul 07 05:36:39 PM PDT 24
Finished Jul 07 05:36:41 PM PDT 24
Peak memory 204828 kb
Host smart-4c473133-4d9e-4879-982a-fbfad26b3050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471234437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.2471234437
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2738089771
Short name T1007
Test name
Test status
Simulation time 1092981654 ps
CPU time 5.16 seconds
Started Jul 07 05:36:30 PM PDT 24
Finished Jul 07 05:36:36 PM PDT 24
Peak memory 213260 kb
Host smart-1ed81a46-a2ca-4d59-bfe7-bc03ffa1fb17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738089771 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2738089771
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2945382671
Short name T1190
Test name
Test status
Simulation time 21272948120 ps
CPU time 15.78 seconds
Started Jul 07 05:36:28 PM PDT 24
Finished Jul 07 05:36:44 PM PDT 24
Peak memory 509000 kb
Host smart-1604853f-2ea1-4b71-91bd-89451a079b0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945382671 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2945382671
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.1324405731
Short name T469
Test name
Test status
Simulation time 1078787164 ps
CPU time 15.33 seconds
Started Jul 07 05:36:26 PM PDT 24
Finished Jul 07 05:36:42 PM PDT 24
Peak memory 204996 kb
Host smart-6154dd7d-97b7-4b4f-b41f-203d76ab06d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324405731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.1324405731
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.1838644964
Short name T496
Test name
Test status
Simulation time 1478230623 ps
CPU time 32.66 seconds
Started Jul 07 05:36:25 PM PDT 24
Finished Jul 07 05:36:58 PM PDT 24
Peak memory 204976 kb
Host smart-d77915b6-627d-44ce-846d-2c12f41027d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838644964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.1838644964
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.1078313464
Short name T271
Test name
Test status
Simulation time 44603157511 ps
CPU time 110.1 seconds
Started Jul 07 05:36:29 PM PDT 24
Finished Jul 07 05:38:19 PM PDT 24
Peak memory 1591624 kb
Host smart-067b7843-2ceb-496b-93d2-335fd4d6cee8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078313464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.1078313464
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.708762887
Short name T969
Test name
Test status
Simulation time 2371234469 ps
CPU time 115.7 seconds
Started Jul 07 05:36:25 PM PDT 24
Finished Jul 07 05:38:21 PM PDT 24
Peak memory 694428 kb
Host smart-99686d9a-6471-4996-99ce-60511066ca1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708762887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_t
arget_stretch.708762887
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.147703823
Short name T1017
Test name
Test status
Simulation time 2758090305 ps
CPU time 6.79 seconds
Started Jul 07 05:36:26 PM PDT 24
Finished Jul 07 05:36:33 PM PDT 24
Peak memory 210552 kb
Host smart-a03bae20-647e-435a-99f1-85812226af53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147703823 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_timeout.147703823
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.797180839
Short name T267
Test name
Test status
Simulation time 115657906 ps
CPU time 2.8 seconds
Started Jul 07 05:36:33 PM PDT 24
Finished Jul 07 05:36:37 PM PDT 24
Peak memory 205012 kb
Host smart-a8e07f86-63c0-4832-85aa-0a465ba16852
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797180839 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.797180839
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.339865848
Short name T402
Test name
Test status
Simulation time 21774156 ps
CPU time 0.64 seconds
Started Jul 07 05:33:22 PM PDT 24
Finished Jul 07 05:33:23 PM PDT 24
Peak memory 204460 kb
Host smart-6be6fcdb-2fa4-4110-a2b2-22f41638d6db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339865848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.339865848
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.1601443374
Short name T814
Test name
Test status
Simulation time 127613360 ps
CPU time 2.36 seconds
Started Jul 07 05:33:15 PM PDT 24
Finished Jul 07 05:33:17 PM PDT 24
Peak memory 213200 kb
Host smart-a9207866-b173-4da3-b0e6-57032aaa3a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601443374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.1601443374
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.3658290445
Short name T1518
Test name
Test status
Simulation time 300563693 ps
CPU time 5.49 seconds
Started Jul 07 05:33:16 PM PDT 24
Finished Jul 07 05:33:22 PM PDT 24
Peak memory 261164 kb
Host smart-69c24220-debd-4ebe-b91f-a17b4ed01d7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658290445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.3658290445
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.759961169
Short name T46
Test name
Test status
Simulation time 9461082138 ps
CPU time 74.96 seconds
Started Jul 07 05:33:17 PM PDT 24
Finished Jul 07 05:34:32 PM PDT 24
Peak memory 637172 kb
Host smart-c36e4a97-79ab-44e9-a58f-43bbdc970f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759961169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.759961169
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.2371037880
Short name T840
Test name
Test status
Simulation time 1881192559 ps
CPU time 114.24 seconds
Started Jul 07 05:33:23 PM PDT 24
Finished Jul 07 05:35:18 PM PDT 24
Peak memory 459996 kb
Host smart-cc91030e-f977-4563-92fb-f90b2f105e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371037880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.2371037880
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.3328527716
Short name T633
Test name
Test status
Simulation time 103587468 ps
CPU time 1.28 seconds
Started Jul 07 05:33:15 PM PDT 24
Finished Jul 07 05:33:16 PM PDT 24
Peak memory 204952 kb
Host smart-9cd70d45-7b27-488a-8d3c-d99025131c10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328527716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.3328527716
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.3149031928
Short name T160
Test name
Test status
Simulation time 487667315 ps
CPU time 3.7 seconds
Started Jul 07 05:33:09 PM PDT 24
Finished Jul 07 05:33:13 PM PDT 24
Peak memory 224592 kb
Host smart-5bba82ae-85b7-4238-9216-b7683c2c97d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149031928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
3149031928
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.3488316936
Short name T1126
Test name
Test status
Simulation time 3054942606 ps
CPU time 188.94 seconds
Started Jul 07 05:33:14 PM PDT 24
Finished Jul 07 05:36:23 PM PDT 24
Peak memory 941336 kb
Host smart-b62fab2e-944d-4770-ad0b-80458c2a1fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488316936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.3488316936
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.620840514
Short name T1256
Test name
Test status
Simulation time 363001143 ps
CPU time 4.95 seconds
Started Jul 07 05:33:18 PM PDT 24
Finished Jul 07 05:33:23 PM PDT 24
Peak memory 205072 kb
Host smart-a5abad07-3dc1-41f6-b76d-d3bdf43d7660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620840514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.620840514
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_override.3323157084
Short name T138
Test name
Test status
Simulation time 103900317 ps
CPU time 0.71 seconds
Started Jul 07 05:33:12 PM PDT 24
Finished Jul 07 05:33:13 PM PDT 24
Peak memory 204720 kb
Host smart-a1d7bf76-d04f-4136-851d-49d382e5356a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323157084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3323157084
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.2636788341
Short name T850
Test name
Test status
Simulation time 27402949237 ps
CPU time 952.53 seconds
Started Jul 07 05:33:23 PM PDT 24
Finished Jul 07 05:49:16 PM PDT 24
Peak memory 221296 kb
Host smart-fd924ee1-c6ab-484b-86d1-856ea97b39dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636788341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2636788341
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.406264680
Short name T766
Test name
Test status
Simulation time 52291847 ps
CPU time 1.34 seconds
Started Jul 07 05:33:13 PM PDT 24
Finished Jul 07 05:33:15 PM PDT 24
Peak memory 214072 kb
Host smart-76c69dc8-a20c-4140-92af-21de8dbb46a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406264680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.406264680
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.3350763115
Short name T900
Test name
Test status
Simulation time 1577055381 ps
CPU time 29.56 seconds
Started Jul 07 05:33:14 PM PDT 24
Finished Jul 07 05:33:44 PM PDT 24
Peak memory 408012 kb
Host smart-3f45af9f-23e7-442f-9c6d-3a5c5b98a6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350763115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.3350763115
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.175998894
Short name T833
Test name
Test status
Simulation time 102786037314 ps
CPU time 3573.05 seconds
Started Jul 07 05:33:13 PM PDT 24
Finished Jul 07 06:32:47 PM PDT 24
Peak memory 2962396 kb
Host smart-1330a4a9-4e0e-4254-a498-bac95d9774b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175998894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.175998894
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.544682129
Short name T479
Test name
Test status
Simulation time 660256011 ps
CPU time 31.16 seconds
Started Jul 07 05:33:13 PM PDT 24
Finished Jul 07 05:33:45 PM PDT 24
Peak memory 213296 kb
Host smart-1e24fc62-05b7-49fb-ae9b-d0e4721808e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544682129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.544682129
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3713381551
Short name T186
Test name
Test status
Simulation time 99819378 ps
CPU time 0.87 seconds
Started Jul 07 05:33:18 PM PDT 24
Finished Jul 07 05:33:19 PM PDT 24
Peak memory 223096 kb
Host smart-f397f433-0852-43b5-8a33-f7690cb34d6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713381551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3713381551
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.473474658
Short name T1100
Test name
Test status
Simulation time 524477916 ps
CPU time 3.15 seconds
Started Jul 07 05:33:18 PM PDT 24
Finished Jul 07 05:33:22 PM PDT 24
Peak memory 205012 kb
Host smart-9abe49ec-394e-458c-9076-cfc4a5af3460
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473474658 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.473474658
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.1414473340
Short name T1496
Test name
Test status
Simulation time 321158742 ps
CPU time 1.26 seconds
Started Jul 07 05:33:12 PM PDT 24
Finished Jul 07 05:33:14 PM PDT 24
Peak memory 205048 kb
Host smart-56ea575d-7ec9-47fa-b604-107ed9acdd9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414473340 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.1414473340
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.1421305601
Short name T1091
Test name
Test status
Simulation time 204378123 ps
CPU time 1.11 seconds
Started Jul 07 05:33:16 PM PDT 24
Finished Jul 07 05:33:17 PM PDT 24
Peak memory 204956 kb
Host smart-8a70d239-1f19-4873-8712-dc79448c3c38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421305601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.1421305601
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.4177488213
Short name T749
Test name
Test status
Simulation time 482644462 ps
CPU time 2.58 seconds
Started Jul 07 05:33:20 PM PDT 24
Finished Jul 07 05:33:23 PM PDT 24
Peak memory 204968 kb
Host smart-a9b91ebd-8d28-451b-a9fb-5a4176550c03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177488213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.4177488213
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.1006463004
Short name T1321
Test name
Test status
Simulation time 134353067 ps
CPU time 1.13 seconds
Started Jul 07 05:33:18 PM PDT 24
Finished Jul 07 05:33:20 PM PDT 24
Peak memory 204844 kb
Host smart-5498588e-ce3d-4ae5-b3be-18f0b172f435
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006463004 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.1006463004
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.1116098204
Short name T709
Test name
Test status
Simulation time 1300427662 ps
CPU time 2.72 seconds
Started Jul 07 05:33:21 PM PDT 24
Finished Jul 07 05:33:24 PM PDT 24
Peak memory 204932 kb
Host smart-8181144c-6b4a-430d-a129-c796ad0a60ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116098204 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.1116098204
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.752561157
Short name T298
Test name
Test status
Simulation time 4771466039 ps
CPU time 5.7 seconds
Started Jul 07 05:33:17 PM PDT 24
Finished Jul 07 05:33:23 PM PDT 24
Peak memory 210200 kb
Host smart-0401c3c1-1a4f-44fe-a356-431090114864
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752561157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.752561157
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.2265557162
Short name T323
Test name
Test status
Simulation time 10091198114 ps
CPU time 3.76 seconds
Started Jul 07 05:33:15 PM PDT 24
Finished Jul 07 05:33:19 PM PDT 24
Peak memory 250028 kb
Host smart-17edb7d0-4f5e-466c-80ee-13b721942e48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265557162 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.2265557162
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1029716960
Short name T1338
Test name
Test status
Simulation time 4559538828 ps
CPU time 51.27 seconds
Started Jul 07 05:33:14 PM PDT 24
Finished Jul 07 05:34:05 PM PDT 24
Peak memory 205800 kb
Host smart-207fc5ec-562c-492f-a34b-0939f6bc35fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029716960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1029716960
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2549105248
Short name T256
Test name
Test status
Simulation time 67951289752 ps
CPU time 51.61 seconds
Started Jul 07 05:33:14 PM PDT 24
Finished Jul 07 05:34:06 PM PDT 24
Peak memory 795440 kb
Host smart-4ede2f6e-6d9d-4271-83b5-3c8cfa196092
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549105248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2549105248
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.3996174606
Short name T744
Test name
Test status
Simulation time 1271822582 ps
CPU time 7.37 seconds
Started Jul 07 05:33:12 PM PDT 24
Finished Jul 07 05:33:21 PM PDT 24
Peak memory 215060 kb
Host smart-07eeaf9b-ca9d-448f-973f-7ca898f3a5a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996174606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.3996174606
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.4050560405
Short name T1324
Test name
Test status
Simulation time 130971922 ps
CPU time 2.27 seconds
Started Jul 07 05:33:18 PM PDT 24
Finished Jul 07 05:33:21 PM PDT 24
Peak memory 204996 kb
Host smart-cc5b89e0-d367-46d2-8185-3ab50b9e2bf4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050560405 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.4050560405
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2241824241
Short name T1078
Test name
Test status
Simulation time 25643470 ps
CPU time 0.68 seconds
Started Jul 07 05:36:33 PM PDT 24
Finished Jul 07 05:36:34 PM PDT 24
Peak memory 204512 kb
Host smart-51d7d22f-2502-4ed1-ad2c-361c04ac72d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241824241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2241824241
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.1845172009
Short name T1150
Test name
Test status
Simulation time 84511275 ps
CPU time 1.55 seconds
Started Jul 07 05:36:39 PM PDT 24
Finished Jul 07 05:36:41 PM PDT 24
Peak memory 213232 kb
Host smart-e970ebf4-8393-4fa9-93ac-9d349b64b5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845172009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.1845172009
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1050265698
Short name T614
Test name
Test status
Simulation time 1240918343 ps
CPU time 6.62 seconds
Started Jul 07 05:36:32 PM PDT 24
Finished Jul 07 05:36:39 PM PDT 24
Peak memory 264192 kb
Host smart-d99f3e66-4b3f-4ea2-b6c8-27a58a9b194c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050265698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1050265698
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.733408562
Short name T793
Test name
Test status
Simulation time 16728611827 ps
CPU time 208.25 seconds
Started Jul 07 05:36:39 PM PDT 24
Finished Jul 07 05:40:08 PM PDT 24
Peak memory 873300 kb
Host smart-9ad2c545-0c2b-4e63-aa23-a597db2f37f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733408562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.733408562
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.1580620913
Short name T1237
Test name
Test status
Simulation time 8887360425 ps
CPU time 67.19 seconds
Started Jul 07 05:36:32 PM PDT 24
Finished Jul 07 05:37:40 PM PDT 24
Peak memory 762188 kb
Host smart-e2df0075-2d22-4f23-abc1-794d21b76cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580620913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1580620913
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.1957004176
Short name T594
Test name
Test status
Simulation time 641766302 ps
CPU time 1.29 seconds
Started Jul 07 05:36:30 PM PDT 24
Finished Jul 07 05:36:32 PM PDT 24
Peak memory 204724 kb
Host smart-717fe94a-c360-4f38-9e92-28bd6746137f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957004176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.1957004176
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2463080328
Short name T1261
Test name
Test status
Simulation time 606990083 ps
CPU time 3.34 seconds
Started Jul 07 05:36:39 PM PDT 24
Finished Jul 07 05:36:43 PM PDT 24
Peak memory 205068 kb
Host smart-d086d72c-0994-4f07-ad30-229fc40209b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463080328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.2463080328
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.2341382333
Short name T106
Test name
Test status
Simulation time 21086951407 ps
CPU time 126.53 seconds
Started Jul 07 05:36:30 PM PDT 24
Finished Jul 07 05:38:37 PM PDT 24
Peak memory 1367288 kb
Host smart-f24225a9-ed1e-4995-85d0-4d4ef3cac674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341382333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.2341382333
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.3720233081
Short name T586
Test name
Test status
Simulation time 379099736 ps
CPU time 6.11 seconds
Started Jul 07 05:36:35 PM PDT 24
Finished Jul 07 05:36:42 PM PDT 24
Peak memory 205000 kb
Host smart-9dc5f586-fcf1-4e6b-ba81-d8f9da16d1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720233081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.3720233081
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.1411340469
Short name T736
Test name
Test status
Simulation time 9643164946 ps
CPU time 107.64 seconds
Started Jul 07 05:36:35 PM PDT 24
Finished Jul 07 05:38:23 PM PDT 24
Peak memory 350856 kb
Host smart-e1d5de07-4ef3-4b67-86fe-7d2e0dab36bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411340469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.1411340469
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.373119945
Short name T137
Test name
Test status
Simulation time 31543970 ps
CPU time 0.68 seconds
Started Jul 07 05:36:31 PM PDT 24
Finished Jul 07 05:36:32 PM PDT 24
Peak memory 204648 kb
Host smart-5731fe2d-3663-46ca-91dd-fcf6d150da5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373119945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.373119945
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3529550204
Short name T1353
Test name
Test status
Simulation time 6259523855 ps
CPU time 81.44 seconds
Started Jul 07 05:36:29 PM PDT 24
Finished Jul 07 05:37:51 PM PDT 24
Peak memory 856004 kb
Host smart-35bf7fe0-16da-4157-a444-4c1fa6c820c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529550204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3529550204
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.1889827158
Short name T1083
Test name
Test status
Simulation time 267337682 ps
CPU time 3.37 seconds
Started Jul 07 05:36:33 PM PDT 24
Finished Jul 07 05:36:37 PM PDT 24
Peak memory 204908 kb
Host smart-4dcaf270-841e-4b52-ad38-d557412b83b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889827158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.1889827158
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2500334614
Short name T836
Test name
Test status
Simulation time 2562017572 ps
CPU time 26.29 seconds
Started Jul 07 05:36:30 PM PDT 24
Finished Jul 07 05:36:57 PM PDT 24
Peak memory 328572 kb
Host smart-c17e258e-8ecb-461f-add6-2c86abef578b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500334614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2500334614
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.3902315104
Short name T944
Test name
Test status
Simulation time 10502015837 ps
CPU time 1014.57 seconds
Started Jul 07 05:36:35 PM PDT 24
Finished Jul 07 05:53:31 PM PDT 24
Peak memory 2209224 kb
Host smart-df67bb30-be41-476e-9204-689c3c80a89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902315104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.3902315104
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.4170954892
Short name T473
Test name
Test status
Simulation time 654086291 ps
CPU time 12.11 seconds
Started Jul 07 05:36:34 PM PDT 24
Finished Jul 07 05:36:46 PM PDT 24
Peak memory 216700 kb
Host smart-9edb8e5c-9e79-4f1f-8234-ff5722138c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170954892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.4170954892
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.2225207013
Short name T1025
Test name
Test status
Simulation time 3395745071 ps
CPU time 4.18 seconds
Started Jul 07 05:36:36 PM PDT 24
Finished Jul 07 05:36:40 PM PDT 24
Peak memory 213268 kb
Host smart-8550bf6e-8419-481f-82c0-7af891ea4ee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225207013 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2225207013
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2843305880
Short name T80
Test name
Test status
Simulation time 555916196 ps
CPU time 1.1 seconds
Started Jul 07 05:36:34 PM PDT 24
Finished Jul 07 05:36:36 PM PDT 24
Peak memory 204804 kb
Host smart-bbd6d6ad-81d3-4fa0-9aec-0f78b4ffac44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843305880 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2843305880
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.323183533
Short name T1419
Test name
Test status
Simulation time 179260893 ps
CPU time 1.31 seconds
Started Jul 07 05:36:33 PM PDT 24
Finished Jul 07 05:36:35 PM PDT 24
Peak memory 204924 kb
Host smart-c7e43783-971e-4de8-b1b1-a3fd1b302fb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323183533 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_tx.323183533
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.2491497028
Short name T1024
Test name
Test status
Simulation time 564236296 ps
CPU time 1.71 seconds
Started Jul 07 05:36:38 PM PDT 24
Finished Jul 07 05:36:41 PM PDT 24
Peak memory 204728 kb
Host smart-23348505-4c12-4ea8-b3b0-288980f3a651
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491497028 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.2491497028
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.3350478150
Short name T501
Test name
Test status
Simulation time 196227486 ps
CPU time 1.16 seconds
Started Jul 07 05:36:36 PM PDT 24
Finished Jul 07 05:36:38 PM PDT 24
Peak memory 204800 kb
Host smart-4f894536-374c-4f3a-81d6-2ba1f8388ea8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350478150 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.3350478150
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.632604694
Short name T1081
Test name
Test status
Simulation time 417305270 ps
CPU time 3.77 seconds
Started Jul 07 05:36:36 PM PDT 24
Finished Jul 07 05:36:41 PM PDT 24
Peak memory 205056 kb
Host smart-41f13c2b-1272-4c29-9fa6-0f698e627871
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632604694 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_hrst.632604694
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.221047568
Short name T678
Test name
Test status
Simulation time 1595040285 ps
CPU time 4.55 seconds
Started Jul 07 05:36:34 PM PDT 24
Finished Jul 07 05:36:39 PM PDT 24
Peak memory 205016 kb
Host smart-d41cdfb3-7b7d-469b-a7e2-d53434f790f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221047568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_intr_smoke.221047568
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.816953664
Short name T213
Test name
Test status
Simulation time 20371558791 ps
CPU time 5.56 seconds
Started Jul 07 05:36:40 PM PDT 24
Finished Jul 07 05:36:46 PM PDT 24
Peak memory 205096 kb
Host smart-128e9484-87d2-437c-a954-cadc38e3bddd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816953664 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.816953664
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.1213565767
Short name T429
Test name
Test status
Simulation time 1019266189 ps
CPU time 7.84 seconds
Started Jul 07 05:36:33 PM PDT 24
Finished Jul 07 05:36:42 PM PDT 24
Peak memory 204952 kb
Host smart-16752422-bf76-40c1-aa62-8b0eb47bc347
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213565767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.1213565767
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.477707631
Short name T1018
Test name
Test status
Simulation time 1152143933 ps
CPU time 48.89 seconds
Started Jul 07 05:36:36 PM PDT 24
Finished Jul 07 05:37:25 PM PDT 24
Peak memory 205152 kb
Host smart-ae6556c6-6817-4674-8656-76d4968197ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477707631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_rd.477707631
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.650086489
Short name T972
Test name
Test status
Simulation time 44914519107 ps
CPU time 847.74 seconds
Started Jul 07 05:36:32 PM PDT 24
Finished Jul 07 05:50:40 PM PDT 24
Peak memory 6512428 kb
Host smart-cebdb39a-c0f5-46c7-bfda-30c01179fcff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650086489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_wr.650086489
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.2491145468
Short name T1371
Test name
Test status
Simulation time 3205350242 ps
CPU time 169.54 seconds
Started Jul 07 05:36:32 PM PDT 24
Finished Jul 07 05:39:22 PM PDT 24
Peak memory 931552 kb
Host smart-7ae159aa-c3cd-417c-b921-631f6bc025fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491145468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.2491145468
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1488538524
Short name T1235
Test name
Test status
Simulation time 1279808560 ps
CPU time 6.96 seconds
Started Jul 07 05:36:38 PM PDT 24
Finished Jul 07 05:36:46 PM PDT 24
Peak memory 205028 kb
Host smart-d740f3cf-4a5d-4bc1-8384-ad44ad1b29f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488538524 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1488538524
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.1380244202
Short name T669
Test name
Test status
Simulation time 246001895 ps
CPU time 3.22 seconds
Started Jul 07 05:36:33 PM PDT 24
Finished Jul 07 05:36:36 PM PDT 24
Peak memory 204972 kb
Host smart-383b71d0-33e0-48b0-bd82-22a05f05d40f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380244202 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.1380244202
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.691563889
Short name T397
Test name
Test status
Simulation time 30456451 ps
CPU time 0.62 seconds
Started Jul 07 05:36:50 PM PDT 24
Finished Jul 07 05:36:51 PM PDT 24
Peak memory 204564 kb
Host smart-e157866e-ae21-4799-a3e6-9e43a90fc87d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691563889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.691563889
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3690727399
Short name T600
Test name
Test status
Simulation time 573271223 ps
CPU time 2.34 seconds
Started Jul 07 05:36:40 PM PDT 24
Finished Jul 07 05:36:43 PM PDT 24
Peak memory 213316 kb
Host smart-5ce0420c-36e9-48f2-9e62-bac47688110b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690727399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3690727399
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1171800054
Short name T1477
Test name
Test status
Simulation time 823742978 ps
CPU time 10.86 seconds
Started Jul 07 05:36:37 PM PDT 24
Finished Jul 07 05:36:49 PM PDT 24
Peak memory 247292 kb
Host smart-7ae328ad-fa58-4e96-bd05-62fad824680d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171800054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.1171800054
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2259932334
Short name T613
Test name
Test status
Simulation time 1415900724 ps
CPU time 90.76 seconds
Started Jul 07 05:36:39 PM PDT 24
Finished Jul 07 05:38:11 PM PDT 24
Peak memory 543528 kb
Host smart-7e12aab5-da15-4ac0-a490-9545e729f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259932334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2259932334
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1501110468
Short name T1437
Test name
Test status
Simulation time 10967300894 ps
CPU time 80.78 seconds
Started Jul 07 05:36:43 PM PDT 24
Finished Jul 07 05:38:05 PM PDT 24
Peak memory 779976 kb
Host smart-a5d9d94b-ec69-4581-9ef4-5ea63d9e6fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501110468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1501110468
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.265015576
Short name T880
Test name
Test status
Simulation time 360223697 ps
CPU time 1.16 seconds
Started Jul 07 05:36:37 PM PDT 24
Finished Jul 07 05:36:38 PM PDT 24
Peak memory 204916 kb
Host smart-2b9d4a7e-dade-4486-9b4a-7b24b04a9b6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265015576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fm
t.265015576
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.3256328617
Short name T908
Test name
Test status
Simulation time 695048171 ps
CPU time 10.82 seconds
Started Jul 07 05:36:36 PM PDT 24
Finished Jul 07 05:36:48 PM PDT 24
Peak memory 239148 kb
Host smart-224499d8-a5af-4c82-b589-bc8b1413330b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256328617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.3256328617
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1019922559
Short name T916
Test name
Test status
Simulation time 7743225584 ps
CPU time 107.15 seconds
Started Jul 07 05:36:39 PM PDT 24
Finished Jul 07 05:38:27 PM PDT 24
Peak memory 1103844 kb
Host smart-8f929955-f469-453e-b204-403b8fd691dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019922559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1019922559
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.3954828429
Short name T1482
Test name
Test status
Simulation time 400113032 ps
CPU time 4.56 seconds
Started Jul 07 05:36:47 PM PDT 24
Finished Jul 07 05:36:52 PM PDT 24
Peak memory 204984 kb
Host smart-bc9c35c9-8934-4b8f-8a56-c8823e6f4186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954828429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3954828429
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1247704898
Short name T684
Test name
Test status
Simulation time 35145603918 ps
CPU time 40.6 seconds
Started Jul 07 05:36:49 PM PDT 24
Finished Jul 07 05:37:30 PM PDT 24
Peak memory 415824 kb
Host smart-b049601a-e70f-4774-aea7-831a841870a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247704898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1247704898
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.4134535618
Short name T955
Test name
Test status
Simulation time 95404103 ps
CPU time 0.76 seconds
Started Jul 07 05:36:37 PM PDT 24
Finished Jul 07 05:36:39 PM PDT 24
Peak memory 204700 kb
Host smart-f29c5695-613a-47ec-aad1-ea019b17ef90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134535618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.4134535618
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.630842053
Short name T1227
Test name
Test status
Simulation time 7338754833 ps
CPU time 32.37 seconds
Started Jul 07 05:36:41 PM PDT 24
Finished Jul 07 05:37:13 PM PDT 24
Peak memory 488736 kb
Host smart-42d66a40-ea02-4b08-85ac-7459e0b3c495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630842053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.630842053
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.2466517224
Short name T113
Test name
Test status
Simulation time 489493776 ps
CPU time 7.59 seconds
Started Jul 07 05:36:38 PM PDT 24
Finished Jul 07 05:36:46 PM PDT 24
Peak memory 204968 kb
Host smart-8b8ddc44-bb14-4d26-b669-10ef579fb212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466517224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.2466517224
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.4161461160
Short name T877
Test name
Test status
Simulation time 1755961499 ps
CPU time 30.92 seconds
Started Jul 07 05:36:34 PM PDT 24
Finished Jul 07 05:37:05 PM PDT 24
Peak memory 345272 kb
Host smart-e4433e91-1044-4f81-b6ef-17594784f656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161461160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.4161461160
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.2268643886
Short name T1145
Test name
Test status
Simulation time 50712285076 ps
CPU time 729.57 seconds
Started Jul 07 05:36:43 PM PDT 24
Finished Jul 07 05:48:53 PM PDT 24
Peak memory 2923268 kb
Host smart-eaa5ba61-8564-4e75-99fe-1d63eb431e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268643886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.2268643886
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.2069684188
Short name T1325
Test name
Test status
Simulation time 3743993379 ps
CPU time 17.4 seconds
Started Jul 07 05:36:38 PM PDT 24
Finished Jul 07 05:36:56 PM PDT 24
Peak memory 219316 kb
Host smart-c4e58262-036e-44ee-8afd-80656aaf23a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069684188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.2069684188
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.793655306
Short name T1345
Test name
Test status
Simulation time 10626694043 ps
CPU time 3.57 seconds
Started Jul 07 05:36:47 PM PDT 24
Finished Jul 07 05:36:51 PM PDT 24
Peak memory 205060 kb
Host smart-492b7e45-43a8-4c22-9aab-8fc9086e4f02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793655306 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.793655306
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.1370817696
Short name T924
Test name
Test status
Simulation time 239032592 ps
CPU time 1.54 seconds
Started Jul 07 05:36:51 PM PDT 24
Finished Jul 07 05:36:53 PM PDT 24
Peak memory 204984 kb
Host smart-be8cd794-4605-4c4f-a059-79b324a20727
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370817696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.1370817696
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.3603273899
Short name T1054
Test name
Test status
Simulation time 216268097 ps
CPU time 1.22 seconds
Started Jul 07 05:36:51 PM PDT 24
Finished Jul 07 05:36:53 PM PDT 24
Peak memory 204796 kb
Host smart-1d4646ab-d367-4859-a56d-7a5a0b684ed3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603273899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.3603273899
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.2508469423
Short name T258
Test name
Test status
Simulation time 1900961409 ps
CPU time 2.32 seconds
Started Jul 07 05:36:48 PM PDT 24
Finished Jul 07 05:36:51 PM PDT 24
Peak memory 204924 kb
Host smart-8d941de1-af91-4b80-b25f-674fd41a75b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508469423 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.2508469423
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.2067539249
Short name T1457
Test name
Test status
Simulation time 1322124105 ps
CPU time 1.07 seconds
Started Jul 07 05:36:41 PM PDT 24
Finished Jul 07 05:36:42 PM PDT 24
Peak memory 204804 kb
Host smart-7f55fce3-eeaf-40cb-a1ed-81e3dd629fef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067539249 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.2067539249
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.885595759
Short name T1020
Test name
Test status
Simulation time 382746223 ps
CPU time 4.93 seconds
Started Jul 07 05:36:48 PM PDT 24
Finished Jul 07 05:36:54 PM PDT 24
Peak memory 205060 kb
Host smart-0f8d385b-fe4d-45cb-887e-35024038a81a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885595759 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.i2c_target_hrst.885595759
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.2535899556
Short name T1452
Test name
Test status
Simulation time 1589330047 ps
CPU time 7.7 seconds
Started Jul 07 05:36:46 PM PDT 24
Finished Jul 07 05:36:54 PM PDT 24
Peak memory 216724 kb
Host smart-1e764e29-538d-403e-b34b-4339457b797a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535899556 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.2535899556
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.2419169646
Short name T565
Test name
Test status
Simulation time 21049599899 ps
CPU time 412.93 seconds
Started Jul 07 05:36:40 PM PDT 24
Finished Jul 07 05:43:33 PM PDT 24
Peak memory 4935956 kb
Host smart-fcdde526-bebd-4059-ad13-8ac10f3ab886
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419169646 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.2419169646
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.3091449073
Short name T1167
Test name
Test status
Simulation time 1908544717 ps
CPU time 37.57 seconds
Started Jul 07 05:36:39 PM PDT 24
Finished Jul 07 05:37:17 PM PDT 24
Peak memory 204948 kb
Host smart-ba72aace-71ff-450f-9666-c115e8eba0d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091449073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.3091449073
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3239850728
Short name T1520
Test name
Test status
Simulation time 1154841288 ps
CPU time 27.59 seconds
Started Jul 07 05:36:39 PM PDT 24
Finished Jul 07 05:37:07 PM PDT 24
Peak memory 205000 kb
Host smart-3777c63f-de84-4397-bb67-14eb483c419f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239850728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3239850728
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.3363195088
Short name T129
Test name
Test status
Simulation time 14289692414 ps
CPU time 13.31 seconds
Started Jul 07 05:36:37 PM PDT 24
Finished Jul 07 05:36:51 PM PDT 24
Peak memory 205064 kb
Host smart-f1af17fd-b562-4db9-b058-42fda259dc2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363195088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.3363195088
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.345258308
Short name T729
Test name
Test status
Simulation time 2000766644 ps
CPU time 29.84 seconds
Started Jul 07 05:36:38 PM PDT 24
Finished Jul 07 05:37:09 PM PDT 24
Peak memory 633200 kb
Host smart-b883f43c-6e54-45c2-925e-25f1cc1fdc8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345258308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_t
arget_stretch.345258308
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.3932011217
Short name T1298
Test name
Test status
Simulation time 5460232044 ps
CPU time 7.61 seconds
Started Jul 07 05:36:44 PM PDT 24
Finished Jul 07 05:36:52 PM PDT 24
Peak memory 219088 kb
Host smart-558d4e16-fa2a-44ee-a4b7-0f3bcf9dfb00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932011217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.3932011217
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.2083524529
Short name T670
Test name
Test status
Simulation time 99368459 ps
CPU time 2.29 seconds
Started Jul 07 05:36:48 PM PDT 24
Finished Jul 07 05:36:51 PM PDT 24
Peak memory 204984 kb
Host smart-dc85f5fa-a5b8-4014-b26d-a1ac41bc01a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083524529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.2083524529
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.216317578
Short name T300
Test name
Test status
Simulation time 65189064 ps
CPU time 0.62 seconds
Started Jul 07 05:36:50 PM PDT 24
Finished Jul 07 05:36:51 PM PDT 24
Peak memory 204556 kb
Host smart-2a5b4c1e-df03-48da-8b1f-9dd0547a8a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216317578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.216317578
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2390374402
Short name T750
Test name
Test status
Simulation time 144726236 ps
CPU time 4.38 seconds
Started Jul 07 05:36:48 PM PDT 24
Finished Jul 07 05:36:53 PM PDT 24
Peak memory 221460 kb
Host smart-d3bb7e11-a5c4-4e3a-9ea4-4cf86a08c02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390374402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2390374402
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.1593698200
Short name T1340
Test name
Test status
Simulation time 360218775 ps
CPU time 8.3 seconds
Started Jul 07 05:36:52 PM PDT 24
Finished Jul 07 05:37:01 PM PDT 24
Peak memory 276496 kb
Host smart-60174441-99cb-4cdc-b99e-0abbcc4360d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593698200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.1593698200
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.2942103794
Short name T1287
Test name
Test status
Simulation time 2933866365 ps
CPU time 110.35 seconds
Started Jul 07 05:36:48 PM PDT 24
Finished Jul 07 05:38:39 PM PDT 24
Peak memory 900080 kb
Host smart-8c7cb192-1dd6-4748-bdda-50eb345e1869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942103794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.2942103794
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.2931372828
Short name T1258
Test name
Test status
Simulation time 9076725862 ps
CPU time 154.58 seconds
Started Jul 07 05:36:52 PM PDT 24
Finished Jul 07 05:39:27 PM PDT 24
Peak memory 648548 kb
Host smart-6a9f915a-17b7-4f53-b631-d95201c0ea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931372828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2931372828
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.3851548606
Short name T377
Test name
Test status
Simulation time 93283933 ps
CPU time 1.09 seconds
Started Jul 07 05:36:48 PM PDT 24
Finished Jul 07 05:36:50 PM PDT 24
Peak memory 204760 kb
Host smart-7410ae33-8ace-416a-b04f-dc65f861066c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851548606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.3851548606
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.2567290176
Short name T710
Test name
Test status
Simulation time 501158483 ps
CPU time 3.38 seconds
Started Jul 07 05:36:52 PM PDT 24
Finished Jul 07 05:36:56 PM PDT 24
Peak memory 224652 kb
Host smart-dc07b434-0069-4ed5-8962-52b0c081eb2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567290176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.2567290176
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.2887927908
Short name T936
Test name
Test status
Simulation time 3065243408 ps
CPU time 81.63 seconds
Started Jul 07 05:36:47 PM PDT 24
Finished Jul 07 05:38:08 PM PDT 24
Peak memory 944088 kb
Host smart-00dae41b-6e78-4c68-bf14-854bf4da31f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887927908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.2887927908
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.1249909170
Short name T424
Test name
Test status
Simulation time 303358834 ps
CPU time 4.14 seconds
Started Jul 07 05:36:50 PM PDT 24
Finished Jul 07 05:36:54 PM PDT 24
Peak memory 205064 kb
Host smart-a8d40092-9c07-48f9-a2cf-ded37773614f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249909170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.1249909170
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.1336229476
Short name T339
Test name
Test status
Simulation time 1408678726 ps
CPU time 26.89 seconds
Started Jul 07 05:36:48 PM PDT 24
Finished Jul 07 05:37:16 PM PDT 24
Peak memory 354952 kb
Host smart-67cf182f-bb00-4762-a94c-c84b6180d45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336229476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.1336229476
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.49443711
Short name T787
Test name
Test status
Simulation time 19337345 ps
CPU time 0.67 seconds
Started Jul 07 05:36:49 PM PDT 24
Finished Jul 07 05:36:50 PM PDT 24
Peak memory 204680 kb
Host smart-a7c7b322-33b1-4a49-a236-1b3a3a7cc067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49443711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.49443711
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.3556324285
Short name T578
Test name
Test status
Simulation time 384459279 ps
CPU time 1.89 seconds
Started Jul 07 05:36:48 PM PDT 24
Finished Jul 07 05:36:51 PM PDT 24
Peak memory 213352 kb
Host smart-b364a3e0-19e9-4b64-a4f5-ab9963c1e57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556324285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3556324285
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.641234133
Short name T1140
Test name
Test status
Simulation time 265807718 ps
CPU time 1.78 seconds
Started Jul 07 05:36:43 PM PDT 24
Finished Jul 07 05:36:46 PM PDT 24
Peak memory 217816 kb
Host smart-97e83152-d474-4293-8d77-632a7d0b5297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641234133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.641234133
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.630482594
Short name T506
Test name
Test status
Simulation time 4738573496 ps
CPU time 22.72 seconds
Started Jul 07 05:36:46 PM PDT 24
Finished Jul 07 05:37:09 PM PDT 24
Peak memory 334544 kb
Host smart-5e9e7601-4613-478b-9f94-946918b00bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630482594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.630482594
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.3067443239
Short name T275
Test name
Test status
Simulation time 12405980427 ps
CPU time 1392.03 seconds
Started Jul 07 05:36:48 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 2699852 kb
Host smart-7c1293b4-c37d-43d4-b42e-e1b0b60c19a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067443239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.3067443239
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.734784509
Short name T404
Test name
Test status
Simulation time 3138783755 ps
CPU time 12.01 seconds
Started Jul 07 05:36:51 PM PDT 24
Finished Jul 07 05:37:03 PM PDT 24
Peak memory 229572 kb
Host smart-bd79976c-be50-4315-ae0f-e2e39c225f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734784509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.734784509
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.2228094442
Short name T1119
Test name
Test status
Simulation time 1444935017 ps
CPU time 4.09 seconds
Started Jul 07 05:36:55 PM PDT 24
Finished Jul 07 05:37:00 PM PDT 24
Peak memory 212872 kb
Host smart-a3a9e494-c980-43e4-b8ba-7ea8ad3f4892
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228094442 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2228094442
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1939147499
Short name T295
Test name
Test status
Simulation time 283809426 ps
CPU time 1.22 seconds
Started Jul 07 05:36:51 PM PDT 24
Finished Jul 07 05:36:53 PM PDT 24
Peak memory 204996 kb
Host smart-9a3599f1-cf86-41a3-8470-7c89f1032272
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939147499 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1939147499
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.3145899347
Short name T1462
Test name
Test status
Simulation time 160507992 ps
CPU time 1.08 seconds
Started Jul 07 05:36:50 PM PDT 24
Finished Jul 07 05:36:51 PM PDT 24
Peak memory 205024 kb
Host smart-a3383131-ca63-4427-b5f9-d11bc22f06ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145899347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.3145899347
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.4155009216
Short name T398
Test name
Test status
Simulation time 653944838 ps
CPU time 3.27 seconds
Started Jul 07 05:36:51 PM PDT 24
Finished Jul 07 05:36:55 PM PDT 24
Peak memory 205056 kb
Host smart-a13dbb02-6491-41df-83a0-18d81c471ead
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155009216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.4155009216
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.1194383761
Short name T321
Test name
Test status
Simulation time 150049027 ps
CPU time 1.02 seconds
Started Jul 07 05:36:47 PM PDT 24
Finished Jul 07 05:36:49 PM PDT 24
Peak memory 204728 kb
Host smart-a96b3f27-dff9-43c5-bedc-95cf73d7fc57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194383761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.1194383761
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1244974649
Short name T273
Test name
Test status
Simulation time 1544944769 ps
CPU time 3.06 seconds
Started Jul 07 05:36:55 PM PDT 24
Finished Jul 07 05:36:59 PM PDT 24
Peak memory 204768 kb
Host smart-47cd1d8d-6144-429c-9c59-53c0f5404aa8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244974649 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1244974649
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.4124929093
Short name T1105
Test name
Test status
Simulation time 1322818743 ps
CPU time 6.26 seconds
Started Jul 07 05:36:48 PM PDT 24
Finished Jul 07 05:36:54 PM PDT 24
Peak memory 213228 kb
Host smart-6584a9c3-163c-415a-acb4-f18ae840cb1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124929093 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.4124929093
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1817716351
Short name T1390
Test name
Test status
Simulation time 14602796805 ps
CPU time 13.37 seconds
Started Jul 07 05:36:51 PM PDT 24
Finished Jul 07 05:37:05 PM PDT 24
Peak memory 495072 kb
Host smart-55f23a8a-2dcf-42fc-831c-1ea06fe52c18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817716351 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1817716351
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.1962437555
Short name T173
Test name
Test status
Simulation time 2476935876 ps
CPU time 21.33 seconds
Started Jul 07 05:36:48 PM PDT 24
Finished Jul 07 05:37:09 PM PDT 24
Peak memory 204972 kb
Host smart-84cbd5ea-085c-4edc-ac1c-95adeab827d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962437555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.1962437555
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2437059946
Short name T753
Test name
Test status
Simulation time 1335994536 ps
CPU time 61.44 seconds
Started Jul 07 05:36:49 PM PDT 24
Finished Jul 07 05:37:51 PM PDT 24
Peak memory 205836 kb
Host smart-7ebbbfa9-edad-4811-84dc-9d9ec23508c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437059946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2437059946
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.24029202
Short name T566
Test name
Test status
Simulation time 8011925656 ps
CPU time 4.76 seconds
Started Jul 07 05:36:49 PM PDT 24
Finished Jul 07 05:36:54 PM PDT 24
Peak memory 205052 kb
Host smart-5d3b4293-2852-4ec5-8000-70759022f633
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24029202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stress_wr.24029202
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1507018836
Short name T1082
Test name
Test status
Simulation time 1231815149 ps
CPU time 9.49 seconds
Started Jul 07 05:36:41 PM PDT 24
Finished Jul 07 05:36:51 PM PDT 24
Peak memory 310084 kb
Host smart-9475c90c-8667-4feb-8124-0bd07c1fdc0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507018836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1507018836
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1636322048
Short name T883
Test name
Test status
Simulation time 1332885781 ps
CPU time 6.68 seconds
Started Jul 07 05:36:47 PM PDT 24
Finished Jul 07 05:36:54 PM PDT 24
Peak memory 215480 kb
Host smart-c14386d6-1869-4338-beb5-8d1d30490e9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636322048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1636322048
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.1305303250
Short name T434
Test name
Test status
Simulation time 1763651280 ps
CPU time 20.46 seconds
Started Jul 07 05:36:47 PM PDT 24
Finished Jul 07 05:37:07 PM PDT 24
Peak memory 213740 kb
Host smart-28abc1cb-8e31-455c-8d9f-1ddab299a726
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305303250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.1305303250
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.643637143
Short name T1271
Test name
Test status
Simulation time 55813392 ps
CPU time 0.66 seconds
Started Jul 07 05:36:58 PM PDT 24
Finished Jul 07 05:36:59 PM PDT 24
Peak memory 204600 kb
Host smart-904b7f10-b993-42f6-97e2-1d1d931e7cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643637143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.643637143
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.3417523045
Short name T53
Test name
Test status
Simulation time 136776801 ps
CPU time 2.85 seconds
Started Jul 07 05:36:52 PM PDT 24
Finished Jul 07 05:36:56 PM PDT 24
Peak memory 214308 kb
Host smart-93d1aa78-762c-4a31-8729-fb98f5d6e6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417523045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.3417523045
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2141722561
Short name T625
Test name
Test status
Simulation time 1163306988 ps
CPU time 7.58 seconds
Started Jul 07 05:36:54 PM PDT 24
Finished Jul 07 05:37:02 PM PDT 24
Peak memory 280928 kb
Host smart-e410c042-d1b0-427c-8066-38f9088c2cf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141722561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2141722561
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.2675350152
Short name T703
Test name
Test status
Simulation time 3856194171 ps
CPU time 72.11 seconds
Started Jul 07 05:36:49 PM PDT 24
Finished Jul 07 05:38:01 PM PDT 24
Peak memory 648112 kb
Host smart-520b87a9-5067-489c-a2ee-b66c2ea9f88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675350152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2675350152
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.3563168413
Short name T1269
Test name
Test status
Simulation time 4486020497 ps
CPU time 145.93 seconds
Started Jul 07 05:36:50 PM PDT 24
Finished Jul 07 05:39:16 PM PDT 24
Peak memory 614548 kb
Host smart-0ec4d021-0f37-4f1e-a917-5b51e5476306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563168413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.3563168413
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.2884150963
Short name T716
Test name
Test status
Simulation time 442541148 ps
CPU time 1 seconds
Started Jul 07 05:36:51 PM PDT 24
Finished Jul 07 05:36:52 PM PDT 24
Peak memory 204724 kb
Host smart-f2fd890a-9324-4d40-9558-cc5dca9677db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884150963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.2884150963
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.1150839575
Short name T604
Test name
Test status
Simulation time 1967950600 ps
CPU time 5.4 seconds
Started Jul 07 05:37:00 PM PDT 24
Finished Jul 07 05:37:06 PM PDT 24
Peak memory 247420 kb
Host smart-131e5279-e5d0-4b4f-892d-544e9f14ae8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150839575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.1150839575
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1359707102
Short name T102
Test name
Test status
Simulation time 4960181475 ps
CPU time 126.23 seconds
Started Jul 07 05:36:53 PM PDT 24
Finished Jul 07 05:39:00 PM PDT 24
Peak memory 1384060 kb
Host smart-037cbe49-1778-4340-a286-0aa4c53247be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359707102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1359707102
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.3971607653
Short name T45
Test name
Test status
Simulation time 726848946 ps
CPU time 7.75 seconds
Started Jul 07 05:36:54 PM PDT 24
Finished Jul 07 05:37:02 PM PDT 24
Peak memory 204980 kb
Host smart-0b01fb4e-33df-4787-b6b8-e8a526fcaf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971607653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.3971607653
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.2183681062
Short name T874
Test name
Test status
Simulation time 9130298239 ps
CPU time 38.17 seconds
Started Jul 07 05:36:59 PM PDT 24
Finished Jul 07 05:37:38 PM PDT 24
Peak memory 413208 kb
Host smart-b743cb3c-2b6c-4943-86ee-63d922737543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183681062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.2183681062
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.1706659339
Short name T1026
Test name
Test status
Simulation time 27551844 ps
CPU time 0.75 seconds
Started Jul 07 05:36:48 PM PDT 24
Finished Jul 07 05:36:49 PM PDT 24
Peak memory 205024 kb
Host smart-2b4371e1-0394-470c-895a-744f53b3255c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706659339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1706659339
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.710301015
Short name T1016
Test name
Test status
Simulation time 6497188468 ps
CPU time 25.31 seconds
Started Jul 07 05:36:50 PM PDT 24
Finished Jul 07 05:37:16 PM PDT 24
Peak memory 214796 kb
Host smart-920b3180-11eb-45aa-a884-3b076bd5d20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710301015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.710301015
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.2346591276
Short name T1057
Test name
Test status
Simulation time 484640617 ps
CPU time 1.97 seconds
Started Jul 07 05:36:50 PM PDT 24
Finished Jul 07 05:36:53 PM PDT 24
Peak memory 205024 kb
Host smart-a980b734-99c9-493f-8118-33e748d7fa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346591276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.2346591276
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2192795167
Short name T8
Test name
Test status
Simulation time 1459081613 ps
CPU time 29.42 seconds
Started Jul 07 05:36:51 PM PDT 24
Finished Jul 07 05:37:21 PM PDT 24
Peak memory 356416 kb
Host smart-ae8f8e5e-5252-4853-bfc6-e378dc13d594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192795167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2192795167
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.868572569
Short name T1527
Test name
Test status
Simulation time 18248594249 ps
CPU time 247.46 seconds
Started Jul 07 05:36:49 PM PDT 24
Finished Jul 07 05:40:56 PM PDT 24
Peak memory 672728 kb
Host smart-2e40ffea-5692-450c-9b0a-85a733fac1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868572569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.868572569
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.4188657489
Short name T947
Test name
Test status
Simulation time 1496904998 ps
CPU time 30.55 seconds
Started Jul 07 05:36:53 PM PDT 24
Finished Jul 07 05:37:24 PM PDT 24
Peak memory 213256 kb
Host smart-4d30bc58-4aef-4185-aa9e-75d17fa48016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188657489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.4188657489
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.3472623128
Short name T1185
Test name
Test status
Simulation time 861510030 ps
CPU time 4.26 seconds
Started Jul 07 05:36:51 PM PDT 24
Finished Jul 07 05:36:56 PM PDT 24
Peak memory 213276 kb
Host smart-82a778ec-bcd7-40c4-8dd3-ad0e9c6cad12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472623128 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.3472623128
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.4194986781
Short name T951
Test name
Test status
Simulation time 633339876 ps
CPU time 1.37 seconds
Started Jul 07 05:36:59 PM PDT 24
Finished Jul 07 05:37:01 PM PDT 24
Peak memory 205000 kb
Host smart-b08c4add-dbf1-4294-9135-e41d24d79e10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194986781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.4194986781
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.1257865278
Short name T802
Test name
Test status
Simulation time 226545763 ps
CPU time 0.9 seconds
Started Jul 07 05:36:53 PM PDT 24
Finished Jul 07 05:36:55 PM PDT 24
Peak memory 213004 kb
Host smart-f6eb1e8f-1ee7-499b-bb62-3c54311f9eca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257865278 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.1257865278
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.2678314212
Short name T1318
Test name
Test status
Simulation time 430563680 ps
CPU time 2.49 seconds
Started Jul 07 05:36:55 PM PDT 24
Finished Jul 07 05:36:58 PM PDT 24
Peak memory 204940 kb
Host smart-89f28a79-9961-414d-a7fd-369739e29bf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678314212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.2678314212
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.2747680268
Short name T664
Test name
Test status
Simulation time 127097541 ps
CPU time 0.88 seconds
Started Jul 07 05:37:00 PM PDT 24
Finished Jul 07 05:37:01 PM PDT 24
Peak memory 204804 kb
Host smart-331fa457-ec12-4062-a8d3-cd2d777198f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747680268 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.2747680268
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.3091316954
Short name T1084
Test name
Test status
Simulation time 2226341031 ps
CPU time 2.53 seconds
Started Jul 07 05:37:00 PM PDT 24
Finished Jul 07 05:37:03 PM PDT 24
Peak memory 205084 kb
Host smart-5529c939-0c97-4d45-a6b0-d508cf5c3f65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091316954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.3091316954
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3457147384
Short name T1526
Test name
Test status
Simulation time 1947016493 ps
CPU time 5.7 seconds
Started Jul 07 05:36:52 PM PDT 24
Finished Jul 07 05:36:59 PM PDT 24
Peak memory 210264 kb
Host smart-1f2377e6-72af-48ac-81d3-a633c483d863
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457147384 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3457147384
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.1353606152
Short name T1529
Test name
Test status
Simulation time 6043041093 ps
CPU time 13.03 seconds
Started Jul 07 05:36:51 PM PDT 24
Finished Jul 07 05:37:04 PM PDT 24
Peak memory 205076 kb
Host smart-a7d0dc25-5a69-4527-abe0-055347b468e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353606152 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.1353606152
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.1590058478
Short name T27
Test name
Test status
Simulation time 1203220523 ps
CPU time 13.03 seconds
Started Jul 07 05:36:59 PM PDT 24
Finished Jul 07 05:37:13 PM PDT 24
Peak memory 205000 kb
Host smart-762d73c9-8160-47f6-b274-c058f70c9487
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590058478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.1590058478
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2768997893
Short name T359
Test name
Test status
Simulation time 1856568570 ps
CPU time 40.1 seconds
Started Jul 07 05:36:50 PM PDT 24
Finished Jul 07 05:37:31 PM PDT 24
Peak memory 204996 kb
Host smart-13e81c81-4cb2-4808-a0f9-8ac9f28d0059
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768997893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2768997893
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.1002392602
Short name T854
Test name
Test status
Simulation time 37599160621 ps
CPU time 547.8 seconds
Started Jul 07 05:36:52 PM PDT 24
Finished Jul 07 05:46:01 PM PDT 24
Peak memory 4556196 kb
Host smart-c3da8cbc-e950-4576-95be-40b5af363c3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002392602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.1002392602
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.3483221935
Short name T922
Test name
Test status
Simulation time 1428605662 ps
CPU time 7.51 seconds
Started Jul 07 05:36:50 PM PDT 24
Finished Jul 07 05:36:58 PM PDT 24
Peak memory 213212 kb
Host smart-f2210769-f163-4be4-83f2-8de2ef0abd32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483221935 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.3483221935
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.2329635513
Short name T1077
Test name
Test status
Simulation time 102697348 ps
CPU time 2.37 seconds
Started Jul 07 05:36:52 PM PDT 24
Finished Jul 07 05:36:55 PM PDT 24
Peak memory 205024 kb
Host smart-c804e1df-9b0a-4e9e-be72-d7a9a2a447c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329635513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.2329635513
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.4168752814
Short name T556
Test name
Test status
Simulation time 47669192 ps
CPU time 0.64 seconds
Started Jul 07 05:36:59 PM PDT 24
Finished Jul 07 05:37:01 PM PDT 24
Peak memory 204600 kb
Host smart-ef166a5f-86d3-4814-abee-368c56948f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168752814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.4168752814
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.891266083
Short name T561
Test name
Test status
Simulation time 698556027 ps
CPU time 7.5 seconds
Started Jul 07 05:36:58 PM PDT 24
Finished Jul 07 05:37:05 PM PDT 24
Peak memory 236844 kb
Host smart-af8df95b-19a5-47b3-82fd-a2a914167acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891266083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.891266083
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2627845661
Short name T1442
Test name
Test status
Simulation time 635569256 ps
CPU time 16.83 seconds
Started Jul 07 05:36:56 PM PDT 24
Finished Jul 07 05:37:13 PM PDT 24
Peak memory 271976 kb
Host smart-f68af646-71b5-479a-b0c8-f5daf9aa846b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627845661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.2627845661
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3935334578
Short name T79
Test name
Test status
Simulation time 3426530766 ps
CPU time 41.63 seconds
Started Jul 07 05:36:53 PM PDT 24
Finished Jul 07 05:37:35 PM PDT 24
Peak memory 376536 kb
Host smart-9a467132-6e78-43a6-948a-eb4cf1af7460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935334578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3935334578
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.408525799
Short name T1074
Test name
Test status
Simulation time 8723588033 ps
CPU time 89.39 seconds
Started Jul 07 05:36:59 PM PDT 24
Finished Jul 07 05:38:29 PM PDT 24
Peak memory 814384 kb
Host smart-d2652708-866f-4577-912d-071292efe788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408525799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.408525799
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.3085753127
Short name T241
Test name
Test status
Simulation time 181823437 ps
CPU time 1.01 seconds
Started Jul 07 05:36:55 PM PDT 24
Finished Jul 07 05:36:56 PM PDT 24
Peak memory 204712 kb
Host smart-33a3f02a-ab82-48fe-8f03-39a21e1f6396
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085753127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.3085753127
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.920732906
Short name T3
Test name
Test status
Simulation time 135133371 ps
CPU time 7.4 seconds
Started Jul 07 05:36:52 PM PDT 24
Finished Jul 07 05:37:00 PM PDT 24
Peak memory 205320 kb
Host smart-e5a1895f-8aca-415c-a0e5-9b996876aea8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920732906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.
920732906
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2014064576
Short name T104
Test name
Test status
Simulation time 3714992828 ps
CPU time 84.13 seconds
Started Jul 07 05:36:58 PM PDT 24
Finished Jul 07 05:38:23 PM PDT 24
Peak memory 1094296 kb
Host smart-61188280-e8db-47ef-966c-8577e1cbc167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014064576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2014064576
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.529928559
Short name T562
Test name
Test status
Simulation time 2393967696 ps
CPU time 11.2 seconds
Started Jul 07 05:36:55 PM PDT 24
Finished Jul 07 05:37:07 PM PDT 24
Peak memory 205004 kb
Host smart-8e69a5aa-7884-4405-892b-17724486e2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529928559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.529928559
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.3390554699
Short name T1284
Test name
Test status
Simulation time 2227510392 ps
CPU time 46.61 seconds
Started Jul 07 05:37:01 PM PDT 24
Finished Jul 07 05:37:48 PM PDT 24
Peak memory 460464 kb
Host smart-96d62560-4742-439a-8ed8-baf817e77766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390554699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.3390554699
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.3391037836
Short name T163
Test name
Test status
Simulation time 48203486 ps
CPU time 0.71 seconds
Started Jul 07 05:36:58 PM PDT 24
Finished Jul 07 05:37:00 PM PDT 24
Peak memory 204724 kb
Host smart-f4faec34-eaf0-4912-b709-3c37bcc33551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391037836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.3391037836
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.1448698234
Short name T41
Test name
Test status
Simulation time 5661725855 ps
CPU time 23.12 seconds
Started Jul 07 05:36:54 PM PDT 24
Finished Jul 07 05:37:17 PM PDT 24
Peak memory 205308 kb
Host smart-25959f5e-941a-4b25-b8f7-1225e4285006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448698234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.1448698234
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.6934065
Short name T329
Test name
Test status
Simulation time 164416051 ps
CPU time 1.64 seconds
Started Jul 07 05:36:54 PM PDT 24
Finished Jul 07 05:36:56 PM PDT 24
Peak memory 205384 kb
Host smart-f3d1b323-6bfc-4ba9-9ae6-7270e43135a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6934065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.6934065
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.3380988885
Short name T527
Test name
Test status
Simulation time 10925109727 ps
CPU time 22.91 seconds
Started Jul 07 05:36:51 PM PDT 24
Finished Jul 07 05:37:15 PM PDT 24
Peak memory 323264 kb
Host smart-479c46dd-bca8-4f9d-a136-7da0c6986ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380988885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3380988885
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.3834888961
Short name T290
Test name
Test status
Simulation time 11432660973 ps
CPU time 739.46 seconds
Started Jul 07 05:36:57 PM PDT 24
Finished Jul 07 05:49:17 PM PDT 24
Peak memory 1178932 kb
Host smart-a896178b-f1d3-4b88-9bd8-13b8e2c1bb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834888961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.3834888961
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.68357481
Short name T640
Test name
Test status
Simulation time 8435258817 ps
CPU time 46.02 seconds
Started Jul 07 05:37:01 PM PDT 24
Finished Jul 07 05:37:47 PM PDT 24
Peak memory 215516 kb
Host smart-3772f341-806e-46f6-a52b-6a8f6668ff50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68357481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.68357481
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.1643619903
Short name T1264
Test name
Test status
Simulation time 927550012 ps
CPU time 4.63 seconds
Started Jul 07 05:37:01 PM PDT 24
Finished Jul 07 05:37:06 PM PDT 24
Peak memory 213232 kb
Host smart-4466d837-973d-4630-b72b-2eb2861118d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643619903 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.1643619903
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.2793062596
Short name T763
Test name
Test status
Simulation time 812678092 ps
CPU time 1.45 seconds
Started Jul 07 05:36:56 PM PDT 24
Finished Jul 07 05:36:58 PM PDT 24
Peak memory 206404 kb
Host smart-e48c3dbf-7741-44a0-9a1b-f4e0d6199b8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793062596 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.2793062596
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.403008590
Short name T727
Test name
Test status
Simulation time 249088738 ps
CPU time 1.47 seconds
Started Jul 07 05:36:57 PM PDT 24
Finished Jul 07 05:36:58 PM PDT 24
Peak memory 204872 kb
Host smart-d74e0bb2-b746-49e1-889b-651ad361b4f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403008590 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_fifo_reset_tx.403008590
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.1424108042
Short name T413
Test name
Test status
Simulation time 1823685702 ps
CPU time 2.6 seconds
Started Jul 07 05:37:00 PM PDT 24
Finished Jul 07 05:37:03 PM PDT 24
Peak memory 204944 kb
Host smart-9fc7dbb8-4e29-4ee7-aaf2-ec3e112bf05a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424108042 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.1424108042
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.1299629557
Short name T508
Test name
Test status
Simulation time 310998447 ps
CPU time 1.05 seconds
Started Jul 07 05:37:00 PM PDT 24
Finished Jul 07 05:37:02 PM PDT 24
Peak memory 204836 kb
Host smart-ed33106f-1b22-4757-a81e-ac7f4ee9d822
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299629557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.1299629557
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.684252247
Short name T349
Test name
Test status
Simulation time 325795709 ps
CPU time 4.48 seconds
Started Jul 07 05:37:01 PM PDT 24
Finished Jul 07 05:37:06 PM PDT 24
Peak memory 205024 kb
Host smart-996eb40a-6262-4bc1-aaa8-3d417df5468a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684252247 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_hrst.684252247
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.2125651068
Short name T818
Test name
Test status
Simulation time 705476557 ps
CPU time 4.68 seconds
Started Jul 07 05:36:58 PM PDT 24
Finished Jul 07 05:37:03 PM PDT 24
Peak memory 213512 kb
Host smart-7324b6ce-9e1f-4924-8d1c-0b2ce0abcdb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125651068 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.2125651068
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3618922449
Short name T1510
Test name
Test status
Simulation time 19795467477 ps
CPU time 49.51 seconds
Started Jul 07 05:36:57 PM PDT 24
Finished Jul 07 05:37:47 PM PDT 24
Peak memory 835792 kb
Host smart-ba5bad68-7595-45b7-8c00-e980b5906995
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618922449 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3618922449
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2440879453
Short name T270
Test name
Test status
Simulation time 776826337 ps
CPU time 12.31 seconds
Started Jul 07 05:36:58 PM PDT 24
Finished Jul 07 05:37:11 PM PDT 24
Peak memory 205044 kb
Host smart-d13b2eb9-0476-400c-93a8-f7f2d2305b70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440879453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2440879453
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.211664325
Short name T1263
Test name
Test status
Simulation time 1484514441 ps
CPU time 26.51 seconds
Started Jul 07 05:36:55 PM PDT 24
Finished Jul 07 05:37:22 PM PDT 24
Peak memory 221616 kb
Host smart-bfa2d827-4dfc-4c2b-9e27-4851e8db4d7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211664325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.211664325
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.589953295
Short name T1154
Test name
Test status
Simulation time 34804131106 ps
CPU time 150.15 seconds
Started Jul 07 05:36:55 PM PDT 24
Finished Jul 07 05:39:26 PM PDT 24
Peak memory 2129668 kb
Host smart-7d90228d-0518-47c1-912f-2fdbbb7c4eb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589953295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.589953295
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.3834111085
Short name T666
Test name
Test status
Simulation time 3255789064 ps
CPU time 66.04 seconds
Started Jul 07 05:37:01 PM PDT 24
Finished Jul 07 05:38:07 PM PDT 24
Peak memory 939548 kb
Host smart-0fa5d2d5-c21e-4aef-a9d6-164145b807a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834111085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.3834111085
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.2296545191
Short name T540
Test name
Test status
Simulation time 1434949297 ps
CPU time 8.08 seconds
Started Jul 07 05:37:02 PM PDT 24
Finished Jul 07 05:37:10 PM PDT 24
Peak memory 221232 kb
Host smart-98afc748-c3d5-42fc-8bdb-488b09d7ef07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296545191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.2296545191
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.1822834906
Short name T1502
Test name
Test status
Simulation time 55957877 ps
CPU time 1.34 seconds
Started Jul 07 05:36:58 PM PDT 24
Finished Jul 07 05:37:00 PM PDT 24
Peak memory 205028 kb
Host smart-7e1f6740-b2b4-49e4-a772-4ecb48cdfd9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822834906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.1822834906
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1296476548
Short name T1473
Test name
Test status
Simulation time 56337184 ps
CPU time 0.65 seconds
Started Jul 07 05:37:03 PM PDT 24
Finished Jul 07 05:37:04 PM PDT 24
Peak memory 204884 kb
Host smart-e71468a8-d515-47c8-a2f4-646e56e9f09e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296476548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1296476548
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2315997771
Short name T811
Test name
Test status
Simulation time 76436533 ps
CPU time 1.37 seconds
Started Jul 07 05:37:00 PM PDT 24
Finished Jul 07 05:37:02 PM PDT 24
Peak memory 221524 kb
Host smart-3d4544d0-bc54-44ed-aef6-b4592fa7fe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315997771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2315997771
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.643169568
Short name T1516
Test name
Test status
Simulation time 1088173810 ps
CPU time 14.11 seconds
Started Jul 07 05:37:03 PM PDT 24
Finished Jul 07 05:37:18 PM PDT 24
Peak memory 255288 kb
Host smart-0dc094bc-c1d6-4119-b166-db79584e10ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643169568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empt
y.643169568
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.2157959121
Short name T1059
Test name
Test status
Simulation time 2327629139 ps
CPU time 58.81 seconds
Started Jul 07 05:37:05 PM PDT 24
Finished Jul 07 05:38:04 PM PDT 24
Peak memory 572972 kb
Host smart-17ffbcda-7830-4242-835f-4ac84e754c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157959121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2157959121
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.1960380184
Short name T338
Test name
Test status
Simulation time 1435182346 ps
CPU time 94.38 seconds
Started Jul 07 05:37:05 PM PDT 24
Finished Jul 07 05:38:40 PM PDT 24
Peak memory 490996 kb
Host smart-aa00d025-2d82-48a8-bcbb-30851912f636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960380184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.1960380184
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.654437732
Short name T242
Test name
Test status
Simulation time 701386143 ps
CPU time 1.31 seconds
Started Jul 07 05:37:05 PM PDT 24
Finished Jul 07 05:37:07 PM PDT 24
Peak memory 204192 kb
Host smart-9317d24e-c263-4ac3-b80f-064be601c2ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654437732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fm
t.654437732
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.3315844330
Short name T589
Test name
Test status
Simulation time 185166144 ps
CPU time 9.6 seconds
Started Jul 07 05:37:02 PM PDT 24
Finished Jul 07 05:37:12 PM PDT 24
Peak memory 204972 kb
Host smart-b3017102-5fb5-40e4-aa58-4afde256fbbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315844330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.3315844330
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2781773259
Short name T1115
Test name
Test status
Simulation time 8846444455 ps
CPU time 134.91 seconds
Started Jul 07 05:37:00 PM PDT 24
Finished Jul 07 05:39:15 PM PDT 24
Peak memory 1478996 kb
Host smart-e4f63b44-664f-4ec5-9745-5ff308c36718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781773259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2781773259
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.617810472
Short name T252
Test name
Test status
Simulation time 1106943994 ps
CPU time 23.32 seconds
Started Jul 07 05:37:04 PM PDT 24
Finished Jul 07 05:37:27 PM PDT 24
Peak memory 205060 kb
Host smart-685ed379-3478-4c55-b946-257f763ca4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617810472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.617810472
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.3180042538
Short name T247
Test name
Test status
Simulation time 1828749575 ps
CPU time 35.22 seconds
Started Jul 07 05:37:04 PM PDT 24
Finished Jul 07 05:37:40 PM PDT 24
Peak memory 380164 kb
Host smart-42db6d6f-130f-42a0-8e09-a66f36594229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180042538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.3180042538
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.825555505
Short name T37
Test name
Test status
Simulation time 18291430 ps
CPU time 0.67 seconds
Started Jul 07 05:37:00 PM PDT 24
Finished Jul 07 05:37:01 PM PDT 24
Peak memory 204724 kb
Host smart-26c58da1-c40e-41fe-bfaf-c4278292a10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825555505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.825555505
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.771868037
Short name T535
Test name
Test status
Simulation time 1439120595 ps
CPU time 30.1 seconds
Started Jul 07 05:37:01 PM PDT 24
Finished Jul 07 05:37:31 PM PDT 24
Peak memory 213180 kb
Host smart-4622445e-761e-4c81-8908-f2d52ee11c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771868037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.771868037
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.2799239561
Short name T761
Test name
Test status
Simulation time 5801250570 ps
CPU time 57.27 seconds
Started Jul 07 05:37:03 PM PDT 24
Finished Jul 07 05:38:00 PM PDT 24
Peak memory 205008 kb
Host smart-fc877571-6f3e-44af-a086-a00407be3b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799239561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.2799239561
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.417950905
Short name T1466
Test name
Test status
Simulation time 1609832693 ps
CPU time 30.1 seconds
Started Jul 07 05:37:02 PM PDT 24
Finished Jul 07 05:37:33 PM PDT 24
Peak memory 312092 kb
Host smart-df010d37-5b59-4b57-89a9-ce38b1fb63e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417950905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.417950905
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.4069889950
Short name T979
Test name
Test status
Simulation time 497152693 ps
CPU time 7.88 seconds
Started Jul 07 05:37:02 PM PDT 24
Finished Jul 07 05:37:11 PM PDT 24
Peak memory 221072 kb
Host smart-8a3c4696-9bbf-4165-81e5-37d0bcffc058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069889950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.4069889950
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.1512389958
Short name T648
Test name
Test status
Simulation time 1639905857 ps
CPU time 4.22 seconds
Started Jul 07 05:37:06 PM PDT 24
Finished Jul 07 05:37:11 PM PDT 24
Peak memory 204992 kb
Host smart-b5af9a15-0c78-422e-9f04-11e0c335dcfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512389958 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.1512389958
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1867612337
Short name T1134
Test name
Test status
Simulation time 162919230 ps
CPU time 1.02 seconds
Started Jul 07 05:37:03 PM PDT 24
Finished Jul 07 05:37:04 PM PDT 24
Peak memory 204712 kb
Host smart-21b911e0-c7ef-4748-bb53-fdd12623a49a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867612337 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1867612337
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.75054353
Short name T1283
Test name
Test status
Simulation time 237254627 ps
CPU time 1.48 seconds
Started Jul 07 05:37:06 PM PDT 24
Finished Jul 07 05:37:07 PM PDT 24
Peak memory 204988 kb
Host smart-df06ebcb-298f-4d78-bdee-d05e5b3e6ebc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75054353 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_fifo_reset_tx.75054353
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.790595349
Short name T661
Test name
Test status
Simulation time 2284347175 ps
CPU time 3.17 seconds
Started Jul 07 05:37:05 PM PDT 24
Finished Jul 07 05:37:09 PM PDT 24
Peak memory 205088 kb
Host smart-e57f4e30-c53c-4799-b96c-c31d229d4cac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790595349 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.790595349
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.3581240532
Short name T255
Test name
Test status
Simulation time 148670081 ps
CPU time 1.2 seconds
Started Jul 07 05:37:06 PM PDT 24
Finished Jul 07 05:37:07 PM PDT 24
Peak memory 204804 kb
Host smart-212c3a9d-bd90-428a-a7a9-f7bfe6e2bd3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581240532 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.3581240532
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.2233557881
Short name T423
Test name
Test status
Simulation time 301762410 ps
CPU time 3.32 seconds
Started Jul 07 05:37:05 PM PDT 24
Finished Jul 07 05:37:08 PM PDT 24
Peak memory 205060 kb
Host smart-c95f4003-f209-4566-838b-b06ac7dd470c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233557881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.2233557881
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2577071769
Short name T1148
Test name
Test status
Simulation time 915874634 ps
CPU time 5.04 seconds
Started Jul 07 05:37:06 PM PDT 24
Finished Jul 07 05:37:11 PM PDT 24
Peak memory 217384 kb
Host smart-03ad2360-b509-44dd-9288-f3de168f2185
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577071769 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2577071769
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1864779610
Short name T388
Test name
Test status
Simulation time 11923345890 ps
CPU time 79.36 seconds
Started Jul 07 05:37:03 PM PDT 24
Finished Jul 07 05:38:22 PM PDT 24
Peak memory 1274140 kb
Host smart-13c71959-45b2-4372-ae06-11e207d8b886
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864779610 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1864779610
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.4196435760
Short name T1009
Test name
Test status
Simulation time 790717308 ps
CPU time 10.82 seconds
Started Jul 07 05:37:05 PM PDT 24
Finished Jul 07 05:37:17 PM PDT 24
Peak memory 205000 kb
Host smart-c037f96e-5560-4506-aafe-150d693cdae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196435760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.4196435760
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.827214395
Short name T553
Test name
Test status
Simulation time 3759470132 ps
CPU time 18.4 seconds
Started Jul 07 05:37:01 PM PDT 24
Finished Jul 07 05:37:20 PM PDT 24
Peak memory 215428 kb
Host smart-6b514fda-4532-410e-9b3a-fc6b78d52de9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827214395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.827214395
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.885405657
Short name T844
Test name
Test status
Simulation time 40217033929 ps
CPU time 193.03 seconds
Started Jul 07 05:37:02 PM PDT 24
Finished Jul 07 05:40:15 PM PDT 24
Peak memory 2633192 kb
Host smart-aed25b18-3b60-476d-958b-c24f36038d34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885405657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_wr.885405657
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.1704033227
Short name T701
Test name
Test status
Simulation time 1911221469 ps
CPU time 29.11 seconds
Started Jul 07 05:37:02 PM PDT 24
Finished Jul 07 05:37:32 PM PDT 24
Peak memory 617516 kb
Host smart-932e3c3b-6862-4b32-8f9c-bd5dbaaa1eac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704033227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.1704033227
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1015844851
Short name T800
Test name
Test status
Simulation time 3834406866 ps
CPU time 6.17 seconds
Started Jul 07 05:37:06 PM PDT 24
Finished Jul 07 05:37:13 PM PDT 24
Peak memory 213268 kb
Host smart-aafc4bd4-1995-4867-b817-6d3ce04efb98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015844851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1015844851
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.886371770
Short name T676
Test name
Test status
Simulation time 53181783 ps
CPU time 1.34 seconds
Started Jul 07 05:37:06 PM PDT 24
Finished Jul 07 05:37:07 PM PDT 24
Peak memory 205032 kb
Host smart-7259163c-31f5-4874-a7a3-1536d40bb6c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886371770 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.886371770
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.898945172
Short name T822
Test name
Test status
Simulation time 18560107 ps
CPU time 0.67 seconds
Started Jul 07 05:37:09 PM PDT 24
Finished Jul 07 05:37:11 PM PDT 24
Peak memory 204572 kb
Host smart-b783cc13-0286-49fb-b5a0-e03c92f2e833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898945172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.898945172
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.4096676562
Short name T981
Test name
Test status
Simulation time 270389807 ps
CPU time 2.15 seconds
Started Jul 07 05:37:07 PM PDT 24
Finished Jul 07 05:37:10 PM PDT 24
Peak memory 213620 kb
Host smart-3b919f2b-f943-4e1b-aee0-0a799d35f2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096676562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.4096676562
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3415855719
Short name T1488
Test name
Test status
Simulation time 224278208 ps
CPU time 11.19 seconds
Started Jul 07 05:37:07 PM PDT 24
Finished Jul 07 05:37:19 PM PDT 24
Peak memory 248720 kb
Host smart-516cc550-07a4-4637-82cb-b887543b0fd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415855719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3415855719
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.916771554
Short name T945
Test name
Test status
Simulation time 8151498060 ps
CPU time 47.63 seconds
Started Jul 07 05:37:09 PM PDT 24
Finished Jul 07 05:37:58 PM PDT 24
Peak memory 522736 kb
Host smart-04069514-53d4-487b-81e4-b7584c339874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916771554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.916771554
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.4245818045
Short name T740
Test name
Test status
Simulation time 9027148041 ps
CPU time 80.22 seconds
Started Jul 07 05:37:14 PM PDT 24
Finished Jul 07 05:38:35 PM PDT 24
Peak memory 734324 kb
Host smart-9a3c351c-3b90-40b0-adbf-2f0baf0611c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245818045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.4245818045
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.1739540965
Short name T450
Test name
Test status
Simulation time 113011480 ps
CPU time 1.14 seconds
Started Jul 07 05:37:14 PM PDT 24
Finished Jul 07 05:37:16 PM PDT 24
Peak memory 204748 kb
Host smart-8c7a604b-0dee-4963-9af5-01e64ed84e4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739540965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.1739540965
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.695276044
Short name T1361
Test name
Test status
Simulation time 626053319 ps
CPU time 9.63 seconds
Started Jul 07 05:37:07 PM PDT 24
Finished Jul 07 05:37:17 PM PDT 24
Peak memory 204996 kb
Host smart-b114b615-87e4-4a36-8715-7c72d67bda50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695276044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.
695276044
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.823651007
Short name T999
Test name
Test status
Simulation time 9427147088 ps
CPU time 148.59 seconds
Started Jul 07 05:37:07 PM PDT 24
Finished Jul 07 05:39:36 PM PDT 24
Peak memory 1382464 kb
Host smart-d617bad9-2f7d-4c0b-8b98-b018d4b61c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823651007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.823651007
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.2156221905
Short name T1339
Test name
Test status
Simulation time 2456714322 ps
CPU time 9.52 seconds
Started Jul 07 05:37:19 PM PDT 24
Finished Jul 07 05:37:29 PM PDT 24
Peak memory 204912 kb
Host smart-4bb561e0-4748-4012-abeb-b38e95e1eacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156221905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2156221905
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.3721338276
Short name T1523
Test name
Test status
Simulation time 3697321925 ps
CPU time 22.36 seconds
Started Jul 07 05:37:12 PM PDT 24
Finished Jul 07 05:37:35 PM PDT 24
Peak memory 297256 kb
Host smart-90b1953e-5d0f-4b86-a4fa-a2b7a35d75bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721338276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.3721338276
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.3152326266
Short name T1479
Test name
Test status
Simulation time 53160364 ps
CPU time 0.65 seconds
Started Jul 07 05:37:06 PM PDT 24
Finished Jul 07 05:37:07 PM PDT 24
Peak memory 204680 kb
Host smart-8ff29f69-8443-489d-b035-73470e3c601a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152326266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.3152326266
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1050746594
Short name T1133
Test name
Test status
Simulation time 7009735033 ps
CPU time 49.16 seconds
Started Jul 07 05:37:12 PM PDT 24
Finished Jul 07 05:38:01 PM PDT 24
Peak memory 205096 kb
Host smart-8767fc30-0462-4db8-9536-4c71f0707ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050746594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1050746594
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.1963546826
Short name T158
Test name
Test status
Simulation time 2452517479 ps
CPU time 47.44 seconds
Started Jul 07 05:37:08 PM PDT 24
Finished Jul 07 05:37:56 PM PDT 24
Peak memory 597948 kb
Host smart-6cf9b60f-e425-4f29-a9ab-71ec2c8314c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963546826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.1963546826
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.297971534
Short name T1195
Test name
Test status
Simulation time 6817871774 ps
CPU time 80.53 seconds
Started Jul 07 05:37:09 PM PDT 24
Finished Jul 07 05:38:30 PM PDT 24
Peak memory 346580 kb
Host smart-a04f8b9c-a941-4239-b937-08e7f55676b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297971534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.297971534
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.210453462
Short name T1166
Test name
Test status
Simulation time 22314895751 ps
CPU time 554.77 seconds
Started Jul 07 05:37:12 PM PDT 24
Finished Jul 07 05:46:28 PM PDT 24
Peak memory 2429040 kb
Host smart-3cc145fa-6980-4322-846b-172bc6102967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210453462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.210453462
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.427916160
Short name T779
Test name
Test status
Simulation time 1869111847 ps
CPU time 8.04 seconds
Started Jul 07 05:37:09 PM PDT 24
Finished Jul 07 05:37:18 PM PDT 24
Peak memory 213252 kb
Host smart-400c2381-c710-4d68-913b-2f64ea3eb2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427916160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.427916160
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.3489081394
Short name T307
Test name
Test status
Simulation time 1628807808 ps
CPU time 2.58 seconds
Started Jul 07 05:37:15 PM PDT 24
Finished Jul 07 05:37:17 PM PDT 24
Peak memory 205008 kb
Host smart-57372721-263a-4962-b67c-f3fecd79004d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489081394 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.3489081394
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.767388463
Short name T801
Test name
Test status
Simulation time 192546695 ps
CPU time 1.22 seconds
Started Jul 07 05:37:06 PM PDT 24
Finished Jul 07 05:37:07 PM PDT 24
Peak memory 204804 kb
Host smart-d2b654a1-ea0b-4daa-8810-93dec0ad14ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767388463 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_acq.767388463
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.3733032422
Short name T1323
Test name
Test status
Simulation time 288844192 ps
CPU time 1.58 seconds
Started Jul 07 05:37:08 PM PDT 24
Finished Jul 07 05:37:10 PM PDT 24
Peak memory 204960 kb
Host smart-5028263c-1cb7-47ef-bddb-efca2db312fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733032422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.3733032422
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.1766849010
Short name T1349
Test name
Test status
Simulation time 480573954 ps
CPU time 2.52 seconds
Started Jul 07 05:37:10 PM PDT 24
Finished Jul 07 05:37:13 PM PDT 24
Peak memory 204956 kb
Host smart-6f8fe8bd-ce6f-4910-8ad5-bf1409e4a8cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766849010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.1766849010
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.1948838767
Short name T932
Test name
Test status
Simulation time 199774751 ps
CPU time 1.05 seconds
Started Jul 07 05:37:12 PM PDT 24
Finished Jul 07 05:37:13 PM PDT 24
Peak memory 204800 kb
Host smart-215d1ade-5ad5-4b41-a51b-0fea35600cb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948838767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.1948838767
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.1171937806
Short name T1402
Test name
Test status
Simulation time 469305656 ps
CPU time 2.31 seconds
Started Jul 07 05:37:17 PM PDT 24
Finished Jul 07 05:37:19 PM PDT 24
Peak memory 205024 kb
Host smart-acb14405-e773-45bd-956f-5f27521d77d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171937806 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.1171937806
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.74331355
Short name T935
Test name
Test status
Simulation time 1275973933 ps
CPU time 3.95 seconds
Started Jul 07 05:37:08 PM PDT 24
Finished Jul 07 05:37:12 PM PDT 24
Peak memory 213156 kb
Host smart-3d6c0820-2deb-4882-bb66-57db2ff295f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74331355 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.74331355
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.1823502336
Short name T302
Test name
Test status
Simulation time 2440902006 ps
CPU time 3.37 seconds
Started Jul 07 05:37:07 PM PDT 24
Finished Jul 07 05:37:11 PM PDT 24
Peak memory 204848 kb
Host smart-14e41234-851d-44b3-ae38-7ba35cc33e4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823502336 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.1823502336
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.730066261
Short name T668
Test name
Test status
Simulation time 825235744 ps
CPU time 12.58 seconds
Started Jul 07 05:37:08 PM PDT 24
Finished Jul 07 05:37:21 PM PDT 24
Peak memory 205008 kb
Host smart-98563ab5-2660-4f34-ac5d-890513435f7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730066261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_tar
get_smoke.730066261
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.190234921
Short name T1035
Test name
Test status
Simulation time 1607924542 ps
CPU time 9.19 seconds
Started Jul 07 05:37:14 PM PDT 24
Finished Jul 07 05:37:23 PM PDT 24
Peak memory 204980 kb
Host smart-a9462c83-1e5b-4f44-b6d0-16feb0832621
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190234921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_rd.190234921
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.1212019194
Short name T1292
Test name
Test status
Simulation time 50185679758 ps
CPU time 1104.51 seconds
Started Jul 07 05:37:14 PM PDT 24
Finished Jul 07 05:55:39 PM PDT 24
Peak memory 7701960 kb
Host smart-15a05ce1-1432-4b7a-9c41-7106a9b28e89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212019194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.1212019194
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.2660138124
Short name T458
Test name
Test status
Simulation time 2802850047 ps
CPU time 22.32 seconds
Started Jul 07 05:37:06 PM PDT 24
Finished Jul 07 05:37:29 PM PDT 24
Peak memory 482864 kb
Host smart-5cdb542e-aca4-453e-ba00-2e16b3ee2879
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660138124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.2660138124
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2808457148
Short name T930
Test name
Test status
Simulation time 1088755601 ps
CPU time 6.85 seconds
Started Jul 07 05:37:09 PM PDT 24
Finished Jul 07 05:37:16 PM PDT 24
Peak memory 221236 kb
Host smart-1bbeb2ef-69f8-4947-9a52-ad96ee826909
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808457148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2808457148
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.265129916
Short name T1262
Test name
Test status
Simulation time 245185670 ps
CPU time 4.02 seconds
Started Jul 07 05:37:14 PM PDT 24
Finished Jul 07 05:37:18 PM PDT 24
Peak memory 205036 kb
Host smart-5cf060bd-506b-4839-97c9-2add538baf53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265129916 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.265129916
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.788510411
Short name T1302
Test name
Test status
Simulation time 18484441 ps
CPU time 0.63 seconds
Started Jul 07 05:37:32 PM PDT 24
Finished Jul 07 05:37:34 PM PDT 24
Peak memory 204560 kb
Host smart-9912730b-57f4-4a35-9022-f1af5fe00298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788510411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.788510411
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.3312174651
Short name T44
Test name
Test status
Simulation time 185311025 ps
CPU time 6.56 seconds
Started Jul 07 05:37:11 PM PDT 24
Finished Jul 07 05:37:18 PM PDT 24
Peak memory 236412 kb
Host smart-ed9d7625-4e4f-41f1-a28d-5844ab93d38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312174651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.3312174651
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.4241119110
Short name T1297
Test name
Test status
Simulation time 298347593 ps
CPU time 6.72 seconds
Started Jul 07 05:37:11 PM PDT 24
Finished Jul 07 05:37:18 PM PDT 24
Peak memory 263992 kb
Host smart-7f0c62d5-25fc-40bf-80ec-785c1f0ffbe9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241119110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.4241119110
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.3860371957
Short name T371
Test name
Test status
Simulation time 6574267761 ps
CPU time 107.97 seconds
Started Jul 07 05:37:13 PM PDT 24
Finished Jul 07 05:39:02 PM PDT 24
Peak memory 597468 kb
Host smart-c4c1654f-2e8d-492c-8528-2e3988d28f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860371957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.3860371957
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.840998507
Short name T1104
Test name
Test status
Simulation time 2792724384 ps
CPU time 78.52 seconds
Started Jul 07 05:37:09 PM PDT 24
Finished Jul 07 05:38:28 PM PDT 24
Peak memory 796868 kb
Host smart-40dd3d03-f416-41c7-8686-628d7d1ba086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840998507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.840998507
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.3155097663
Short name T451
Test name
Test status
Simulation time 164576918 ps
CPU time 1.29 seconds
Started Jul 07 05:37:16 PM PDT 24
Finished Jul 07 05:37:17 PM PDT 24
Peak memory 204740 kb
Host smart-a6eefcfc-f328-4601-b08f-ef5c60e7f9cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155097663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.3155097663
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.3677687135
Short name T755
Test name
Test status
Simulation time 176327121 ps
CPU time 3.77 seconds
Started Jul 07 05:37:19 PM PDT 24
Finished Jul 07 05:37:24 PM PDT 24
Peak memory 204884 kb
Host smart-0dd322f8-812a-4fa3-9d52-83a4833e6c94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677687135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.3677687135
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.649989930
Short name T463
Test name
Test status
Simulation time 4307331692 ps
CPU time 315.25 seconds
Started Jul 07 05:37:19 PM PDT 24
Finished Jul 07 05:42:35 PM PDT 24
Peak memory 1246984 kb
Host smart-0718bbe7-1632-432b-bf64-5a641a9d2757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649989930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.649989930
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.3202569778
Short name T1239
Test name
Test status
Simulation time 674771053 ps
CPU time 13.73 seconds
Started Jul 07 05:37:20 PM PDT 24
Finished Jul 07 05:37:34 PM PDT 24
Peak memory 205060 kb
Host smart-cbabf620-f7c1-4162-8d49-2af087770dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202569778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.3202569778
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.1510419819
Short name T40
Test name
Test status
Simulation time 6487676859 ps
CPU time 94.02 seconds
Started Jul 07 05:37:19 PM PDT 24
Finished Jul 07 05:38:54 PM PDT 24
Peak memory 350848 kb
Host smart-ec16028b-d539-4c9a-8380-a4feeccfb15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510419819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.1510419819
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.3777660658
Short name T346
Test name
Test status
Simulation time 17079151 ps
CPU time 0.73 seconds
Started Jul 07 05:37:13 PM PDT 24
Finished Jul 07 05:37:14 PM PDT 24
Peak memory 204724 kb
Host smart-1728d960-2a0f-473c-95d6-29d6ec593e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777660658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.3777660658
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.43087971
Short name T1202
Test name
Test status
Simulation time 6178852503 ps
CPU time 203.55 seconds
Started Jul 07 05:37:18 PM PDT 24
Finished Jul 07 05:40:42 PM PDT 24
Peak memory 1306564 kb
Host smart-d60f56e7-e174-4731-a211-795050e98a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43087971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.43087971
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.2142913598
Short name T141
Test name
Test status
Simulation time 222785774 ps
CPU time 10.38 seconds
Started Jul 07 05:37:19 PM PDT 24
Finished Jul 07 05:37:29 PM PDT 24
Peak memory 235380 kb
Host smart-9e585a04-dfea-4cb0-a1f1-fd65cdf499ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142913598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.2142913598
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3901956475
Short name T1168
Test name
Test status
Simulation time 23874431627 ps
CPU time 32.76 seconds
Started Jul 07 05:37:13 PM PDT 24
Finished Jul 07 05:37:46 PM PDT 24
Peak memory 450832 kb
Host smart-530ee2ee-4840-47b9-9bf1-f75ee98b9600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901956475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3901956475
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3596911337
Short name T63
Test name
Test status
Simulation time 11995216313 ps
CPU time 1050.71 seconds
Started Jul 07 05:37:16 PM PDT 24
Finished Jul 07 05:54:48 PM PDT 24
Peak memory 1954112 kb
Host smart-a0b46a36-a364-488d-8514-21bef3e52806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596911337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3596911337
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.720970877
Short name T282
Test name
Test status
Simulation time 800328664 ps
CPU time 14.29 seconds
Started Jul 07 05:37:18 PM PDT 24
Finished Jul 07 05:37:33 PM PDT 24
Peak memory 216852 kb
Host smart-24d4baa7-261e-433f-9dc3-5022b5d4e557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720970877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.720970877
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.2206553319
Short name T112
Test name
Test status
Simulation time 1833142827 ps
CPU time 4.33 seconds
Started Jul 07 05:37:13 PM PDT 24
Finished Jul 07 05:37:18 PM PDT 24
Peak memory 204996 kb
Host smart-531083f7-1d40-416e-904d-8974e47e95f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206553319 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.2206553319
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.1593505822
Short name T1203
Test name
Test status
Simulation time 186372082 ps
CPU time 1.21 seconds
Started Jul 07 05:37:21 PM PDT 24
Finished Jul 07 05:37:23 PM PDT 24
Peak memory 213220 kb
Host smart-af737e31-db0d-4bc2-bcc1-228029948cdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593505822 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.1593505822
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.1882993294
Short name T665
Test name
Test status
Simulation time 413270818 ps
CPU time 1.2 seconds
Started Jul 07 05:37:18 PM PDT 24
Finished Jul 07 05:37:19 PM PDT 24
Peak memory 204812 kb
Host smart-2d481067-7c0a-46c4-ac9c-90c80d761ad7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882993294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.1882993294
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.483646813
Short name T1429
Test name
Test status
Simulation time 5102873824 ps
CPU time 2.25 seconds
Started Jul 07 05:37:22 PM PDT 24
Finished Jul 07 05:37:24 PM PDT 24
Peak memory 204992 kb
Host smart-2c1cf4fa-2315-4496-bded-26daf0c4b283
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483646813 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.483646813
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.3439632751
Short name T1019
Test name
Test status
Simulation time 548517527 ps
CPU time 3.66 seconds
Started Jul 07 05:37:15 PM PDT 24
Finished Jul 07 05:37:19 PM PDT 24
Peak memory 205088 kb
Host smart-88709eba-3803-4e32-a99e-a4e36ea10030
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439632751 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.3439632751
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2058751363
Short name T1255
Test name
Test status
Simulation time 1377429723 ps
CPU time 8.5 seconds
Started Jul 07 05:37:16 PM PDT 24
Finished Jul 07 05:37:25 PM PDT 24
Peak memory 221324 kb
Host smart-f95c8f74-b805-40f2-a17b-261cd6b369c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058751363 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2058751363
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.318982479
Short name T595
Test name
Test status
Simulation time 14594918939 ps
CPU time 22.28 seconds
Started Jul 07 05:37:18 PM PDT 24
Finished Jul 07 05:37:41 PM PDT 24
Peak memory 527796 kb
Host smart-d5251053-537b-493a-a073-2bf0fc54e44c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318982479 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.318982479
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.1023179879
Short name T584
Test name
Test status
Simulation time 1609318417 ps
CPU time 24.76 seconds
Started Jul 07 05:37:19 PM PDT 24
Finished Jul 07 05:37:44 PM PDT 24
Peak memory 205000 kb
Host smart-dfdc4bac-fc48-4c69-8e58-1593a74d26b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023179879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.1023179879
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.803437608
Short name T1332
Test name
Test status
Simulation time 1591168862 ps
CPU time 6.89 seconds
Started Jul 07 05:37:19 PM PDT 24
Finished Jul 07 05:37:26 PM PDT 24
Peak memory 205036 kb
Host smart-08737a82-913f-4441-94e0-c625bfd2fa50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803437608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_rd.803437608
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.2136464233
Short name T1089
Test name
Test status
Simulation time 35275963019 ps
CPU time 387.46 seconds
Started Jul 07 05:37:19 PM PDT 24
Finished Jul 07 05:43:47 PM PDT 24
Peak memory 3957364 kb
Host smart-44896f56-83b4-404f-8845-f755c2cbc406
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136464233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.2136464233
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.2127634316
Short name T512
Test name
Test status
Simulation time 408080494 ps
CPU time 1.54 seconds
Started Jul 07 05:37:18 PM PDT 24
Finished Jul 07 05:37:20 PM PDT 24
Peak memory 204764 kb
Host smart-8e197c4c-99df-4921-bc29-f2d0ddb83ee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127634316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.2127634316
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1715759312
Short name T911
Test name
Test status
Simulation time 13299470211 ps
CPU time 7.04 seconds
Started Jul 07 05:37:19 PM PDT 24
Finished Jul 07 05:37:27 PM PDT 24
Peak memory 204960 kb
Host smart-347d210a-b61b-492d-a353-7f26dae5c650
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715759312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1715759312
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.3974283845
Short name T452
Test name
Test status
Simulation time 383211989 ps
CPU time 5.37 seconds
Started Jul 07 05:37:32 PM PDT 24
Finished Jul 07 05:37:38 PM PDT 24
Peak memory 204924 kb
Host smart-9918db8d-71b5-480d-b8fc-adf54fd143ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974283845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.3974283845
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.213108714
Short name T182
Test name
Test status
Simulation time 18577975 ps
CPU time 0.62 seconds
Started Jul 07 05:37:29 PM PDT 24
Finished Jul 07 05:37:30 PM PDT 24
Peak memory 204564 kb
Host smart-e2cc09a2-2b29-43c1-9535-c77a7a539190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213108714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.213108714
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.365194411
Short name T50
Test name
Test status
Simulation time 290143247 ps
CPU time 3.05 seconds
Started Jul 07 05:37:28 PM PDT 24
Finished Jul 07 05:37:32 PM PDT 24
Peak memory 215652 kb
Host smart-b450f54d-6625-4f15-9b1c-701017db0ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365194411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.365194411
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.1081421891
Short name T1366
Test name
Test status
Simulation time 603904538 ps
CPU time 5.32 seconds
Started Jul 07 05:37:21 PM PDT 24
Finished Jul 07 05:37:26 PM PDT 24
Peak memory 267720 kb
Host smart-edbd9fdc-06d4-43c6-8a2a-74f72d123561
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081421891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.1081421891
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.4157559621
Short name T77
Test name
Test status
Simulation time 7787622448 ps
CPU time 69.15 seconds
Started Jul 07 05:37:18 PM PDT 24
Finished Jul 07 05:38:27 PM PDT 24
Peak memory 674088 kb
Host smart-43286bb1-479b-4e7e-ab3d-ebcba6cc336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157559621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.4157559621
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3810558813
Short name T1273
Test name
Test status
Simulation time 2334987222 ps
CPU time 162.53 seconds
Started Jul 07 05:37:30 PM PDT 24
Finished Jul 07 05:40:13 PM PDT 24
Peak memory 760632 kb
Host smart-131d7b58-5060-4832-aef7-36b562b729d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810558813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3810558813
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.3645939364
Short name T876
Test name
Test status
Simulation time 111949932 ps
CPU time 1.12 seconds
Started Jul 07 05:37:26 PM PDT 24
Finished Jul 07 05:37:28 PM PDT 24
Peak memory 204752 kb
Host smart-ad935e81-1fe4-4be8-971a-628713e79ee4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645939364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.3645939364
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3602635472
Short name T1229
Test name
Test status
Simulation time 457717938 ps
CPU time 5.49 seconds
Started Jul 07 05:37:29 PM PDT 24
Finished Jul 07 05:37:36 PM PDT 24
Peak memory 204968 kb
Host smart-8d3fbc74-7ec1-4e45-a2fd-78e7bcdc494e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602635472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3602635472
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.3866664311
Short name T1240
Test name
Test status
Simulation time 251728735 ps
CPU time 10.76 seconds
Started Jul 07 05:37:30 PM PDT 24
Finished Jul 07 05:37:42 PM PDT 24
Peak memory 205028 kb
Host smart-55f76c32-dd2f-42d9-a036-1ee194469889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866664311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.3866664311
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.1940391766
Short name T369
Test name
Test status
Simulation time 1315798984 ps
CPU time 20.61 seconds
Started Jul 07 05:37:28 PM PDT 24
Finished Jul 07 05:37:49 PM PDT 24
Peak memory 318948 kb
Host smart-a19b0349-a066-410e-a7d8-d2efa1a23c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940391766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1940391766
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.3802044088
Short name T72
Test name
Test status
Simulation time 82935664 ps
CPU time 0.64 seconds
Started Jul 07 05:37:30 PM PDT 24
Finished Jul 07 05:37:32 PM PDT 24
Peak memory 204716 kb
Host smart-4efbdf62-a871-4a57-b97d-b78d1dcedd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802044088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3802044088
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.3353115271
Short name T412
Test name
Test status
Simulation time 27732479493 ps
CPU time 2318.78 seconds
Started Jul 07 05:37:37 PM PDT 24
Finished Jul 07 06:16:17 PM PDT 24
Peak memory 4332080 kb
Host smart-3bfe2b6b-1dd9-4aeb-acdc-5b9a1221a777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353115271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.3353115271
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.1899961116
Short name T1027
Test name
Test status
Simulation time 74206801 ps
CPU time 2.91 seconds
Started Jul 07 05:37:33 PM PDT 24
Finished Jul 07 05:37:37 PM PDT 24
Peak memory 204940 kb
Host smart-a7328654-d770-42d6-96ed-d214a4f88ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899961116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.1899961116
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.3567291452
Short name T713
Test name
Test status
Simulation time 2064990114 ps
CPU time 38.81 seconds
Started Jul 07 05:37:27 PM PDT 24
Finished Jul 07 05:38:06 PM PDT 24
Peak memory 439816 kb
Host smart-523a46e5-c901-4125-9d9a-61e1973d920a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567291452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3567291452
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.3068065184
Short name T237
Test name
Test status
Simulation time 104995379699 ps
CPU time 1912.13 seconds
Started Jul 07 05:37:21 PM PDT 24
Finished Jul 07 06:09:14 PM PDT 24
Peak memory 4198364 kb
Host smart-0e0f1413-1930-4478-8d14-3924ef703e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068065184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.3068065184
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.2136403622
Short name T1280
Test name
Test status
Simulation time 2219541597 ps
CPU time 20.54 seconds
Started Jul 07 05:37:30 PM PDT 24
Finished Jul 07 05:37:51 PM PDT 24
Peak memory 220920 kb
Host smart-563c7a31-db75-4f6d-b6f7-f75cce985acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136403622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2136403622
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1619485174
Short name T367
Test name
Test status
Simulation time 673451624 ps
CPU time 3.37 seconds
Started Jul 07 05:37:32 PM PDT 24
Finished Jul 07 05:37:37 PM PDT 24
Peak memory 205032 kb
Host smart-9086e19d-e194-4594-ba4f-52487b0889be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619485174 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1619485174
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2264330463
Short name T639
Test name
Test status
Simulation time 664206161 ps
CPU time 1.31 seconds
Started Jul 07 05:37:29 PM PDT 24
Finished Jul 07 05:37:31 PM PDT 24
Peak memory 204964 kb
Host smart-36bf76a4-84a0-4833-ac49-f9b81834c562
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264330463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2264330463
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.2870967449
Short name T28
Test name
Test status
Simulation time 1207982496 ps
CPU time 1.11 seconds
Started Jul 07 05:37:29 PM PDT 24
Finished Jul 07 05:37:30 PM PDT 24
Peak memory 206380 kb
Host smart-8681b04f-382f-4bed-83e9-0a84b6838ead
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870967449 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.2870967449
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.3954433183
Short name T1173
Test name
Test status
Simulation time 455514610 ps
CPU time 2.59 seconds
Started Jul 07 05:37:29 PM PDT 24
Finished Jul 07 05:37:32 PM PDT 24
Peak memory 204968 kb
Host smart-4815438c-66a1-4ca2-b028-73da59ab3cfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954433183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.3954433183
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.4027978892
Short name T306
Test name
Test status
Simulation time 145948088 ps
CPU time 1.25 seconds
Started Jul 07 05:37:31 PM PDT 24
Finished Jul 07 05:37:33 PM PDT 24
Peak memory 204788 kb
Host smart-237c7286-4d05-42d7-b8a3-a76d2dc3fc0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027978892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.4027978892
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3760053424
Short name T1250
Test name
Test status
Simulation time 1321534831 ps
CPU time 3.41 seconds
Started Jul 07 05:37:33 PM PDT 24
Finished Jul 07 05:37:38 PM PDT 24
Peak memory 205080 kb
Host smart-00c2a6db-a894-4c39-87a4-7b0178b7672b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760053424 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3760053424
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.3830601313
Short name T909
Test name
Test status
Simulation time 3177788825 ps
CPU time 7.95 seconds
Started Jul 07 05:37:29 PM PDT 24
Finished Jul 07 05:37:38 PM PDT 24
Peak memory 213404 kb
Host smart-790d45b2-912f-4dca-8f05-a86e99b2b299
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830601313 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.3830601313
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.1004899754
Short name T1006
Test name
Test status
Simulation time 30406746836 ps
CPU time 85.15 seconds
Started Jul 07 05:37:33 PM PDT 24
Finished Jul 07 05:39:00 PM PDT 24
Peak memory 1631552 kb
Host smart-3180c1c3-f373-4119-a917-23ca32a33042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004899754 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.1004899754
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.742450248
Short name T579
Test name
Test status
Simulation time 5055634672 ps
CPU time 54.51 seconds
Started Jul 07 05:37:31 PM PDT 24
Finished Jul 07 05:38:27 PM PDT 24
Peak memory 205092 kb
Host smart-ee26b658-fe47-4dea-8537-454efef96bba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742450248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_tar
get_smoke.742450248
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.3833153729
Short name T638
Test name
Test status
Simulation time 1038107235 ps
CPU time 14.36 seconds
Started Jul 07 05:37:31 PM PDT 24
Finished Jul 07 05:37:47 PM PDT 24
Peak memory 211480 kb
Host smart-9787e08f-fa23-47a2-b2b3-7bdac817f0ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833153729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.3833153729
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.1106914092
Short name T1275
Test name
Test status
Simulation time 35269584394 ps
CPU time 43.03 seconds
Started Jul 07 05:37:31 PM PDT 24
Finished Jul 07 05:38:15 PM PDT 24
Peak memory 783320 kb
Host smart-364ce0ea-6f5f-4cbf-b1f2-90bdc31bef9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106914092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.1106914092
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.3942180124
Short name T1364
Test name
Test status
Simulation time 3465317971 ps
CPU time 77.17 seconds
Started Jul 07 05:37:32 PM PDT 24
Finished Jul 07 05:38:50 PM PDT 24
Peak memory 555012 kb
Host smart-e8b7284f-d7a1-40d2-9f4f-8eb1cbf6b526
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942180124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.3942180124
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1465592996
Short name T1480
Test name
Test status
Simulation time 4029585293 ps
CPU time 5.99 seconds
Started Jul 07 05:37:37 PM PDT 24
Finished Jul 07 05:37:44 PM PDT 24
Peak memory 213308 kb
Host smart-44b54600-6f5a-4bf5-a208-c26a325d20b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465592996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1465592996
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.1599775804
Short name T437
Test name
Test status
Simulation time 381181888 ps
CPU time 5.4 seconds
Started Jul 07 05:37:31 PM PDT 24
Finished Jul 07 05:37:38 PM PDT 24
Peak memory 204988 kb
Host smart-06a5f5df-53c7-4b4d-8e50-0ceea619e6dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599775804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.1599775804
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.99253013
Short name T847
Test name
Test status
Simulation time 23673811 ps
CPU time 0.67 seconds
Started Jul 07 05:37:33 PM PDT 24
Finished Jul 07 05:37:34 PM PDT 24
Peak memory 204600 kb
Host smart-9b32c51e-a8ef-4563-89e5-4354dc2c1de9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99253013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.99253013
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.391431794
Short name T1252
Test name
Test status
Simulation time 239979008 ps
CPU time 2.7 seconds
Started Jul 07 05:37:32 PM PDT 24
Finished Jul 07 05:37:36 PM PDT 24
Peak memory 213336 kb
Host smart-d9559dd5-b2aa-48d3-9f8d-4001bb205a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391431794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.391431794
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.2007212335
Short name T114
Test name
Test status
Simulation time 1836866845 ps
CPU time 10.27 seconds
Started Jul 07 05:37:32 PM PDT 24
Finished Jul 07 05:37:43 PM PDT 24
Peak memory 297352 kb
Host smart-99ddd39a-4d46-4727-9756-872feabf7d10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007212335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.2007212335
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.3727539993
Short name T1465
Test name
Test status
Simulation time 28542678694 ps
CPU time 260.11 seconds
Started Jul 07 05:37:27 PM PDT 24
Finished Jul 07 05:41:47 PM PDT 24
Peak memory 989480 kb
Host smart-f7da1160-2389-4288-a79c-1ee43e76c9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727539993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.3727539993
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.2529954203
Short name T470
Test name
Test status
Simulation time 5198430740 ps
CPU time 189.25 seconds
Started Jul 07 05:37:37 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 765024 kb
Host smart-ff470db4-bfe2-45a2-a21f-2f807973838a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529954203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.2529954203
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.1268286984
Short name T767
Test name
Test status
Simulation time 131568422 ps
CPU time 3.13 seconds
Started Jul 07 05:37:29 PM PDT 24
Finished Jul 07 05:37:32 PM PDT 24
Peak memory 205028 kb
Host smart-1870577e-aa07-4b8c-8223-1bc6acc4cc67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268286984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.1268286984
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.2206087997
Short name T1217
Test name
Test status
Simulation time 4692328135 ps
CPU time 334.82 seconds
Started Jul 07 05:37:31 PM PDT 24
Finished Jul 07 05:43:07 PM PDT 24
Peak memory 1315712 kb
Host smart-101264e1-abe6-4555-91d2-bf2d3aae9fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206087997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2206087997
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.4273818085
Short name T475
Test name
Test status
Simulation time 342079659 ps
CPU time 14.58 seconds
Started Jul 07 05:37:27 PM PDT 24
Finished Jul 07 05:37:42 PM PDT 24
Peak memory 204984 kb
Host smart-0c2e9ad4-52ab-404e-9585-ea7931c669ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273818085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.4273818085
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.2067193480
Short name T1063
Test name
Test status
Simulation time 1128677144 ps
CPU time 56.11 seconds
Started Jul 07 05:37:30 PM PDT 24
Finished Jul 07 05:38:27 PM PDT 24
Peak memory 338656 kb
Host smart-0f0bebdd-5d26-46cd-9c64-7cfe06512b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067193480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.2067193480
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.121039130
Short name T541
Test name
Test status
Simulation time 33713343 ps
CPU time 0.64 seconds
Started Jul 07 05:37:31 PM PDT 24
Finished Jul 07 05:37:33 PM PDT 24
Peak memory 204648 kb
Host smart-13327ccb-c23e-40b4-8dfe-627a8273b547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121039130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.121039130
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1444289144
Short name T1268
Test name
Test status
Simulation time 2738751922 ps
CPU time 14.1 seconds
Started Jul 07 05:37:41 PM PDT 24
Finished Jul 07 05:37:56 PM PDT 24
Peak memory 355256 kb
Host smart-0219bed1-a8e6-438c-8d16-8f282dbdb40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444289144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1444289144
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.4132865991
Short name T238
Test name
Test status
Simulation time 893218496 ps
CPU time 35.57 seconds
Started Jul 07 05:37:31 PM PDT 24
Finished Jul 07 05:38:07 PM PDT 24
Peak memory 204996 kb
Host smart-3d4606ef-9afb-4d2e-92f2-7565cf0aebc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132865991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.4132865991
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.3419969785
Short name T715
Test name
Test status
Simulation time 6359878390 ps
CPU time 28.25 seconds
Started Jul 07 05:37:31 PM PDT 24
Finished Jul 07 05:38:00 PM PDT 24
Peak memory 337168 kb
Host smart-51eb90dc-0d64-489f-b426-2fa2cba999ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419969785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.3419969785
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.2334059957
Short name T919
Test name
Test status
Simulation time 787391306 ps
CPU time 14.47 seconds
Started Jul 07 05:37:32 PM PDT 24
Finished Jul 07 05:37:47 PM PDT 24
Peak memory 221416 kb
Host smart-84d6cdda-eae7-446d-9b08-6b2056c6ad1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334059957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.2334059957
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.1907674108
Short name T654
Test name
Test status
Simulation time 2890997544 ps
CPU time 3.78 seconds
Started Jul 07 05:37:34 PM PDT 24
Finished Jul 07 05:37:39 PM PDT 24
Peak memory 213324 kb
Host smart-da127196-0aa5-4925-a4c3-31effd5196af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907674108 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.1907674108
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3538357496
Short name T189
Test name
Test status
Simulation time 324651717 ps
CPU time 1.3 seconds
Started Jul 07 05:37:29 PM PDT 24
Finished Jul 07 05:37:31 PM PDT 24
Peak memory 204776 kb
Host smart-033a35c4-730e-418b-8407-6deffc831eff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538357496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3538357496
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.681722307
Short name T293
Test name
Test status
Simulation time 1709239329 ps
CPU time 1.53 seconds
Started Jul 07 05:37:29 PM PDT 24
Finished Jul 07 05:37:32 PM PDT 24
Peak memory 206008 kb
Host smart-64d625bc-f258-4c00-8ad6-f922d5b7f71f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681722307 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_tx.681722307
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.723932856
Short name T414
Test name
Test status
Simulation time 198074273 ps
CPU time 1.37 seconds
Started Jul 07 05:37:33 PM PDT 24
Finished Jul 07 05:37:35 PM PDT 24
Peak memory 204744 kb
Host smart-2246d76b-382a-4a6b-8c44-232b625fdc11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723932856 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.723932856
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.3378901856
Short name T440
Test name
Test status
Simulation time 218874064 ps
CPU time 1.07 seconds
Started Jul 07 05:37:32 PM PDT 24
Finished Jul 07 05:37:34 PM PDT 24
Peak memory 204752 kb
Host smart-91e7a6c2-1e64-40f8-a32b-73f559db34db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378901856 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.3378901856
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.396518736
Short name T249
Test name
Test status
Simulation time 290134341 ps
CPU time 2.91 seconds
Started Jul 07 05:37:32 PM PDT 24
Finished Jul 07 05:37:36 PM PDT 24
Peak memory 205148 kb
Host smart-099dd56b-c8de-4343-82b8-6d8e81cad899
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396518736 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_hrst.396518736
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.2711826859
Short name T780
Test name
Test status
Simulation time 1643545319 ps
CPU time 4.57 seconds
Started Jul 07 05:37:26 PM PDT 24
Finished Jul 07 05:37:31 PM PDT 24
Peak memory 204976 kb
Host smart-0a3ff158-6b8c-4488-af1d-cd3100094476
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711826859 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.2711826859
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.1457715529
Short name T1162
Test name
Test status
Simulation time 24288883950 ps
CPU time 73.83 seconds
Started Jul 07 05:37:30 PM PDT 24
Finished Jul 07 05:38:45 PM PDT 24
Peak memory 1496408 kb
Host smart-2ed5891b-e7b5-47da-ba7d-65a1442c18c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457715529 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.1457715529
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2568934394
Short name T1236
Test name
Test status
Simulation time 3496244382 ps
CPU time 14.81 seconds
Started Jul 07 05:37:31 PM PDT 24
Finished Jul 07 05:37:46 PM PDT 24
Peak memory 205060 kb
Host smart-1e3ee417-db8d-4335-878c-27ad258b5301
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568934394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2568934394
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.2503448705
Short name T505
Test name
Test status
Simulation time 1996789656 ps
CPU time 35.33 seconds
Started Jul 07 05:37:32 PM PDT 24
Finished Jul 07 05:38:09 PM PDT 24
Peak memory 225280 kb
Host smart-6485b410-0785-454a-ae9c-0e4642c81321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503448705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.2503448705
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.540144956
Short name T214
Test name
Test status
Simulation time 68480981584 ps
CPU time 847.55 seconds
Started Jul 07 05:37:33 PM PDT 24
Finished Jul 07 05:51:42 PM PDT 24
Peak memory 6184024 kb
Host smart-e28a22e7-908c-4bbb-bea9-1885172b42b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540144956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_wr.540144956
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.380020267
Short name T786
Test name
Test status
Simulation time 6986066464 ps
CPU time 51.62 seconds
Started Jul 07 05:37:30 PM PDT 24
Finished Jul 07 05:38:23 PM PDT 24
Peak memory 868468 kb
Host smart-3c1fcd99-d92b-4251-acab-d7c52761248e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380020267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stretch.380020267
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.2779444019
Short name T1453
Test name
Test status
Simulation time 2769658529 ps
CPU time 6.64 seconds
Started Jul 07 05:37:33 PM PDT 24
Finished Jul 07 05:37:41 PM PDT 24
Peak memory 205088 kb
Host smart-a0db8a30-8a49-45f6-9996-a91f2a5d2213
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779444019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.2779444019
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.2046785676
Short name T657
Test name
Test status
Simulation time 45011069 ps
CPU time 1.14 seconds
Started Jul 07 05:37:31 PM PDT 24
Finished Jul 07 05:37:33 PM PDT 24
Peak memory 205016 kb
Host smart-e9457a41-1635-4037-bc39-dccf2b6ec4eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046785676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.2046785676
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.360021838
Short name T341
Test name
Test status
Simulation time 16960183 ps
CPU time 0.63 seconds
Started Jul 07 05:33:32 PM PDT 24
Finished Jul 07 05:33:33 PM PDT 24
Peak memory 204452 kb
Host smart-a07bec4e-6cb6-4451-bc17-252e84622bc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360021838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.360021838
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3444766732
Short name T1507
Test name
Test status
Simulation time 273864559 ps
CPU time 11.18 seconds
Started Jul 07 05:33:20 PM PDT 24
Finished Jul 07 05:33:31 PM PDT 24
Peak memory 213240 kb
Host smart-205a2c68-c267-4912-ad8d-5f53d891809f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444766732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3444766732
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.3044488722
Short name T809
Test name
Test status
Simulation time 1564843861 ps
CPU time 23.16 seconds
Started Jul 07 05:33:30 PM PDT 24
Finished Jul 07 05:33:53 PM PDT 24
Peak memory 302636 kb
Host smart-90127ffc-b353-4876-9d79-8b35e3a3236a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044488722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.3044488722
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.3585394947
Short name T1199
Test name
Test status
Simulation time 8323948745 ps
CPU time 110.05 seconds
Started Jul 07 05:33:16 PM PDT 24
Finished Jul 07 05:35:06 PM PDT 24
Peak memory 441984 kb
Host smart-cc1fa3aa-2c9b-4fac-bed0-522b45f69c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585394947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.3585394947
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3577958068
Short name T737
Test name
Test status
Simulation time 10332903361 ps
CPU time 81.03 seconds
Started Jul 07 05:33:17 PM PDT 24
Finished Jul 07 05:34:39 PM PDT 24
Peak memory 821440 kb
Host smart-e73f7505-8216-4b28-a93d-4ad8cbda4f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577958068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3577958068
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1516872972
Short name T1096
Test name
Test status
Simulation time 436098399 ps
CPU time 1.1 seconds
Started Jul 07 05:33:21 PM PDT 24
Finished Jul 07 05:33:22 PM PDT 24
Peak memory 204632 kb
Host smart-14800314-6f42-47e3-a3fb-433f8200670a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516872972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1516872972
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.2801680516
Short name T1066
Test name
Test status
Simulation time 1141045191 ps
CPU time 9.81 seconds
Started Jul 07 05:33:20 PM PDT 24
Finished Jul 07 05:33:30 PM PDT 24
Peak memory 205064 kb
Host smart-fb622666-1ee6-4ffd-aaa7-17888c527386
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801680516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
2801680516
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.373537986
Short name T1234
Test name
Test status
Simulation time 4402376180 ps
CPU time 133.36 seconds
Started Jul 07 05:33:23 PM PDT 24
Finished Jul 07 05:35:38 PM PDT 24
Peak memory 1282340 kb
Host smart-8b9e6a68-9887-4743-af08-5d71073ac626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373537986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.373537986
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.651386625
Short name T1222
Test name
Test status
Simulation time 1125682523 ps
CPU time 21.98 seconds
Started Jul 07 05:33:32 PM PDT 24
Finished Jul 07 05:33:55 PM PDT 24
Peak memory 205040 kb
Host smart-1e9797e5-d97d-4739-a575-de1357fc92c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651386625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.651386625
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.946636386
Short name T1000
Test name
Test status
Simulation time 2713111052 ps
CPU time 38.04 seconds
Started Jul 07 05:33:32 PM PDT 24
Finished Jul 07 05:34:11 PM PDT 24
Peak memory 437100 kb
Host smart-f561a438-c403-4cca-9f5c-27dfee14a95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946636386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.946636386
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.2219700832
Short name T1416
Test name
Test status
Simulation time 83448273 ps
CPU time 0.67 seconds
Started Jul 07 05:33:25 PM PDT 24
Finished Jul 07 05:33:27 PM PDT 24
Peak memory 204696 kb
Host smart-234bcd37-f3d1-4548-b89b-0500b5e693dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219700832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.2219700832
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.493699904
Short name T1225
Test name
Test status
Simulation time 372230336 ps
CPU time 2.62 seconds
Started Jul 07 05:33:19 PM PDT 24
Finished Jul 07 05:33:22 PM PDT 24
Peak memory 229476 kb
Host smart-890aaf27-fa30-4ed5-9ecb-17e85bcfa0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493699904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.493699904
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.433629865
Short name T159
Test name
Test status
Simulation time 6272285831 ps
CPU time 26 seconds
Started Jul 07 05:33:25 PM PDT 24
Finished Jul 07 05:33:51 PM PDT 24
Peak memory 522152 kb
Host smart-7fa35465-0c64-432d-a190-41c637d136b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433629865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.433629865
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.844125745
Short name T650
Test name
Test status
Simulation time 2164561492 ps
CPU time 29.75 seconds
Started Jul 07 05:33:16 PM PDT 24
Finished Jul 07 05:33:46 PM PDT 24
Peak memory 341036 kb
Host smart-b32d82d1-014e-46d0-8145-acecc477161a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844125745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.844125745
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.3589773804
Short name T108
Test name
Test status
Simulation time 14540718892 ps
CPU time 450.55 seconds
Started Jul 07 05:33:21 PM PDT 24
Finished Jul 07 05:40:53 PM PDT 24
Peak memory 2887348 kb
Host smart-c4d4184b-28e7-47fc-bdcd-38d82a714720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589773804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.3589773804
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2457654445
Short name T616
Test name
Test status
Simulation time 1114480612 ps
CPU time 24.02 seconds
Started Jul 07 05:33:18 PM PDT 24
Finished Jul 07 05:33:42 PM PDT 24
Peak memory 213236 kb
Host smart-ec965220-d8b2-40fc-805c-f9ffab5d89b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457654445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2457654445
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.2965129317
Short name T1410
Test name
Test status
Simulation time 1083843404 ps
CPU time 3.06 seconds
Started Jul 07 05:33:19 PM PDT 24
Finished Jul 07 05:33:22 PM PDT 24
Peak memory 213200 kb
Host smart-5928cc8d-898b-44eb-9fb7-d5d02c9d58ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965129317 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2965129317
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.2723062408
Short name T928
Test name
Test status
Simulation time 762608255 ps
CPU time 1.39 seconds
Started Jul 07 05:33:21 PM PDT 24
Finished Jul 07 05:33:22 PM PDT 24
Peak memory 213116 kb
Host smart-9e78b6cc-d089-49ae-ac96-805a20ae81d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723062408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.2723062408
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.376794561
Short name T629
Test name
Test status
Simulation time 356330335 ps
CPU time 1.3 seconds
Started Jul 07 05:33:23 PM PDT 24
Finished Jul 07 05:33:25 PM PDT 24
Peak memory 207200 kb
Host smart-66a58eb1-e461-4d08-8b93-e1f4ebafc10a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376794561 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_tx.376794561
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.1687080998
Short name T549
Test name
Test status
Simulation time 718701593 ps
CPU time 1.34 seconds
Started Jul 07 05:33:23 PM PDT 24
Finished Jul 07 05:33:24 PM PDT 24
Peak memory 204752 kb
Host smart-e384bd23-da33-4722-bdfe-c7209e5d01cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687080998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.1687080998
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.4049319709
Short name T518
Test name
Test status
Simulation time 274452804 ps
CPU time 1.13 seconds
Started Jul 07 05:33:25 PM PDT 24
Finished Jul 07 05:33:27 PM PDT 24
Peak memory 204604 kb
Host smart-82abafab-2983-440a-8017-7c9ccab669c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049319709 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.4049319709
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.1990608208
Short name T1398
Test name
Test status
Simulation time 2061847384 ps
CPU time 3.29 seconds
Started Jul 07 05:33:22 PM PDT 24
Finished Jul 07 05:33:25 PM PDT 24
Peak memory 205028 kb
Host smart-f33a9fed-af1f-4ff2-9a7e-4f7679ad30ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990608208 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.1990608208
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3842591830
Short name T6
Test name
Test status
Simulation time 15833832175 ps
CPU time 13.1 seconds
Started Jul 07 05:33:21 PM PDT 24
Finished Jul 07 05:33:35 PM PDT 24
Peak memory 461368 kb
Host smart-72fea054-214a-44e1-a20d-7bf83870d115
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842591830 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3842591830
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.4082804861
Short name T91
Test name
Test status
Simulation time 462422044 ps
CPU time 17.52 seconds
Started Jul 07 05:33:24 PM PDT 24
Finished Jul 07 05:33:42 PM PDT 24
Peak memory 204984 kb
Host smart-0dd1ba6f-3b8a-4bc2-acd5-2c964c046949
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082804861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.4082804861
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3417744811
Short name T254
Test name
Test status
Simulation time 5257221320 ps
CPU time 20.91 seconds
Started Jul 07 05:33:22 PM PDT 24
Finished Jul 07 05:33:43 PM PDT 24
Peak memory 230896 kb
Host smart-2abcd2e9-eaf3-4154-a337-2f77e5f7670e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417744811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3417744811
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3889570084
Short name T949
Test name
Test status
Simulation time 3149706447 ps
CPU time 61.06 seconds
Started Jul 07 05:33:23 PM PDT 24
Finished Jul 07 05:34:25 PM PDT 24
Peak memory 480488 kb
Host smart-f37a16cc-c9a7-435a-87ef-3e28f3db1941
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889570084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3889570084
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.2434170067
Short name T384
Test name
Test status
Simulation time 1452455574 ps
CPU time 7.03 seconds
Started Jul 07 05:33:23 PM PDT 24
Finished Jul 07 05:33:31 PM PDT 24
Peak memory 213224 kb
Host smart-b9a6cb59-3646-4cb9-a34c-b59325a39c19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434170067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.2434170067
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.3417013259
Short name T529
Test name
Test status
Simulation time 1263556552 ps
CPU time 14.24 seconds
Started Jul 07 05:33:22 PM PDT 24
Finished Jul 07 05:33:37 PM PDT 24
Peak memory 204988 kb
Host smart-60bc6e17-07da-42d6-ba6c-452f17117b1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417013259 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.3417013259
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.1587392263
Short name T1285
Test name
Test status
Simulation time 47592980 ps
CPU time 0.61 seconds
Started Jul 07 05:33:28 PM PDT 24
Finished Jul 07 05:33:29 PM PDT 24
Peak memory 204588 kb
Host smart-ea1dcfd5-3b8a-4dc0-a1a7-49fbd3fdde5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587392263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1587392263
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.3575344977
Short name T1137
Test name
Test status
Simulation time 110321678 ps
CPU time 1.88 seconds
Started Jul 07 05:33:27 PM PDT 24
Finished Jul 07 05:33:29 PM PDT 24
Peak memory 213232 kb
Host smart-61b3591e-0402-46f9-b9ac-a583e526e1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575344977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.3575344977
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.2278401194
Short name T36
Test name
Test status
Simulation time 1174764057 ps
CPU time 9.47 seconds
Started Jul 07 05:33:20 PM PDT 24
Finished Jul 07 05:33:29 PM PDT 24
Peak memory 282400 kb
Host smart-ff9bfe22-aa60-48da-b923-0717707af641
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278401194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.2278401194
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2937493859
Short name T75
Test name
Test status
Simulation time 4705483408 ps
CPU time 73.94 seconds
Started Jul 07 05:33:23 PM PDT 24
Finished Jul 07 05:34:38 PM PDT 24
Peak memory 757188 kb
Host smart-e959b7f9-c9fb-40be-b88f-d578049a87f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937493859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2937493859
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.129036101
Short name T823
Test name
Test status
Simulation time 4117599072 ps
CPU time 146.79 seconds
Started Jul 07 05:33:21 PM PDT 24
Finished Jul 07 05:35:48 PM PDT 24
Peak memory 670160 kb
Host smart-3b6bf182-4f18-4a8c-b88b-d64cab2b26d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129036101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.129036101
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.31331716
Short name T243
Test name
Test status
Simulation time 97988585 ps
CPU time 1.08 seconds
Started Jul 07 05:33:24 PM PDT 24
Finished Jul 07 05:33:26 PM PDT 24
Peak memory 204724 kb
Host smart-f1967775-780a-4565-9294-e1a1b3d187f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31331716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt.31331716
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.466493665
Short name T1002
Test name
Test status
Simulation time 162908840 ps
CPU time 4.04 seconds
Started Jul 07 05:33:26 PM PDT 24
Finished Jul 07 05:33:31 PM PDT 24
Peak memory 204708 kb
Host smart-e27297b3-5900-4dc0-b605-83b7c44758ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466493665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.466493665
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2149802849
Short name T795
Test name
Test status
Simulation time 2819807098 ps
CPU time 152.03 seconds
Started Jul 07 05:33:26 PM PDT 24
Finished Jul 07 05:35:59 PM PDT 24
Peak memory 849512 kb
Host smart-ca9e00c2-7dae-4b3b-940e-5a28d77080c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149802849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2149802849
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.240925750
Short name T583
Test name
Test status
Simulation time 496164114 ps
CPU time 6.68 seconds
Started Jul 07 05:33:25 PM PDT 24
Finished Jul 07 05:33:32 PM PDT 24
Peak memory 204984 kb
Host smart-bf07e9a7-edcc-4b83-8ed1-2e9c83f67925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240925750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.240925750
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.1410334887
Short name T902
Test name
Test status
Simulation time 4208099870 ps
CPU time 21.23 seconds
Started Jul 07 05:33:24 PM PDT 24
Finished Jul 07 05:33:46 PM PDT 24
Peak memory 292952 kb
Host smart-07460f8c-4245-4662-9e17-a3ef4f45625e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410334887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.1410334887
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.2065464922
Short name T353
Test name
Test status
Simulation time 93262044 ps
CPU time 0.64 seconds
Started Jul 07 05:33:26 PM PDT 24
Finished Jul 07 05:33:27 PM PDT 24
Peak memory 204412 kb
Host smart-64396f0d-875b-40d8-9ed3-f55e28852c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065464922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2065464922
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.900533267
Short name T1426
Test name
Test status
Simulation time 5156072956 ps
CPU time 9.8 seconds
Started Jul 07 05:33:21 PM PDT 24
Finished Jul 07 05:33:31 PM PDT 24
Peak memory 251588 kb
Host smart-2d29a2ce-0d4d-42e4-b4ef-77d2b9d5a664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900533267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.900533267
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.1039419260
Short name T596
Test name
Test status
Simulation time 5889284910 ps
CPU time 117.12 seconds
Started Jul 07 05:33:22 PM PDT 24
Finished Jul 07 05:35:20 PM PDT 24
Peak memory 205016 kb
Host smart-c100649b-7be8-4a4a-bc85-f0ba0538d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039419260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.1039419260
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.3033618000
Short name T691
Test name
Test status
Simulation time 8528737654 ps
CPU time 31.27 seconds
Started Jul 07 05:33:22 PM PDT 24
Finished Jul 07 05:33:54 PM PDT 24
Peak memory 331928 kb
Host smart-76c5ed48-a8f5-44b0-bc91-a7995005ab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033618000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.3033618000
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.318427324
Short name T1206
Test name
Test status
Simulation time 27431713629 ps
CPU time 1154.97 seconds
Started Jul 07 05:33:32 PM PDT 24
Finished Jul 07 05:52:48 PM PDT 24
Peak memory 3443432 kb
Host smart-ecf23127-9d1d-40a8-94f0-1a87693b6a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318427324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.318427324
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.4143786568
Short name T1500
Test name
Test status
Simulation time 2143458629 ps
CPU time 24.04 seconds
Started Jul 07 05:33:23 PM PDT 24
Finished Jul 07 05:33:48 PM PDT 24
Peak memory 213244 kb
Host smart-2e86c656-f896-4281-87f8-ad4bbff3241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143786568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.4143786568
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.3454921170
Short name T1251
Test name
Test status
Simulation time 1749759784 ps
CPU time 4.3 seconds
Started Jul 07 05:33:24 PM PDT 24
Finished Jul 07 05:33:29 PM PDT 24
Peak memory 213552 kb
Host smart-c660d1bd-5bce-411c-87e9-15cad337fe5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454921170 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3454921170
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2100421721
Short name T1214
Test name
Test status
Simulation time 648685195 ps
CPU time 1.36 seconds
Started Jul 07 05:33:28 PM PDT 24
Finished Jul 07 05:33:29 PM PDT 24
Peak memory 205008 kb
Host smart-83bbb956-1dd1-47bd-8655-a28f3de5eb56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100421721 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2100421721
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.3852009503
Short name T1391
Test name
Test status
Simulation time 152818503 ps
CPU time 0.81 seconds
Started Jul 07 05:33:24 PM PDT 24
Finished Jul 07 05:33:26 PM PDT 24
Peak memory 204768 kb
Host smart-8c4ac37c-e75a-4b23-8cee-f1f9a78881af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852009503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.3852009503
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.360801083
Short name T929
Test name
Test status
Simulation time 5415176957 ps
CPU time 2.37 seconds
Started Jul 07 05:33:23 PM PDT 24
Finished Jul 07 05:33:27 PM PDT 24
Peak memory 205012 kb
Host smart-c75d5dcb-35dd-45b5-a6b8-7aec03fae6cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360801083 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.360801083
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.1727013898
Short name T1014
Test name
Test status
Simulation time 68928321 ps
CPU time 0.96 seconds
Started Jul 07 05:33:23 PM PDT 24
Finished Jul 07 05:33:25 PM PDT 24
Peak memory 204800 kb
Host smart-015a106c-ea22-49c7-9a69-c223c10d5390
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727013898 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.1727013898
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.263614382
Short name T612
Test name
Test status
Simulation time 8226838825 ps
CPU time 4.81 seconds
Started Jul 07 05:33:28 PM PDT 24
Finished Jul 07 05:33:33 PM PDT 24
Peak memory 205012 kb
Host smart-c036b497-0c0d-48ed-ac38-2a3c8395e89d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263614382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_intr_smoke.263614382
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.3950006650
Short name T1175
Test name
Test status
Simulation time 19345568312 ps
CPU time 377.7 seconds
Started Jul 07 05:33:26 PM PDT 24
Finished Jul 07 05:39:44 PM PDT 24
Peak memory 4701092 kb
Host smart-37f5feb3-2370-42fc-b29f-4ca9b09a7bc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950006650 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.3950006650
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.2138410228
Short name T1289
Test name
Test status
Simulation time 2509945010 ps
CPU time 9.96 seconds
Started Jul 07 05:33:18 PM PDT 24
Finished Jul 07 05:33:28 PM PDT 24
Peak memory 205092 kb
Host smart-a14a53a3-0935-407c-a81b-a45060b887f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138410228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2138410228
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.16144153
Short name T702
Test name
Test status
Simulation time 1891265873 ps
CPU time 32.52 seconds
Started Jul 07 05:33:22 PM PDT 24
Finished Jul 07 05:33:55 PM PDT 24
Peak memory 204976 kb
Host smart-85e7f814-5d8a-4fbe-a45b-abaaccdc9b81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16144153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stress_rd.16144153
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.3035404081
Short name T819
Test name
Test status
Simulation time 35229202359 ps
CPU time 10.56 seconds
Started Jul 07 05:33:26 PM PDT 24
Finished Jul 07 05:33:37 PM PDT 24
Peak memory 348624 kb
Host smart-93da1e73-aa8a-44c1-9ac7-04c613166b75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035404081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.3035404081
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.2747459753
Short name T1226
Test name
Test status
Simulation time 2146634012 ps
CPU time 41.15 seconds
Started Jul 07 05:33:23 PM PDT 24
Finished Jul 07 05:34:05 PM PDT 24
Peak memory 638684 kb
Host smart-e34294ac-daff-40bb-8bcb-e265335f07d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747459753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.2747459753
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.989504680
Short name T826
Test name
Test status
Simulation time 1424043478 ps
CPU time 8.29 seconds
Started Jul 07 05:33:24 PM PDT 24
Finished Jul 07 05:33:33 PM PDT 24
Peak memory 218696 kb
Host smart-e9f92983-2d65-47f5-b31b-10a01892deb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989504680 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_timeout.989504680
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.3669884096
Short name T707
Test name
Test status
Simulation time 135200046 ps
CPU time 2.94 seconds
Started Jul 07 05:33:27 PM PDT 24
Finished Jul 07 05:33:30 PM PDT 24
Peak memory 205032 kb
Host smart-77bdd78a-6759-4914-af9f-cbe1c0feb1b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669884096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.3669884096
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1583441958
Short name T195
Test name
Test status
Simulation time 41170989 ps
CPU time 0.62 seconds
Started Jul 07 05:33:31 PM PDT 24
Finished Jul 07 05:33:32 PM PDT 24
Peak memory 204568 kb
Host smart-18c0e680-799f-4f3e-ac1d-579edbd8446c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583441958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1583441958
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.4150659443
Short name T1208
Test name
Test status
Simulation time 152277442 ps
CPU time 1.32 seconds
Started Jul 07 05:33:29 PM PDT 24
Finished Jul 07 05:33:31 PM PDT 24
Peak memory 213288 kb
Host smart-52bcbec7-d41a-47af-9418-eabe65187a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150659443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.4150659443
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.359758869
Short name T915
Test name
Test status
Simulation time 987308721 ps
CPU time 4.93 seconds
Started Jul 07 05:33:22 PM PDT 24
Finished Jul 07 05:33:28 PM PDT 24
Peak memory 255872 kb
Host smart-c2007837-5cbf-465d-bb51-7679834a1575
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359758869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.359758869
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.3325548994
Short name T386
Test name
Test status
Simulation time 4189513150 ps
CPU time 63.36 seconds
Started Jul 07 05:33:30 PM PDT 24
Finished Jul 07 05:34:34 PM PDT 24
Peak memory 685648 kb
Host smart-0b5abbac-b3f0-457d-b871-473006919dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325548994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3325548994
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2535593957
Short name T610
Test name
Test status
Simulation time 3065920445 ps
CPU time 191.81 seconds
Started Jul 07 05:33:27 PM PDT 24
Finished Jul 07 05:36:39 PM PDT 24
Peak memory 806312 kb
Host smart-eb1a7a8e-97ee-494a-98c9-37997973c02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535593957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2535593957
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.529610261
Short name T1123
Test name
Test status
Simulation time 131491367 ps
CPU time 1.21 seconds
Started Jul 07 05:33:24 PM PDT 24
Finished Jul 07 05:33:26 PM PDT 24
Peak memory 204660 kb
Host smart-765894ab-a13a-41ad-8f3f-b1fbe28baae9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529610261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt
.529610261
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2578892894
Short name T751
Test name
Test status
Simulation time 227854701 ps
CPU time 10.11 seconds
Started Jul 07 05:33:26 PM PDT 24
Finished Jul 07 05:33:37 PM PDT 24
Peak memory 205072 kb
Host smart-3d6b45ce-e74d-44ad-917a-f920b73b6fc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578892894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2578892894
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.831513533
Short name T1053
Test name
Test status
Simulation time 15430357131 ps
CPU time 110.03 seconds
Started Jul 07 05:33:27 PM PDT 24
Finished Jul 07 05:35:17 PM PDT 24
Peak memory 1136364 kb
Host smart-7f996deb-4302-4700-9e54-6d1baa8ce0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831513533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.831513533
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3139973972
Short name T997
Test name
Test status
Simulation time 908987628 ps
CPU time 6.96 seconds
Started Jul 07 05:33:36 PM PDT 24
Finished Jul 07 05:33:43 PM PDT 24
Peak memory 204992 kb
Host smart-1454a141-1611-4081-8347-ef0de9b71a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139973972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3139973972
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.364283343
Short name T1450
Test name
Test status
Simulation time 1423589198 ps
CPU time 23.23 seconds
Started Jul 07 05:33:35 PM PDT 24
Finished Jul 07 05:33:58 PM PDT 24
Peak memory 366384 kb
Host smart-d7bd6be8-1255-4ec1-8140-0713802b75e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364283343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.364283343
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.2430849411
Short name T169
Test name
Test status
Simulation time 16349505 ps
CPU time 0.69 seconds
Started Jul 07 05:33:25 PM PDT 24
Finished Jul 07 05:33:27 PM PDT 24
Peak memory 204576 kb
Host smart-4ebd8c6c-fee5-4bfa-beea-29e2f815117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430849411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.2430849411
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1324718562
Short name T1212
Test name
Test status
Simulation time 6838491777 ps
CPU time 57.84 seconds
Started Jul 07 05:33:28 PM PDT 24
Finished Jul 07 05:34:26 PM PDT 24
Peak memory 234108 kb
Host smart-b1f821e6-585f-4a24-b6e6-4030bd662b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324718562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1324718562
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.2124958798
Short name T528
Test name
Test status
Simulation time 24312766846 ps
CPU time 313.7 seconds
Started Jul 07 05:33:29 PM PDT 24
Finished Jul 07 05:38:43 PM PDT 24
Peak memory 205076 kb
Host smart-8a3120cc-ec80-468e-b36e-19d4b975e025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124958798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.2124958798
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.113947175
Short name T1403
Test name
Test status
Simulation time 1598171276 ps
CPU time 79.15 seconds
Started Jul 07 05:33:23 PM PDT 24
Finished Jul 07 05:34:43 PM PDT 24
Peak memory 380496 kb
Host smart-5260aeb3-e664-41d5-ae4a-f14af417e836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113947175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.113947175
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.1673507738
Short name T415
Test name
Test status
Simulation time 3260037212 ps
CPU time 13.17 seconds
Started Jul 07 05:33:28 PM PDT 24
Finished Jul 07 05:33:43 PM PDT 24
Peak memory 229532 kb
Host smart-8e59a0a9-b6ea-4991-8263-af9879c72771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673507738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.1673507738
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2856019685
Short name T1342
Test name
Test status
Simulation time 3242618771 ps
CPU time 3.97 seconds
Started Jul 07 05:33:32 PM PDT 24
Finished Jul 07 05:33:36 PM PDT 24
Peak memory 213548 kb
Host smart-aebc04ce-ba3f-4094-a9ae-1dc65359fe83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856019685 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2856019685
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.1465726232
Short name T179
Test name
Test status
Simulation time 439112705 ps
CPU time 1.46 seconds
Started Jul 07 05:33:32 PM PDT 24
Finished Jul 07 05:33:34 PM PDT 24
Peak memory 204984 kb
Host smart-1f3d11df-b59a-45cd-83c8-265337183b22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465726232 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.1465726232
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1277576074
Short name T1411
Test name
Test status
Simulation time 1108064125 ps
CPU time 1.33 seconds
Started Jul 07 05:33:34 PM PDT 24
Finished Jul 07 05:33:36 PM PDT 24
Peak memory 205004 kb
Host smart-37df2eb6-132d-4ed1-9a23-4646ecbf59df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277576074 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1277576074
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.3076526756
Short name T489
Test name
Test status
Simulation time 619831326 ps
CPU time 1.48 seconds
Started Jul 07 05:33:31 PM PDT 24
Finished Jul 07 05:33:33 PM PDT 24
Peak memory 204728 kb
Host smart-5cdfdc27-0b1c-4f07-8db2-7deaaf0b321f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076526756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.3076526756
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.1654244063
Short name T1481
Test name
Test status
Simulation time 398012860 ps
CPU time 1.05 seconds
Started Jul 07 05:33:32 PM PDT 24
Finished Jul 07 05:33:33 PM PDT 24
Peak memory 204776 kb
Host smart-2f2df2ed-1f8c-46bd-9b51-a0bb0bc69bba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654244063 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.1654244063
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.2385309671
Short name T1408
Test name
Test status
Simulation time 6282344676 ps
CPU time 7.83 seconds
Started Jul 07 05:33:28 PM PDT 24
Finished Jul 07 05:33:37 PM PDT 24
Peak memory 205384 kb
Host smart-d592f88f-4296-4eb3-9e4f-34093bd4cda9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385309671 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.2385309671
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.74556253
Short name T299
Test name
Test status
Simulation time 7791681188 ps
CPU time 9.51 seconds
Started Jul 07 05:33:29 PM PDT 24
Finished Jul 07 05:33:40 PM PDT 24
Peak memory 205048 kb
Host smart-f6de63ec-a21c-4c7f-91f8-30da02b763da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74556253 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.74556253
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.685327328
Short name T1301
Test name
Test status
Simulation time 856974716 ps
CPU time 36.27 seconds
Started Jul 07 05:33:28 PM PDT 24
Finished Jul 07 05:34:06 PM PDT 24
Peak memory 204844 kb
Host smart-14373b90-5288-4359-9f39-6e66e099287a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685327328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_targ
et_smoke.685327328
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.1256567542
Short name T1065
Test name
Test status
Simulation time 12214121477 ps
CPU time 14.51 seconds
Started Jul 07 05:33:26 PM PDT 24
Finished Jul 07 05:33:41 PM PDT 24
Peak memory 211120 kb
Host smart-c3dc08bc-5727-469b-beff-8c1a64518d0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256567542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.1256567542
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.505339531
Short name T1319
Test name
Test status
Simulation time 42249846451 ps
CPU time 369.48 seconds
Started Jul 07 05:33:29 PM PDT 24
Finished Jul 07 05:39:39 PM PDT 24
Peak memory 3473484 kb
Host smart-70e0e23e-bda4-4eb7-98a8-3478b19921c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505339531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_wr.505339531
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.2287709596
Short name T110
Test name
Test status
Simulation time 4120991313 ps
CPU time 5.74 seconds
Started Jul 07 05:33:29 PM PDT 24
Finished Jul 07 05:33:36 PM PDT 24
Peak memory 245528 kb
Host smart-fe7dc566-b237-42c6-96ad-906d439937cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287709596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.2287709596
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1564663320
Short name T1060
Test name
Test status
Simulation time 1511532947 ps
CPU time 7.87 seconds
Started Jul 07 05:33:29 PM PDT 24
Finished Jul 07 05:33:38 PM PDT 24
Peak memory 221208 kb
Host smart-4c61cbe4-2cbd-47c3-8966-60bd0a8196ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564663320 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1564663320
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.2747269451
Short name T627
Test name
Test status
Simulation time 59314225 ps
CPU time 1.46 seconds
Started Jul 07 05:33:35 PM PDT 24
Finished Jul 07 05:33:36 PM PDT 24
Peak memory 205064 kb
Host smart-cd232e1d-25b7-44d2-9bce-f492af9edc45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747269451 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.2747269451
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.2647109615
Short name T546
Test name
Test status
Simulation time 43898191 ps
CPU time 0.66 seconds
Started Jul 07 05:33:38 PM PDT 24
Finished Jul 07 05:33:39 PM PDT 24
Peak memory 204568 kb
Host smart-9dd71ad9-0985-40e3-9973-140d70282a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647109615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2647109615
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.3228781059
Short name T927
Test name
Test status
Simulation time 170818314 ps
CPU time 2.7 seconds
Started Jul 07 05:33:36 PM PDT 24
Finished Jul 07 05:33:39 PM PDT 24
Peak memory 230696 kb
Host smart-03c58860-609e-4b05-a17d-f4b07017c58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228781059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3228781059
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.904816435
Short name T361
Test name
Test status
Simulation time 941308176 ps
CPU time 12.09 seconds
Started Jul 07 05:33:38 PM PDT 24
Finished Jul 07 05:33:51 PM PDT 24
Peak memory 250208 kb
Host smart-caaa07b1-e19d-403a-b9fa-6840b0e2cf19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904816435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty
.904816435
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.3347640309
Short name T1427
Test name
Test status
Simulation time 2102286745 ps
CPU time 51.09 seconds
Started Jul 07 05:33:34 PM PDT 24
Finished Jul 07 05:34:25 PM PDT 24
Peak memory 529568 kb
Host smart-b7381f2b-138f-4db2-b394-50068186e0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347640309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.3347640309
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2830189422
Short name T1149
Test name
Test status
Simulation time 9828610620 ps
CPU time 90.66 seconds
Started Jul 07 05:33:36 PM PDT 24
Finished Jul 07 05:35:07 PM PDT 24
Peak memory 781188 kb
Host smart-bac7c69e-30c3-4bd2-aca4-8e9330d0dfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830189422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2830189422
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3036539001
Short name T1434
Test name
Test status
Simulation time 269714508 ps
CPU time 1.03 seconds
Started Jul 07 05:33:34 PM PDT 24
Finished Jul 07 05:33:36 PM PDT 24
Peak memory 204708 kb
Host smart-99a8c48c-8f7f-40e4-894d-20feb5f453c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036539001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3036539001
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.605391005
Short name T1357
Test name
Test status
Simulation time 3339041614 ps
CPU time 5.91 seconds
Started Jul 07 05:33:34 PM PDT 24
Finished Jul 07 05:33:40 PM PDT 24
Peak memory 205016 kb
Host smart-e4decbdd-5515-49ce-b591-c5ef76684d91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605391005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.605391005
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3543702911
Short name T1335
Test name
Test status
Simulation time 3769355653 ps
CPU time 60.94 seconds
Started Jul 07 05:33:36 PM PDT 24
Finished Jul 07 05:34:38 PM PDT 24
Peak memory 849916 kb
Host smart-28254c96-940e-4df2-a56a-c3225139ce52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543702911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3543702911
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2539441132
Short name T1181
Test name
Test status
Simulation time 1915404690 ps
CPU time 4.24 seconds
Started Jul 07 05:33:37 PM PDT 24
Finished Jul 07 05:33:42 PM PDT 24
Peak memory 205316 kb
Host smart-a46b0341-de49-4552-a8ba-229228baa8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539441132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2539441132
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.1489838447
Short name T125
Test name
Test status
Simulation time 9264557936 ps
CPU time 91.26 seconds
Started Jul 07 05:33:40 PM PDT 24
Finished Jul 07 05:35:12 PM PDT 24
Peak memory 306660 kb
Host smart-763522ca-9bda-4fd6-98d9-3ca655772c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489838447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.1489838447
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.196350641
Short name T998
Test name
Test status
Simulation time 18977989 ps
CPU time 0.71 seconds
Started Jul 07 05:33:35 PM PDT 24
Finished Jul 07 05:33:36 PM PDT 24
Peak memory 205016 kb
Host smart-81dc957a-7966-4df7-81e2-87b546b91f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196350641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.196350641
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.622041047
Short name T1043
Test name
Test status
Simulation time 12554560361 ps
CPU time 117.83 seconds
Started Jul 07 05:33:33 PM PDT 24
Finished Jul 07 05:35:31 PM PDT 24
Peak memory 694960 kb
Host smart-71f03fc9-0486-4fbc-b75f-b77065af5570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622041047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.622041047
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.3178560267
Short name T1381
Test name
Test status
Simulation time 162301971 ps
CPU time 2.27 seconds
Started Jul 07 05:33:36 PM PDT 24
Finished Jul 07 05:33:39 PM PDT 24
Peak memory 205496 kb
Host smart-79a727d7-a085-4954-880c-5d1f1969e2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178560267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.3178560267
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.199704273
Short name T1447
Test name
Test status
Simulation time 30843008543 ps
CPU time 34.55 seconds
Started Jul 07 05:33:29 PM PDT 24
Finished Jul 07 05:34:04 PM PDT 24
Peak memory 401660 kb
Host smart-a212258c-15e5-42f6-b3e9-3a4d7b8fc448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199704273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.199704273
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.801054900
Short name T235
Test name
Test status
Simulation time 25970626977 ps
CPU time 553.16 seconds
Started Jul 07 05:33:33 PM PDT 24
Finished Jul 07 05:42:47 PM PDT 24
Peak memory 1550376 kb
Host smart-573d19c3-23f6-42ed-923e-d4990a68368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801054900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.801054900
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.536864338
Short name T574
Test name
Test status
Simulation time 3293591988 ps
CPU time 37.58 seconds
Started Jul 07 05:33:35 PM PDT 24
Finished Jul 07 05:34:13 PM PDT 24
Peak memory 213116 kb
Host smart-7849e498-4a4b-4c94-a4d2-5ff7a537fb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536864338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.536864338
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.1304691723
Short name T925
Test name
Test status
Simulation time 1957070291 ps
CPU time 2.7 seconds
Started Jul 07 05:33:44 PM PDT 24
Finished Jul 07 05:33:48 PM PDT 24
Peak memory 205064 kb
Host smart-43fc6891-0a9d-4247-9c1c-cb917922a772
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304691723 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1304691723
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.2164587064
Short name T837
Test name
Test status
Simulation time 165068244 ps
CPU time 1.04 seconds
Started Jul 07 05:33:37 PM PDT 24
Finished Jul 07 05:33:38 PM PDT 24
Peak memory 204772 kb
Host smart-c8765a2f-fe93-4bba-b49e-ec4c15138078
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164587064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.2164587064
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.656393066
Short name T525
Test name
Test status
Simulation time 543868463 ps
CPU time 1.29 seconds
Started Jul 07 05:33:41 PM PDT 24
Finished Jul 07 05:33:43 PM PDT 24
Peak memory 205036 kb
Host smart-bfa4b30b-591a-44a7-b3d4-9c0b69cd355f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656393066 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_tx.656393066
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.2337438835
Short name T261
Test name
Test status
Simulation time 543571444 ps
CPU time 2.76 seconds
Started Jul 07 05:33:41 PM PDT 24
Finished Jul 07 05:33:44 PM PDT 24
Peak memory 205024 kb
Host smart-236f1eb1-5ed1-4b20-899b-1b536bacde83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337438835 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.2337438835
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.1941677140
Short name T901
Test name
Test status
Simulation time 119336827 ps
CPU time 0.89 seconds
Started Jul 07 05:33:41 PM PDT 24
Finished Jul 07 05:33:43 PM PDT 24
Peak memory 204840 kb
Host smart-47d16b83-0e46-4a5b-8491-1d8883242a05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941677140 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.1941677140
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.508406362
Short name T708
Test name
Test status
Simulation time 344479142 ps
CPU time 3.25 seconds
Started Jul 07 05:33:43 PM PDT 24
Finished Jul 07 05:33:47 PM PDT 24
Peak memory 205072 kb
Host smart-ee9d49ab-624c-4f3c-9fc3-aa8b7a82a2d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508406362 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_hrst.508406362
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.1643975601
Short name T292
Test name
Test status
Simulation time 1794132491 ps
CPU time 6.89 seconds
Started Jul 07 05:33:35 PM PDT 24
Finished Jul 07 05:33:42 PM PDT 24
Peak memory 211444 kb
Host smart-8a18e671-f111-4e22-a450-6e336936ffbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643975601 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.1643975601
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2219599983
Short name T608
Test name
Test status
Simulation time 9170861903 ps
CPU time 30.8 seconds
Started Jul 07 05:33:36 PM PDT 24
Finished Jul 07 05:34:07 PM PDT 24
Peak memory 623308 kb
Host smart-dffa1a6b-bd29-4180-b42e-1d73d4a6880e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219599983 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2219599983
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.3630229166
Short name T1344
Test name
Test status
Simulation time 2318886694 ps
CPU time 16.78 seconds
Started Jul 07 05:33:36 PM PDT 24
Finished Jul 07 05:33:54 PM PDT 24
Peak memory 205004 kb
Host smart-9fa5e25a-a167-4a5e-b85d-5b82594312b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630229166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.3630229166
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.3958843153
Short name T963
Test name
Test status
Simulation time 1929519078 ps
CPU time 20.47 seconds
Started Jul 07 05:33:37 PM PDT 24
Finished Jul 07 05:33:58 PM PDT 24
Peak memory 204948 kb
Host smart-f0d87819-5897-424d-a873-c2885aedcef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958843153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.3958843153
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.2981060838
Short name T380
Test name
Test status
Simulation time 48191298284 ps
CPU time 141.52 seconds
Started Jul 07 05:33:37 PM PDT 24
Finished Jul 07 05:35:59 PM PDT 24
Peak memory 1866360 kb
Host smart-65ad2378-08a4-4622-8125-229260c99023
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981060838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.2981060838
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.530021786
Short name T12
Test name
Test status
Simulation time 3164221784 ps
CPU time 22.56 seconds
Started Jul 07 05:33:39 PM PDT 24
Finished Jul 07 05:34:02 PM PDT 24
Peak memory 286116 kb
Host smart-bbefaf3c-51ff-4da8-962f-4cc506dfa24d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530021786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_ta
rget_stretch.530021786
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3746595510
Short name T1267
Test name
Test status
Simulation time 5212391855 ps
CPU time 7.56 seconds
Started Jul 07 05:33:35 PM PDT 24
Finished Jul 07 05:33:42 PM PDT 24
Peak memory 205056 kb
Host smart-e0ce03fd-a914-4b24-91a1-25956246ae49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746595510 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3746595510
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.1215561915
Short name T743
Test name
Test status
Simulation time 83175439 ps
CPU time 1.83 seconds
Started Jul 07 05:33:41 PM PDT 24
Finished Jul 07 05:33:43 PM PDT 24
Peak memory 204992 kb
Host smart-15c324b5-f3e8-4241-8e87-64c5f76b88a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215561915 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.1215561915
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.3743394376
Short name T603
Test name
Test status
Simulation time 20479665 ps
CPU time 0.62 seconds
Started Jul 07 05:33:47 PM PDT 24
Finished Jul 07 05:33:49 PM PDT 24
Peak memory 204624 kb
Host smart-7ac2d16f-21d2-4106-939c-ddf68f06c818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743394376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.3743394376
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.2961809594
Short name T49
Test name
Test status
Simulation time 1122470192 ps
CPU time 3.64 seconds
Started Jul 07 05:33:45 PM PDT 24
Finished Jul 07 05:33:49 PM PDT 24
Peak memory 231088 kb
Host smart-3f0c71de-9042-47db-90b7-503099e21ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961809594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.2961809594
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3731721610
Short name T1491
Test name
Test status
Simulation time 222535591 ps
CPU time 3.93 seconds
Started Jul 07 05:33:41 PM PDT 24
Finished Jul 07 05:33:46 PM PDT 24
Peak memory 247636 kb
Host smart-c4bb955e-fba8-49ce-aec4-204f975ce5a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731721610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3731721610
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.1548516985
Short name T153
Test name
Test status
Simulation time 2019571276 ps
CPU time 32.27 seconds
Started Jul 07 05:33:41 PM PDT 24
Finished Jul 07 05:34:14 PM PDT 24
Peak memory 429296 kb
Host smart-eff456b1-ad0e-43cb-987a-0c92a3a77944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548516985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.1548516985
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1557639774
Short name T1367
Test name
Test status
Simulation time 10559063993 ps
CPU time 96.13 seconds
Started Jul 07 05:33:44 PM PDT 24
Finished Jul 07 05:35:21 PM PDT 24
Peak memory 840212 kb
Host smart-4c348917-e100-4ac0-8238-090c1b0957da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557639774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1557639774
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.481321306
Short name T1122
Test name
Test status
Simulation time 142143912 ps
CPU time 1.25 seconds
Started Jul 07 05:33:40 PM PDT 24
Finished Jul 07 05:33:41 PM PDT 24
Peak memory 204764 kb
Host smart-8c03d291-06c3-47eb-bd9a-9948e8a4eea8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481321306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt
.481321306
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.3173496826
Short name T1311
Test name
Test status
Simulation time 201899652 ps
CPU time 5.5 seconds
Started Jul 07 05:33:41 PM PDT 24
Finished Jul 07 05:33:47 PM PDT 24
Peak memory 240424 kb
Host smart-6807ad1b-afbb-4a07-9e29-00e3528d60bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173496826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
3173496826
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.845482162
Short name T1099
Test name
Test status
Simulation time 21670929874 ps
CPU time 159.25 seconds
Started Jul 07 05:33:38 PM PDT 24
Finished Jul 07 05:36:18 PM PDT 24
Peak memory 817824 kb
Host smart-2df1685d-ff5e-4ca8-832e-efacea208dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845482162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.845482162
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.1673387475
Short name T1495
Test name
Test status
Simulation time 1709051884 ps
CPU time 4.58 seconds
Started Jul 07 05:33:46 PM PDT 24
Finished Jul 07 05:33:51 PM PDT 24
Peak memory 204972 kb
Host smart-f461e02d-66d8-4059-ab28-4d8a0bbcb9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673387475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.1673387475
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.513397082
Short name T1041
Test name
Test status
Simulation time 20557500289 ps
CPU time 74.5 seconds
Started Jul 07 05:33:48 PM PDT 24
Finished Jul 07 05:35:03 PM PDT 24
Peak memory 398460 kb
Host smart-eca0286a-800f-4005-81ee-b1ba773abb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513397082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.513397082
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.2798536776
Short name T135
Test name
Test status
Simulation time 29126752 ps
CPU time 0.71 seconds
Started Jul 07 05:33:38 PM PDT 24
Finished Jul 07 05:33:39 PM PDT 24
Peak memory 204676 kb
Host smart-3b8523de-ef51-4adf-8deb-3acf4abfbfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798536776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2798536776
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2354924610
Short name T7
Test name
Test status
Simulation time 6437681618 ps
CPU time 46.33 seconds
Started Jul 07 05:33:45 PM PDT 24
Finished Jul 07 05:34:32 PM PDT 24
Peak memory 234664 kb
Host smart-4738b1f1-537f-4eb9-80c7-56f7336661d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354924610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2354924610
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.143682341
Short name T1139
Test name
Test status
Simulation time 226633452 ps
CPU time 3.15 seconds
Started Jul 07 05:33:45 PM PDT 24
Finished Jul 07 05:33:48 PM PDT 24
Peak memory 219332 kb
Host smart-1e00c252-7c71-453a-b24a-5e91c7e2fbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143682341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.143682341
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2808051834
Short name T1458
Test name
Test status
Simulation time 1612219738 ps
CPU time 29.06 seconds
Started Jul 07 05:33:44 PM PDT 24
Finished Jul 07 05:34:14 PM PDT 24
Peak memory 380180 kb
Host smart-e7f1e777-0ded-40b0-8d44-18e5aae543a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808051834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2808051834
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.278044175
Short name T57
Test name
Test status
Simulation time 12560056070 ps
CPU time 596.19 seconds
Started Jul 07 05:33:43 PM PDT 24
Finished Jul 07 05:43:40 PM PDT 24
Peak memory 2821256 kb
Host smart-3979cdf8-e1ca-463e-a1f9-9970eb74be22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278044175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.278044175
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.2362180899
Short name T1504
Test name
Test status
Simulation time 3160751817 ps
CPU time 16.09 seconds
Started Jul 07 05:33:40 PM PDT 24
Finished Jul 07 05:33:56 PM PDT 24
Peak memory 221208 kb
Host smart-da66db46-8314-44e8-b5cc-3e068a09bfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362180899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2362180899
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.992411630
Short name T336
Test name
Test status
Simulation time 1646593316 ps
CPU time 4.85 seconds
Started Jul 07 05:33:45 PM PDT 24
Finished Jul 07 05:33:50 PM PDT 24
Peak memory 205056 kb
Host smart-b06d85ab-714e-44da-8e6a-3a1f558a210d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992411630 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.992411630
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1573239182
Short name T1051
Test name
Test status
Simulation time 337078533 ps
CPU time 0.93 seconds
Started Jul 07 05:33:44 PM PDT 24
Finished Jul 07 05:33:46 PM PDT 24
Peak memory 204784 kb
Host smart-85a83690-cf9b-4b04-a8f6-7740838a2097
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573239182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.1573239182
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.182709886
Short name T21
Test name
Test status
Simulation time 407796150 ps
CPU time 1.6 seconds
Started Jul 07 05:33:45 PM PDT 24
Finished Jul 07 05:33:47 PM PDT 24
Peak memory 209496 kb
Host smart-8e3c37c5-acb4-4572-8bf0-7a526dd3f6d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182709886 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_tx.182709886
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.3525427092
Short name T381
Test name
Test status
Simulation time 969127635 ps
CPU time 2.8 seconds
Started Jul 07 05:33:45 PM PDT 24
Finished Jul 07 05:33:49 PM PDT 24
Peak memory 204996 kb
Host smart-2f4e7aa7-abce-4f4a-bb41-f73f9a181550
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525427092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.3525427092
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.3079101710
Short name T551
Test name
Test status
Simulation time 133418897 ps
CPU time 1.25 seconds
Started Jul 07 05:33:48 PM PDT 24
Finished Jul 07 05:33:50 PM PDT 24
Peak memory 204768 kb
Host smart-e0c505a6-cc0e-45c0-8e24-de9f70b7203c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079101710 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.3079101710
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.3860798493
Short name T126
Test name
Test status
Simulation time 683226613 ps
CPU time 2.39 seconds
Started Jul 07 05:33:51 PM PDT 24
Finished Jul 07 05:33:54 PM PDT 24
Peak memory 205068 kb
Host smart-4c70a2a4-8c55-4353-add7-12b9f352a1f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860798493 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.3860798493
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.2133013712
Short name T408
Test name
Test status
Simulation time 4700742475 ps
CPU time 5.71 seconds
Started Jul 07 05:33:41 PM PDT 24
Finished Jul 07 05:33:48 PM PDT 24
Peak memory 210264 kb
Host smart-f7da8568-d257-419f-b3a8-a92a3e46824d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133013712 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.2133013712
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.3906712114
Short name T1103
Test name
Test status
Simulation time 13941588615 ps
CPU time 12.45 seconds
Started Jul 07 05:33:45 PM PDT 24
Finished Jul 07 05:33:58 PM PDT 24
Peak memory 458100 kb
Host smart-3d4e33c4-d500-4bfe-8e28-9e9a23cff305
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906712114 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.3906712114
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.1104463426
Short name T90
Test name
Test status
Simulation time 1918072427 ps
CPU time 13.85 seconds
Started Jul 07 05:33:44 PM PDT 24
Finished Jul 07 05:33:59 PM PDT 24
Peak memory 204944 kb
Host smart-569bd456-c397-48f5-b11a-c701420a0f90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104463426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.1104463426
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1869259906
Short name T582
Test name
Test status
Simulation time 263363818 ps
CPU time 11.2 seconds
Started Jul 07 05:33:44 PM PDT 24
Finished Jul 07 05:33:56 PM PDT 24
Peak memory 204992 kb
Host smart-ccadd2ec-3051-442c-a6ff-495ef680a054
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869259906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1869259906
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.1981296678
Short name T500
Test name
Test status
Simulation time 61252064965 ps
CPU time 276.89 seconds
Started Jul 07 05:33:44 PM PDT 24
Finished Jul 07 05:38:21 PM PDT 24
Peak memory 2552492 kb
Host smart-c89b0497-aefe-41de-bf29-093d484f6af5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981296678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.1981296678
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.645309464
Short name T843
Test name
Test status
Simulation time 1318963858 ps
CPU time 2.37 seconds
Started Jul 07 05:33:42 PM PDT 24
Finished Jul 07 05:33:45 PM PDT 24
Peak memory 205064 kb
Host smart-2ae92f4c-6a6a-4f13-9b1a-a20c5e183117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645309464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_ta
rget_stretch.645309464
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.2230235422
Short name T70
Test name
Test status
Simulation time 1576178755 ps
CPU time 7.98 seconds
Started Jul 07 05:33:43 PM PDT 24
Finished Jul 07 05:33:51 PM PDT 24
Peak memory 221308 kb
Host smart-2b11a14f-3382-4fd9-9b04-864f696e8d8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230235422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.2230235422
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.2583523120
Short name T368
Test name
Test status
Simulation time 153589655 ps
CPU time 3.25 seconds
Started Jul 07 05:33:49 PM PDT 24
Finished Jul 07 05:33:52 PM PDT 24
Peak memory 205080 kb
Host smart-31f2469e-5e87-4506-acb7-b254128b88d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583523120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.2583523120
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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