Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.87	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	8	52	86.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	8	52	86.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	556858	1			T1	2		T2	1		T3	2
all_values[1]	556858	1			T1	2		T2	1		T3	2
all_values[2]	556858	1			T1	2		T2	1		T3	2
all_values[3]	556858	1			T1	2		T2	1		T3	2
all_values[4]	556858	1			T1	2		T2	1		T3	2
all_values[5]	556858	1			T1	2		T2	1		T3	2
all_values[6]	556858	1			T1	2		T2	1		T3	2
all_values[7]	556858	1			T1	2		T2	1		T3	2
all_values[8]	556858	1			T1	2		T2	1		T3	2
all_values[9]	556858	1			T1	2		T2	1		T3	2
all_values[10]	556858	1			T1	2		T2	1		T3	2
all_values[11]	556858	1			T1	2		T2	1		T3	2
all_values[12]	556858	1			T1	2		T2	1		T3	2
all_values[13]	556858	1			T1	2		T2	1		T3	2
all_values[14]	556858	1			T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6822060

1

T1

26

T2

15

T3

26

auto[1]

1530810

1

T1

4

T3

4

T4

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8260121

1

T1

30

T2

15

T3

30

auto[1]

92749

1

T29

88522

T161

106

T162

96

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	8	52	86.67	8

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3] , all_values[4] , all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	4
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	55672	1			T2	1		T6	53		T9	5
all_values[0]	auto[0]	auto[1]	303	1			T29	133		T161	4		T162	3
all_values[0]	auto[1]	auto[0]	494989	1			T1	2		T3	2		T4	2
all_values[0]	auto[1]	auto[1]	5894	1			T29	5764		T161	3		T162	3
all_values[1]	auto[0]	auto[0]	550185	1			T1	2		T2	1		T3	2
all_values[1]	auto[0]	auto[1]	6059	1			T29	5895		T161	6		T162	5
all_values[1]	auto[1]	auto[0]	494	1			T14	2		T262	1		T263	1
all_values[1]	auto[1]	auto[1]	120	1			T29	6		T161	2		T162	3
all_values[2]	auto[0]	auto[0]	550470	1			T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	6075	1			T29	5898		T161	4		T264	2
all_values[2]	auto[1]	auto[0]	188	1			T10	1		T46	1		T51	1
all_values[2]	auto[1]	auto[1]	125	1			T29	4		T161	4		T264	1
all_values[3]	auto[0]	auto[0]	550660	1			T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	6060	1			T29	5899		T161	4		T162	4
all_values[3]	auto[1]	auto[1]	138	1			T29	3		T161	3		T162	3
all_values[4]	auto[0]	auto[0]	550670	1			T1	2		T2	1		T3	2
all_values[4]	auto[0]	auto[1]	6065	1			T29	5901		T161	3		T162	6
all_values[4]	auto[1]	auto[1]	123	1			T29	1		T161	3		T162	2
all_values[5]	auto[0]	auto[0]	550673	1			T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	6038	1			T29	5901		T161	6		T162	5
all_values[5]	auto[1]	auto[1]	147	1			T29	1		T161	2		T162	3
all_values[6]	auto[0]	auto[0]	550664	1			T1	2		T2	1		T3	2
all_values[6]	auto[0]	auto[1]	6064	1			T29	5896		T161	3		T162	3
all_values[6]	auto[1]	auto[1]	130	1			T29	6		T161	5		T162	4
all_values[7]	auto[0]	auto[0]	533646	1			T1	2		T2	1		T3	2
all_values[7]	auto[0]	auto[1]	5747	1			T29	5601		T161	2		T162	8
all_values[7]	auto[1]	auto[0]	17033	1			T6	97		T9	52		T14	80
all_values[7]	auto[1]	auto[1]	432	1			T29	300		T161	3		T130	3
all_values[8]	auto[0]	auto[0]	550686	1			T1	2		T2	1		T3	2
all_values[8]	auto[0]	auto[1]	6026	1			T29	5897		T161	7		T162	6
all_values[8]	auto[1]	auto[1]	146	1			T29	5		T161	1		T162	1
all_values[9]	auto[0]	auto[0]	100399	1			T1	2		T2	1		T3	2
all_values[9]	auto[0]	auto[1]	1021	1			T29	867		T161	8		T162	1
all_values[9]	auto[1]	auto[0]	450286	1			T6	14113		T9	23		T13	1
all_values[9]	auto[1]	auto[1]	5152	1			T29	5035		T162	3		T130	3
all_values[10]	auto[0]	auto[0]	550659	1			T1	2		T2	1		T3	2
all_values[10]	auto[0]	auto[1]	6076	1			T29	5899		T161	4		T162	4
all_values[10]	auto[1]	auto[1]	123	1			T29	3		T161	4		T162	1
all_values[11]	auto[0]	auto[0]	1806	1			T2	1		T6	9		T9	4
all_values[11]	auto[0]	auto[1]	183	1			T29	32		T161	4		T162	5
all_values[11]	auto[1]	auto[0]	548884	1			T1	2		T3	2		T4	2
all_values[11]	auto[1]	auto[1]	5985	1			T29	5869		T161	3		T162	2
all_values[12]	auto[0]	auto[0]	550638	1			T1	2		T2	1		T3	2
all_values[12]	auto[0]	auto[1]	6059	1			T29	5899		T161	2		T162	5
all_values[12]	auto[1]	auto[0]	58	1			T10	1		T51	1		T66	1
all_values[12]	auto[1]	auto[1]	103	1			T29	3		T161	1		T162	2
all_values[13]	auto[0]	auto[0]	550676	1			T1	2		T2	1		T3	2
all_values[13]	auto[0]	auto[1]	6055	1			T29	5897		T161	5		T162	4
all_values[13]	auto[1]	auto[1]	127	1			T29	5		T161	2		T162	2
all_values[14]	auto[0]	auto[0]	550685	1			T1	2		T2	1		T3	2
all_values[14]	auto[0]	auto[1]	6040	1			T29	5897		T161	2		T162	4
all_values[14]	auto[1]	auto[1]	133	1			T29	5		T161	6		T162	4