Summary for Variable cp_acq_fifo_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_acq_fifo_size
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
not_empty |
61732410 |
1 |
|
|
T1 |
1302 |
|
T3 |
26 |
|
T4 |
1179 |
empty |
36156401 |
1 |
|
|
T1 |
508 |
|
T3 |
41 |
|
T6 |
996 |
Summary for Variable cp_host_mode_stretch
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_host_mode_stretch
Excluded/Illegal bins
NAME | COUNT | STATUS |
unused |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
stretch |
23783209 |
1 |
|
|
T6 |
996 |
|
T9 |
77673 |
|
T14 |
62105 |
Summary for Variable cp_target_scl_stretch_addr_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_target_scl_stretch_addr_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
addr_write_byte_stretch |
340951 |
1 |
|
|
T4 |
36 |
|
T10 |
27 |
|
T52 |
7978 |
Summary for Variable cp_tx_fifo_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_tx_fifo_size
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
not_empty |
4009493 |
1 |
|
|
T1 |
20 |
|
T3 |
67 |
|
T44 |
48 |
empty |
93938529 |
1 |
|
|
T1 |
1790 |
|
T4 |
1191 |
|
T5 |
42 |
Summary for Cross cp_target_scl_stretch_read
Samples crossed: cp_acq_fifo_size cp_tx_fifo_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
User Defined Cross Bins |
2 |
0 |
2 |
100.00 |
|
Automatically Generated Cross Bins for cp_target_scl_stretch_read
Bins
cp_acq_fifo_size | cp_tx_fifo_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
empty |
not_empty |
2164 |
1 |
|
|
T3 |
41 |
|
T53 |
54 |
|
T54 |
15 |
empty |
empty |
368754 |
1 |
|
|
T1 |
508 |
|
T95 |
725 |
|
T249 |
815 |
User Defined Cross Bins for cp_target_scl_stretch_read
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_byte_stretch |
148430 |
1 |
|
|
T1 |
933 |
|
T5 |
42 |
|
T47 |
438 |
scl_stretch_read_request |
4155068 |
1 |
|
|
T1 |
953 |
|
T3 |
26 |
|
T5 |
42 |