Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	556858	1			T1	2		T2	1		T3	2
all_pins[1]	556858	1			T1	2		T2	1		T3	2
all_pins[2]	556858	1			T1	2		T2	1		T3	2
all_pins[3]	556858	1			T1	2		T2	1		T3	2
all_pins[4]	556858	1			T1	2		T2	1		T3	2
all_pins[5]	556858	1			T1	2		T2	1		T3	2
all_pins[6]	556858	1			T1	2		T2	1		T3	2
all_pins[7]	556858	1			T1	2		T2	1		T3	2
all_pins[8]	556858	1			T1	2		T2	1		T3	2
all_pins[9]	556858	1			T1	2		T2	1		T3	2
all_pins[10]	556858	1			T1	2		T2	1		T3	2
all_pins[11]	556858	1			T1	2		T2	1		T3	2
all_pins[12]	556858	1			T1	2		T2	1		T3	2
all_pins[13]	556858	1			T1	2		T2	1		T3	2
all_pins[14]	556858	1			T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	6820842	1			T1	26		T2	15		T3	26
values[0x1]	1532028	1			T1	4		T3	4		T4	2
transitions[0x0=>0x1]	1531261	1			T1	4		T3	4		T4	2
transitions[0x1=>0x0]	1530189	1			T1	3		T3	3		T4	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	56164	1			T2	1		T4	1		T6	54
all_pins[0]	values[0x1]	500694	1			T1	2		T3	2		T4	1
all_pins[0]	transitions[0x0=>0x1]	500142	1			T1	2		T3	2		T4	1
all_pins[0]	transitions[0x1=>0x0]	99	1			T29	3		T273	55		T274	6
all_pins[1]	values[0x0]	556207	1			T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	651	1			T14	2		T262	2		T275	1
all_pins[1]	transitions[0x0=>0x1]	638	1			T14	2		T262	2		T275	1
all_pins[1]	transitions[0x1=>0x0]	97	1			T46	1		T176	1		T189	1
all_pins[2]	values[0x0]	556748	1			T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	110	1			T46	1		T176	1		T189	1
all_pins[2]	transitions[0x0=>0x1]	96	1			T46	1		T176	1		T189	1
all_pins[2]	transitions[0x1=>0x0]	58	1			T29	2		T161	1		T162	3
all_pins[3]	values[0x0]	556786	1			T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	72	1			T29	3		T161	3		T162	3
all_pins[3]	transitions[0x0=>0x1]	58	1			T29	3		T161	3		T162	3
all_pins[3]	transitions[0x1=>0x0]	50	1			T161	2		T276	1		T277	1
all_pins[4]	values[0x0]	556794	1			T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	64	1			T161	2		T276	1		T277	2
all_pins[4]	transitions[0x0=>0x1]	50	1			T161	2		T276	1		T277	2
all_pins[4]	transitions[0x1=>0x0]	53	1			T161	2		T162	1		T276	2
all_pins[5]	values[0x0]	556791	1			T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	67	1			T161	2		T162	1		T276	2
all_pins[5]	transitions[0x0=>0x1]	51	1			T161	2		T276	2		T131	2
all_pins[5]	transitions[0x1=>0x0]	48	1			T29	2		T161	2		T162	2
all_pins[6]	values[0x0]	556794	1			T1	2		T2	1		T3	2
all_pins[6]	values[0x1]	64	1			T29	2		T161	2		T162	3
all_pins[6]	transitions[0x0=>0x1]	50	1			T29	2		T161	2		T162	3
all_pins[6]	transitions[0x1=>0x0]	19887	1			T6	116		T9	56		T14	93
all_pins[7]	values[0x0]	536957	1			T1	2		T2	1		T3	2
all_pins[7]	values[0x1]	19901	1			T6	116		T9	56		T14	93
all_pins[7]	transitions[0x0=>0x1]	19883	1			T6	116		T9	56		T14	93
all_pins[7]	transitions[0x1=>0x0]	49	1			T29	2		T276	3		T278	1
all_pins[8]	values[0x0]	556791	1			T1	2		T2	1		T3	2
all_pins[8]	values[0x1]	67	1			T29	2		T276	3		T277	1
all_pins[8]	transitions[0x0=>0x1]	50	1			T29	2		T276	3		T277	1
all_pins[8]	transitions[0x1=>0x0]	455401	1			T6	14113		T9	23		T13	1
all_pins[9]	values[0x0]	101440	1			T1	2		T2	1		T3	2
all_pins[9]	values[0x1]	455418	1			T6	14113		T9	23		T13	1
all_pins[9]	transitions[0x0=>0x1]	455410	1			T6	14113		T9	23		T13	1
all_pins[9]	transitions[0x1=>0x0]	53	1			T29	1		T161	1		T264	2
all_pins[10]	values[0x0]	556797	1			T1	2		T2	1		T3	2
all_pins[10]	values[0x1]	61	1			T29	1		T161	1		T264	2
all_pins[10]	transitions[0x0=>0x1]	50	1			T161	1		T264	2		T276	1
all_pins[10]	transitions[0x1=>0x0]	554608	1			T1	2		T3	2		T4	1
all_pins[11]	values[0x0]	2239	1			T2	1		T4	1		T6	9
all_pins[11]	values[0x1]	554619	1			T1	2		T3	2		T4	1
all_pins[11]	transitions[0x0=>0x1]	554599	1			T1	2		T3	2		T4	1
all_pins[11]	transitions[0x1=>0x0]	91	1			T10	1		T51	1		T66	1
all_pins[12]	values[0x0]	556747	1			T1	2		T2	1		T3	2
all_pins[12]	values[0x1]	111	1			T10	1		T51	1		T66	1
all_pins[12]	transitions[0x0=>0x1]	97	1			T10	1		T51	1		T66	1
all_pins[12]	transitions[0x1=>0x0]	51	1			T29	1		T162	2		T277	1
all_pins[13]	values[0x0]	556793	1			T1	2		T2	1		T3	2
all_pins[13]	values[0x1]	65	1			T29	2		T162	2		T131	1
all_pins[13]	transitions[0x0=>0x1]	47	1			T29	2		T162	2		T131	1
all_pins[13]	transitions[0x1=>0x0]	46	1			T29	3		T161	2		T162	1
all_pins[14]	values[0x0]	556794	1			T1	2		T2	1		T3	2
all_pins[14]	values[0x1]	64	1			T29	3		T161	2		T162	1
all_pins[14]	transitions[0x0=>0x1]	40	1			T29	2		T161	2		T277	2
all_pins[14]	transitions[0x1=>0x0]	499598	1			T1	1		T3	1		T4	1