Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	297	1			T29	7		T161	7		T162	7
all_values[1]	297	1			T29	7		T161	7		T162	7
all_values[2]	297	1			T29	7		T161	7		T162	7
all_values[3]	297	1			T29	7		T161	7		T162	7
all_values[4]	297	1			T29	7		T161	7		T162	7
all_values[5]	297	1			T29	7		T161	7		T162	7
all_values[6]	297	1			T29	7		T161	7		T162	7
all_values[7]	297	1			T29	7		T161	7		T162	7
all_values[8]	297	1			T29	7		T161	7		T162	7
all_values[9]	297	1			T29	7		T161	7		T162	7
all_values[10]	297	1			T29	7		T161	7		T162	7
all_values[11]	297	1			T29	7		T161	7		T162	7
all_values[12]	297	1			T29	7		T161	7		T162	7
all_values[13]	297	1			T29	7		T161	7		T162	7
all_values[14]	297	1			T29	7		T161	7		T162	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2417

1

T29

69

T161

62

T162

69

auto[1]

2038

1

T29

36

T161

43

T162

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

775

1

T29

8

T161

14

T162

23

auto[1]

3680

1

T29

97

T161

91

T162

82

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2661

1

T29

54

T161

62

T162

69

auto[1]

1794

1

T29

51

T161

43

T162

36

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	24	1			T29	4		T161	1		T162	2
all_values[0]	auto[0]	auto[0]	auto[1]	65	1			T161	2		T162	1		T276	3
all_values[0]	auto[0]	auto[1]	auto[0]	16	1			T29	1		T130	1		T279	1
all_values[0]	auto[0]	auto[1]	auto[1]	61	1			T29	1		T161	1		T162	1
all_values[0]	auto[1]	auto[0]	auto[1]	76	1			T29	1		T161	2		T162	3
all_values[0]	auto[1]	auto[1]	auto[1]	55	1			T161	1		T264	1		T130	2
all_values[1]	auto[0]	auto[0]	auto[0]	28	1			T29	1		T280	3		T278	1
all_values[1]	auto[0]	auto[0]	auto[1]	61	1			T29	1		T161	2		T162	2
all_values[1]	auto[0]	auto[1]	auto[0]	28	1			T280	1		T278	1		T281	1
all_values[1]	auto[0]	auto[1]	auto[1]	63	1			T29	2		T161	3		T162	2
all_values[1]	auto[1]	auto[0]	auto[1]	55	1			T29	1		T161	2		T162	2
all_values[1]	auto[1]	auto[1]	auto[1]	62	1			T29	2		T162	1		T264	2
all_values[2]	auto[0]	auto[0]	auto[0]	22	1			T162	6		T264	1		T130	1
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T29	2		T161	1		T276	1
all_values[2]	auto[0]	auto[1]	auto[0]	14	1			T162	1		T131	1		T277	1
all_values[2]	auto[0]	auto[1]	auto[1]	64	1			T29	1		T161	2		T264	2
all_values[2]	auto[1]	auto[0]	auto[1]	65	1			T29	1		T161	4		T276	1
all_values[2]	auto[1]	auto[1]	auto[1]	60	1			T29	3		T264	1		T130	2
all_values[3]	auto[0]	auto[0]	auto[0]	27	1			T161	1		T162	1		T264	1
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T29	2		T161	1		T276	1
all_values[3]	auto[0]	auto[1]	auto[0]	11	1			T282	1		T283	2		T284	1
all_values[3]	auto[0]	auto[1]	auto[1]	66	1			T29	1		T161	1		T162	3
all_values[3]	auto[1]	auto[0]	auto[1]	71	1			T29	3		T161	2		T162	2
all_values[3]	auto[1]	auto[1]	auto[1]	49	1			T29	1		T161	2		T162	1
all_values[4]	auto[0]	auto[0]	auto[0]	32	1			T161	1		T264	2		T276	2
all_values[4]	auto[0]	auto[0]	auto[1]	62	1			T29	5		T161	1		T162	5
all_values[4]	auto[0]	auto[1]	auto[0]	16	1			T161	1		T264	2		T276	1
all_values[4]	auto[0]	auto[1]	auto[1]	64	1			T29	1		T161	1		T276	1
all_values[4]	auto[1]	auto[0]	auto[1]	58	1			T29	1		T162	2		T130	1
all_values[4]	auto[1]	auto[1]	auto[1]	65	1			T161	3		T276	2		T277	2
all_values[5]	auto[0]	auto[0]	auto[0]	31	1			T264	1		T276	1		T280	4
all_values[5]	auto[0]	auto[0]	auto[1]	67	1			T29	3		T161	2		T162	1
all_values[5]	auto[0]	auto[1]	auto[0]	19	1			T264	3		T285	1		T286	1
all_values[5]	auto[0]	auto[1]	auto[1]	53	1			T29	1		T161	1		T162	2
all_values[5]	auto[1]	auto[0]	auto[1]	69	1			T29	2		T161	1		T162	2
all_values[5]	auto[1]	auto[1]	auto[1]	58	1			T29	1		T161	3		T162	2
all_values[6]	auto[0]	auto[0]	auto[0]	28	1			T162	1		T276	1		T131	3
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T161	1		T264	1		T130	3
all_values[6]	auto[0]	auto[1]	auto[0]	14	1			T131	4		T282	1		T287	3
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T29	1		T161	2		T162	3
all_values[6]	auto[1]	auto[0]	auto[1]	69	1			T29	5		T161	2		T162	1
all_values[6]	auto[1]	auto[1]	auto[1]	46	1			T29	1		T161	2		T162	2
all_values[7]	auto[0]	auto[0]	auto[0]	42	1			T29	1		T161	3		T264	2
all_values[7]	auto[0]	auto[0]	auto[1]	60	1			T29	4		T162	1		T264	1
all_values[7]	auto[0]	auto[1]	auto[0]	15	1			T288	1		T289	2		T282	1
all_values[7]	auto[0]	auto[1]	auto[1]	67	1			T161	1		T162	4		T276	5
all_values[7]	auto[1]	auto[0]	auto[1]	57	1			T29	1		T162	1		T264	1
all_values[7]	auto[1]	auto[1]	auto[1]	56	1			T29	1		T161	3		T162	1
all_values[8]	auto[0]	auto[0]	auto[0]	32	1			T162	1		T264	2		T131	2
all_values[8]	auto[0]	auto[0]	auto[1]	69	1			T29	2		T161	5		T162	2
all_values[8]	auto[0]	auto[1]	auto[0]	30	1			T264	2		T131	3		T290	1
all_values[8]	auto[0]	auto[1]	auto[1]	40	1			T162	1		T276	2		T277	1
all_values[8]	auto[1]	auto[0]	auto[1]	69	1			T29	2		T161	2		T162	2
all_values[8]	auto[1]	auto[1]	auto[1]	57	1			T29	3		T162	1		T130	1
all_values[9]	auto[0]	auto[0]	auto[0]	33	1			T162	4		T264	1		T276	1
all_values[9]	auto[0]	auto[0]	auto[1]	50	1			T29	1		T161	1		T162	2
all_values[9]	auto[0]	auto[1]	auto[0]	26	1			T264	1		T276	1		T277	1
all_values[9]	auto[0]	auto[1]	auto[1]	74	1			T29	3		T161	5		T264	1
all_values[9]	auto[1]	auto[0]	auto[1]	59	1			T29	3		T161	1		T162	1
all_values[9]	auto[1]	auto[1]	auto[1]	55	1			T264	1		T276	3		T131	3
all_values[10]	auto[0]	auto[0]	auto[0]	25	1			T162	3		T280	4		T278	1
all_values[10]	auto[0]	auto[0]	auto[1]	75	1			T29	3		T161	1		T162	2
all_values[10]	auto[0]	auto[1]	auto[0]	13	1			T131	3		T277	2		T283	1
all_values[10]	auto[0]	auto[1]	auto[1]	61	1			T29	1		T161	2		T162	1
all_values[10]	auto[1]	auto[0]	auto[1]	67	1			T29	3		T161	2		T162	1
all_values[10]	auto[1]	auto[1]	auto[1]	56	1			T161	2		T264	1		T276	1
all_values[11]	auto[0]	auto[0]	auto[0]	42	1			T29	1		T161	1		T162	1
all_values[11]	auto[0]	auto[0]	auto[1]	55	1			T161	2		T162	3		T264	1
all_values[11]	auto[0]	auto[1]	auto[0]	21	1			T285	2		T291	3		T292	1
all_values[11]	auto[0]	auto[1]	auto[1]	60	1			T29	3		T161	1		T162	1
all_values[11]	auto[1]	auto[0]	auto[1]	64	1			T29	2		T161	2		T162	2
all_values[11]	auto[1]	auto[1]	auto[1]	55	1			T29	1		T161	1		T264	2
all_values[12]	auto[0]	auto[0]	auto[0]	50	1			T161	5		T162	1		T276	1
all_values[12]	auto[0]	auto[0]	auto[1]	64	1			T29	2		T161	1		T162	3
all_values[12]	auto[0]	auto[1]	auto[0]	23	1			T131	1		T280	1		T278	1
all_values[12]	auto[0]	auto[1]	auto[1]	57	1			T29	2		T162	1		T264	1
all_values[12]	auto[1]	auto[0]	auto[1]	52	1			T29	2		T161	1		T162	1
all_values[12]	auto[1]	auto[1]	auto[1]	51	1			T29	1		T162	1		T264	2
all_values[13]	auto[0]	auto[0]	auto[0]	27	1			T161	1		T162	2		T130	1
all_values[13]	auto[0]	auto[0]	auto[1]	63	1			T29	2		T161	4		T264	2
all_values[13]	auto[0]	auto[1]	auto[0]	27	1			T130	1		T276	2		T277	2
all_values[13]	auto[0]	auto[1]	auto[1]	57	1			T162	3		T264	1		T277	1
all_values[13]	auto[1]	auto[0]	auto[1]	63	1			T29	2		T161	1		T162	1
all_values[13]	auto[1]	auto[1]	auto[1]	60	1			T29	3		T161	1		T162	1
all_values[14]	auto[0]	auto[0]	auto[0]	39	1			T277	1		T280	1		T278	1
all_values[14]	auto[0]	auto[0]	auto[1]	68	1			T29	1		T161	2		T162	2
all_values[14]	auto[0]	auto[1]	auto[0]	20	1			T130	1		T291	2		T286	3
all_values[14]	auto[0]	auto[1]	auto[1]	55	1			T29	1		T161	2		T264	3
all_values[14]	auto[1]	auto[0]	auto[1]	67	1			T29	5		T161	1		T162	2
all_values[14]	auto[1]	auto[1]	auto[1]	48	1			T161	2		T162	3		T130	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal