| | | | | | | |
u_acq_fifo_next_data |
66.67 |
66.67 |
|
|
|
|
|
u_acqdata_abyte |
100.00 |
100.00 |
|
|
|
|
|
u_acqdata_signal |
100.00 |
100.00 |
|
|
|
|
|
u_alert_test |
100.00 |
100.00 |
|
|
|
|
|
u_chk |
100.00 |
100.00 |
|
100.00 |
|
|
100.00 |
u_chk |
100.00 |
|
|
100.00 |
|
|
|
u_tlul_data_integ_dec |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
u_controller_events_arbitration_lost |
97.22 |
100.00 |
91.67 |
|
|
100.00 |
|
wr_en_data_arb |
95.00 |
100.00 |
90.00 |
|
|
|
|
u_controller_events_bus_timeout |
88.89 |
100.00 |
66.67 |
|
|
100.00 |
|
wr_en_data_arb |
80.00 |
100.00 |
60.00 |
|
|
|
|
u_controller_events_nack |
88.89 |
100.00 |
66.67 |
|
|
100.00 |
|
wr_en_data_arb |
80.00 |
100.00 |
60.00 |
|
|
|
|
u_controller_events_unhandled_nack_timeout |
88.89 |
100.00 |
66.67 |
|
|
100.00 |
|
wr_en_data_arb |
80.00 |
100.00 |
60.00 |
|
|
|
|
u_ctrl_ack_ctrl_en |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_enablehost |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_enabletarget |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_llpbk |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_multi_controller_monitor_en |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_nack_addr_after_timeout |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_tx_stretch_ctrl_en |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_fdata0_qe |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_fdata_fbyte |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_fdata_nakok |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_fdata_rcont |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_fdata_readb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_fdata_start |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_fdata_stop |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_fifo_ctrl0_qe |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_fifo_ctrl_acqrst |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_fifo_ctrl_fmtrst |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_fifo_ctrl_rxrst |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_fifo_ctrl_txrst |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_host_fifo_config0_qe |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_host_fifo_config_fmt_thresh |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_host_fifo_config_rx_thresh |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_host_fifo_status_fmtlvl |
100.00 |
100.00 |
|
|
|
|
|
u_host_fifo_status_rxlvl |
100.00 |
100.00 |
|
|
|
|
|
u_host_nack_handler_timeout_en |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_host_nack_handler_timeout_val |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_host_timeout_ctrl |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_acq_stretch |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_acq_threshold |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_cmd_complete |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_controller_halt |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_fmt_threshold |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_host_timeout |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_rx_overflow |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_rx_threshold |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_scl_interference |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_sda_interference |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_sda_unstable |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_stretch_timeout |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_tx_stretch |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_tx_threshold |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_unexp_stop |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_state_acq_stretch |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_intr_state_acq_threshold |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_intr_state_cmd_complete |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_controller_halt |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_intr_state_fmt_threshold |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_intr_state_host_timeout |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_rx_overflow |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_rx_threshold |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_intr_state_scl_interference |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_sda_interference |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_sda_unstable |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_stretch_timeout |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_tx_stretch |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_intr_state_tx_threshold |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_intr_state_unexp_stop |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_test_acq_stretch |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_acq_threshold |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_cmd_complete |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_controller_halt |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_fmt_threshold |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_host_timeout |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_rx_overflow |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_rx_threshold |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_scl_interference |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_sda_interference |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_sda_unstable |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_stretch_timeout |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_tx_stretch |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_tx_threshold |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_unexp_stop |
100.00 |
100.00 |
|
|
|
|
|
u_ovrd_sclval |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ovrd_sdaval |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ovrd_txovrden |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prim_reg_we_check |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
u_rdata |
100.00 |
100.00 |
|
|
|
|
|
u_reg_if |
98.67 |
97.14 |
97.53 |
|
|
100.00 |
100.00 |
u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_rsp_intg_gen |
83.33 |
66.67 |
|
|
|
|
100.00 |
u_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|
u_status_ack_ctrl_stretch |
100.00 |
100.00 |
|
|
|
|
|
u_status_acqempty |
100.00 |
100.00 |
|
|
|
|
|
u_status_acqfull |
100.00 |
100.00 |
|
|
|
|
|
u_status_fmtempty |
100.00 |
100.00 |
|
|
|
|
|
u_status_fmtfull |
100.00 |
100.00 |
|
|
|
|
|
u_status_hostidle |
100.00 |
100.00 |
|
|
|
|
|
u_status_rxempty |
100.00 |
100.00 |
|
|
|
|
|
u_status_rxfull |
100.00 |
100.00 |
|
|
|
|
|
u_status_targetidle |
100.00 |
100.00 |
|
|
|
|
|
u_status_txempty |
100.00 |
100.00 |
|
|
|
|
|
u_status_txfull |
100.00 |
100.00 |
|
|
|
|
|
u_target_ack_ctrl_nack |
100.00 |
100.00 |
|
|
|
|
|
u_target_ack_ctrl_nbytes |
100.00 |
100.00 |
|
|
|
|
|
u_target_events_arbitration_lost |
88.89 |
100.00 |
66.67 |
|
|
100.00 |
|
wr_en_data_arb |
80.00 |
100.00 |
60.00 |
|
|
|
|
u_target_events_bus_timeout |
88.89 |
100.00 |
66.67 |
|
|
100.00 |
|
wr_en_data_arb |
80.00 |
100.00 |
60.00 |
|
|
|
|
u_target_events_tx_pending |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_target_fifo_config0_qe |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_target_fifo_config_acq_thresh |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_target_fifo_config_tx_thresh |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_target_fifo_status_acqlvl |
100.00 |
100.00 |
|
|
|
|
|
u_target_fifo_status_txlvl |
100.00 |
100.00 |
|
|
|
|
|
u_target_id_address0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_target_id_address1 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_target_id_mask0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_target_id_mask1 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_target_nack_count |
88.57 |
100.00 |
80.00 |
|
|
85.71 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_target_timeout_ctrl_en |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_target_timeout_ctrl_val |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timeout_ctrl_en |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timeout_ctrl_mode |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timeout_ctrl_val |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timing0_thigh |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timing0_tlow |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timing1_t_f |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timing1_t_r |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timing2_thd_sta |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timing2_tsu_sta |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timing3_thd_dat |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timing3_tsu_dat |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timing4_t_buf |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timing4_tsu_sto |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_txdata |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_txdata0_qe |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_val_scl_rx |
66.67 |
66.67 |
|
|
|
|
|
u_val_sda_rx |
66.67 |
66.67 |
|
|
|
|
|