Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
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Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
86.96 86.96 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_protocol_cov_cg 86.96 1 100 1 64 64



Group Instance : i2c_protocol_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
86.96 1 100 1 64 64



Summary for Group Instance i2c_protocol_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 47 8 39 82.98
Crosses 68 7 61 89.71


Variables for Group Instance i2c_protocol_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
RStart_before_read_data_ACK_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_Ack_cp 1 0 1 100.00 100 1 1 0
RStart_during_address_transmission_cp 1 0 1 100.00 100 1 1 0
RStart_during_read_data_cp 1 0 1 100.00 100 1 1 0
RStart_during_rw_bit_cp 1 1 0 0.00 100 1 1 0
RStart_during_write_data_cp 1 0 1 100.00 100 1 1 0
Read_data_ack_before_stop_cp 1 1 0 0.00 100 1 1 0
Rstart_after_Address_Ack_cp 1 0 1 100.00 100 1 1 0
Rstart_after_Address_Nack_cp 1 0 1 100.00 100 1 1 0
Start_followed_by_Rstart_cp 1 0 1 100.00 100 1 1 2
Stop_after_read_data_Nack_cp 1 0 1 100.00 100 1 1 0
Stop_after_read_data_ack_cp 1 1 0 0.00 100 1 1 0
Stop_after_write_data_Nack_cp 1 1 0 0.00 100 1 1 0
Stop_after_write_data_ack_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_addr_cp 1 1 0 0.00 100 1 1 0
Stop_without_ACK_after_data_cp 1 0 1 100.00 100 1 1 0
Stop_without_ACK_after_read_cp 1 1 0 0.00 100 1 1 0
Stop_without_ACK_after_write_cp 1 1 0 0.00 100 1 1 0
bus_state_cp 17 1 16 94.12 100 1 1 0
ip_mode_cp 2 0 2 100.00 100 1 1 0
num_rd_bytes_cp 5 0 5 100.00 100 1 1 0
num_wr_bytes_cp 5 0 5 100.00 100 1 1 0


Crosses for Group Instance i2c_protocol_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
bus_state_x_ip_mode_cp 34 2 32 94.12 100 1 1 0
num_rd_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
num_wr_bytes_x_ip_mode_cp 10 0 10 100.00 100 1 1 0
Stop_after_write_data_ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Stop_after_read_data_ack_x_ip_mode_cp 2 2 0 0.00 100 1 1 0
Stop_after_write_data_Nack_x_ip_mode_cp 2 2 0 0.00 100 1 1 0
Stop_after_read_data_Nack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Ack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Rstart_after_Address_Nack_x_ip_mode_cp 2 0 2 100.00 100 1 1 0
Start_followed_by_Rstart_cp_x_ip_mode_cp 2 1 1 50.00 100 1 1 0


Summary for Variable RStart_before_read_data_ACK_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_before_read_data_ACK_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_before_read_data_ACK_Nack 6290 1 T1 15 T2 24 T8 7


Summary for Variable RStart_during_address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Start_during_address_Acknowledge 8 1 T46 4 T47 4


Summary for Variable RStart_during_address_transmission_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_address_transmission_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_address_transmission 3 1 T65 1 T66 1 T67 1


Summary for Variable RStart_during_read_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_read_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Start_during_read_data 24 1 T46 12 T47 12


Summary for Variable RStart_during_rw_bit_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for RStart_during_rw_bit_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Start_during_rw_bit 0 1 1


Summary for Variable RStart_during_write_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for RStart_during_write_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Start_during_write_data 11263 1 T1 22 T6 58 T9 11


Summary for Variable Read_data_ack_before_stop_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Read_data_ack_before_stop_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Read_data_ack_before_stop 0 1 1


Summary for Variable Rstart_after_Address_Ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack 31 1 T46 10 T256 1 T47 10


Summary for Variable Rstart_after_Address_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Rstart_after_Address_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack 9 1 T46 4 T47 4 T65 1


Summary for Variable Start_followed_by_Rstart_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for Start_followed_by_Rstart_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5 1 T87 1 T132 2 T257 2


Summary for Variable Stop_after_read_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_read_data_Nack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack 7488 1 T1 15 T2 3 T3 21


Summary for Variable Stop_after_read_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_after_read_data_ack_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_after_read_data_ack 0 1 1


Summary for Variable Stop_after_write_data_Nack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_after_write_data_Nack_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_after_write_data_Nack 0 1 1


Summary for Variable Stop_after_write_data_ack_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_after_write_data_ack_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack 4776 1 T1 24 T4 13 T5 14


Summary for Variable Stop_without_ACK_after_addr_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_addr_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_addr 0 1 1


Summary for Variable Stop_without_ACK_after_data_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for Stop_without_ACK_after_data_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_without_ACK_after_data 2257 1 T1 24 T42 9 T52 3


Summary for Variable Stop_without_ACK_after_read_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_read_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_read 0 1 1


Summary for Variable Stop_without_ACK_after_write_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for Stop_without_ACK_after_write_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
Stop_without_ACK_after_write 0 1 1


Summary for Variable bus_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 17 1 16 94.12


User Defined Bins for bus_state_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
read_addr_nack 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle 326916 1 T1 1 T2 1 T3 1
stop 12914 1 T1 39 T2 3 T3 21
write_data_nack 417 1 T6 4 T10 4 T48 4
write_data_ack 764255 1 T1 1172 T3 3 T4 2902
read_data_nack 56338 1 T1 109 T2 88 T3 88
read_data_ack 781398 1 T1 763 T2 1943 T3 1357
write_data 5218816 1 T1 8552 T3 24 T4 17528
read_data 5546838 1 T1 5231 T2 12253 T3 10106
write_addr_nack 33 1 T46 4 T55 4 T47 4
write_addr_ack 56973 1 T1 158 T3 3 T4 47
read_addr_ack 50579 1 T1 107 T2 96 T3 77
write 67137 1 T1 184 T3 4 T4 52
read 43537 1 T1 93 T2 84 T3 66
addr 661960 1 T1 1498 T2 504 T3 407
rstart 46897 1 T1 111 T2 72 T3 3
start 35451 1 T1 120 T2 12 T3 54


Summary for Variable ip_mode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for ip_mode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device 6693128 1 T1 18138 T2 15056 T3 6
host 6977331 1 T3 12208 T4 44384 T5 5782


Summary for Variable num_rd_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_rd_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 12160 1 T2 52 T3 28 T4 52
high 785032 1 T2 1389 T3 983 T4 7211
mid 1398960 1 T2 2205 T3 2344 T4 8038
low 3020951 1 T1 4837 T2 4696 T3 6757
one 302041 1 T1 621 T2 390 T3 589


Summary for Variable num_wr_bytes_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for num_wr_bytes_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sixtyfour 15734 1 T4 65 T9 26 T48 28
high 716895 1 T4 6410 T9 546 T10 230
mid 1108175 1 T4 7032 T5 502 T6 230
low 2563550 1 T1 7373 T4 6340 T5 1671
one 306486 1 T1 1265 T3 4 T4 314


Summary for Cross bus_state_x_ip_mode_cp

Samples crossed: bus_state_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 34 2 32 94.12 2


Automatically Generated Cross Bins for bus_state_x_ip_mode_cp

Element holes
bus_state_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
[read_addr_nack] * -- -- 2


Covered bins
bus_state_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
idle device 323839 1 T1 1 T2 1 T6 1
idle host 3077 1 T3 1 T4 1 T5 1
stop device 4530 1 T1 39 T2 3 T42 14
stop host 8384 1 T3 21 T4 25 T5 27
write_data_nack device 388 1 T6 4 T10 4 T48 4
write_data_nack host 29 1 T157 6 T258 10 T259 6
write_data_ack device 462707 1 T1 1172 T3 3 T6 697
write_data_ack host 301548 1 T4 2902 T5 389 T39 271
read_data_nack device 27838 1 T1 109 T2 88 T8 25
read_data_nack host 28500 1 T3 88 T4 52 T5 56
read_data_ack device 224130 1 T1 763 T2 1943 T8 189
read_data_ack host 557268 1 T3 1357 T4 2878 T5 235
write_data device 3412570 1 T1 8552 T3 3 T6 5110
write_data host 1806246 1 T3 21 T4 17528 T5 2370
read_data device 1508805 1 T1 5231 T2 12253 T8 1295
read_data host 4038033 1 T3 10106 T4 20280 T5 1952
write_addr_nack device 32 1 T46 4 T55 4 T47 4
write_addr_nack host 1 1 T65 1 - - - -
write_addr_ack device 47496 1 T1 158 T6 208 T9 38
write_addr_ack host 9477 1 T3 3 T4 47 T5 49
read_addr_ack device 29959 1 T1 107 T2 96 T8 28
read_addr_ack host 20620 1 T3 77 T4 45 T5 49
write device 56041 1 T1 184 T6 236 T9 48
write host 11096 1 T3 4 T4 52 T5 56
read device 25686 1 T1 93 T2 84 T8 24
read host 17851 1 T3 66 T4 39 T5 42
addr device 509011 1 T1 1498 T2 504 T6 1211
addr host 152949 1 T3 407 T4 472 T5 483
rstart device 46737 1 T1 111 T2 72 T6 147
rstart host 160 1 T3 3 T11 3 T87 1
start device 13359 1 T1 120 T2 12 T6 2
start host 22092 1 T3 54 T4 63 T5 73


Summary for Cross num_rd_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_rd_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_rd_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_rd_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 1684 1 T2 52 T260 26 T182 50
device high 61468 1 T2 1389 T260 942 T153 405
device mid 202399 1 T2 2205 T8 250 T42 146
device low 1088208 1 T1 4837 T2 4696 T8 1012
device one 150980 1 T1 621 T2 390 T8 86
host sixtyfour 10476 1 T3 28 T4 52 T40 4
host high 723564 1 T3 983 T4 7211 T7 1174
host mid 1196561 1 T3 2344 T4 8038 T5 267
host low 1932743 1 T3 6757 T4 7224 T5 1361
host one 151061 1 T3 589 T4 364 T5 288


Summary for Cross num_wr_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_wr_bytes_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for num_wr_bytes_x_ip_mode_cp

Bins
ip_mode_cpnum_wr_bytes_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
device sixtyfour 8655 1 T9 26 T48 28 T52 56
device high 233479 1 T9 546 T10 230 T48 576
device mid 512724 1 T6 230 T9 616 T10 1442
device low 1832692 1 T1 7373 T6 3445 T9 2368
device one 249429 1 T1 1265 T3 4 T6 722
host sixtyfour 7079 1 T4 65 T69 100 T14 24
host high 483416 1 T4 6410 T69 9844 T14 484
host mid 595451 1 T4 7032 T5 502 T39 251
host low 730858 1 T4 6340 T5 1671 T39 1198
host one 57057 1 T4 314 T5 281 T39 236


Summary for Cross Stop_after_write_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_write_data_ack_x_ip_mode_cp

Bins
Stop_after_write_data_ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_write_data_ack device 2257 1 T1 24 T42 9 T52 3
Stop_after_write_data_ack host 2519 1 T4 13 T5 14 T39 10


Summary for Cross Stop_after_read_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 2 0 0.00 2


Automatically Generated Cross Bins for Stop_after_read_data_ack_x_ip_mode_cp

Uncovered bins
Stop_after_read_data_ack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* * -- -- 2


Summary for Cross Stop_after_write_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 2 0 0.00 2


Automatically Generated Cross Bins for Stop_after_write_data_Nack_x_ip_mode_cp

Uncovered bins
Stop_after_write_data_Nack_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* * -- -- 2


Summary for Cross Stop_after_read_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Stop_after_read_data_Nack_x_ip_mode_cp

Bins
Stop_after_read_data_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Stop_after_read_data_Nack device 1910 1 T1 15 T2 3 T42 5
Stop_after_read_data_Nack host 5578 1 T3 21 T4 12 T5 13


Summary for Cross Rstart_after_Address_Ack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Ack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Rstart_after_Address_Ack_x_ip_mode_cp

Bins
Rstart_after_Address_Ack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
Rstart_after_Address_Ack device 20 1 T46 10 T47 10 - -
Rstart_after_Address_Ack host 11 1 T256 1 T261 1 T262 1


Summary for Cross Rstart_after_Address_Nack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Nack_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for Rstart_after_Address_Nack_x_ip_mode_cp

Bins
Rstart_after_Address_Nack_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
Rstart_after_Address_Nack device 8 1 T46 4 T47 4
Rstart_after_Address_Nack host 1 1 T65 1 - -


Summary for Cross Start_followed_by_Rstart_cp_x_ip_mode_cp

Samples crossed: Start_followed_by_Rstart_cp ip_mode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 2 1 1 50.00 1


Automatically Generated Cross Bins for Start_followed_by_Rstart_cp_x_ip_mode_cp

Element holes
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTNUMBERSTATUS
* [device] 0 1 1


Excluded/Illegal bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTSTATUS
[auto[0]] [device , host] -- Excluded (2 bins)


Covered bins
Start_followed_by_Rstart_cpip_mode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] host 5 1 T87 1 T132 2 T257 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%