Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23038342	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5549441

1

T1

336

T2

162

T3

2613

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28062553	1			T1	940		T2	11189		T3	8603
values[0x0]	261803	1			T1	199		T2	308		T3	254
values[0x1]	263427	1			T1	184		T2	320		T3	273

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15991950	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12595833

1

T1

603

T2

4229

T3

4470

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	108907	1			T2	44		T3	28		T4	242
valid_sources[0x01]	102916	1			T2	56		T3	26		T4	205
valid_sources[0x02]	112860	1			T2	43		T3	38		T4	195
valid_sources[0x03]	103585	1			T2	40		T3	42		T4	181
valid_sources[0x04]	117293	1			T2	54		T3	78		T4	241
valid_sources[0x05]	108472	1			T2	42		T3	28		T4	185
valid_sources[0x06]	100799	1			T2	44		T3	33		T4	235
valid_sources[0x07]	103608	1			T2	45		T3	46		T4	210
valid_sources[0x08]	98573	1			T2	39		T3	37		T4	179
valid_sources[0x09]	109321	1			T2	32		T3	40		T4	257
valid_sources[0x0a]	101836	1			T2	67		T3	34		T4	193
valid_sources[0x0b]	104376	1			T2	33		T3	35		T4	222
valid_sources[0x0c]	108216	1			T2	44		T3	41		T4	229
valid_sources[0x0d]	112355	1			T2	53		T3	23		T4	190
valid_sources[0x0e]	146908	1			T2	38		T3	52		T4	188
valid_sources[0x0f]	110797	1			T2	40		T3	33		T4	154
valid_sources[0x10]	101202	1			T2	51		T3	35		T4	173
valid_sources[0x11]	116250	1			T2	33		T3	41		T4	188
valid_sources[0x12]	102297	1			T2	43		T3	35		T4	227
valid_sources[0x13]	111547	1			T2	28		T3	39		T4	161
valid_sources[0x14]	109277	1			T2	50		T3	37		T4	162
valid_sources[0x15]	101551	1			T2	46		T3	24		T4	159
valid_sources[0x16]	109888	1			T2	65		T3	24		T4	176
valid_sources[0x17]	107710	1			T2	49		T3	40		T4	207
valid_sources[0x18]	104974	1			T2	41		T3	26		T4	189
valid_sources[0x19]	115012	1			T2	39		T3	37		T4	156
valid_sources[0x1a]	112232	1			T2	52		T3	29		T4	165
valid_sources[0x1b]	107011	1			T2	52		T3	33		T4	175
valid_sources[0x1c]	109086	1			T2	51		T3	26		T4	173
valid_sources[0x1d]	100428	1			T2	53		T3	28		T4	204
valid_sources[0x1e]	149104	1			T2	40		T3	27		T4	215
valid_sources[0x1f]	108535	1			T2	39		T3	43		T4	151
valid_sources[0x20]	111095	1			T2	56		T3	51		T4	174
valid_sources[0x21]	113756	1			T2	41		T3	41		T4	195
valid_sources[0x22]	101800	1			T2	41		T3	43		T4	203
valid_sources[0x23]	105518	1			T2	37		T3	38		T4	206
valid_sources[0x24]	110369	1			T2	52		T3	46		T4	231
valid_sources[0x25]	113295	1			T2	41		T3	38		T4	227
valid_sources[0x26]	99487	1			T2	52		T3	32		T4	186
valid_sources[0x27]	104930	1			T2	60		T3	23		T4	199
valid_sources[0x28]	112812	1			T2	39		T3	39		T4	211
valid_sources[0x29]	113278	1			T2	41		T3	53		T4	181
valid_sources[0x2a]	105512	1			T2	44		T3	21		T4	240
valid_sources[0x2b]	103390	1			T2	43		T3	26		T4	204
valid_sources[0x2c]	121414	1			T2	43		T3	39		T4	212
valid_sources[0x2d]	112980	1			T2	49		T3	31		T4	201
valid_sources[0x2e]	100869	1			T2	59		T3	23		T4	200
valid_sources[0x2f]	123045	1			T2	62		T3	39		T4	180
valid_sources[0x30]	107873	1			T2	36		T3	33		T4	175
valid_sources[0x31]	113286	1			T2	47		T3	39		T4	196
valid_sources[0x32]	104450	1			T1	1323		T2	58		T3	14
valid_sources[0x33]	108077	1			T2	29		T3	49		T4	209
valid_sources[0x34]	111175	1			T2	45		T3	29		T4	211
valid_sources[0x35]	98236	1			T2	46		T3	36		T4	175
valid_sources[0x36]	108144	1			T2	39		T3	26		T4	193
valid_sources[0x37]	99715	1			T2	57		T3	33		T4	199
valid_sources[0x38]	106046	1			T2	55		T3	34		T4	163
valid_sources[0x39]	110388	1			T2	35		T3	38		T4	217
valid_sources[0x3a]	111897	1			T2	42		T3	26		T4	188
valid_sources[0x3b]	119098	1			T2	53		T3	58		T4	175
valid_sources[0x3c]	125659	1			T2	45		T3	50		T4	202
valid_sources[0x3d]	125031	1			T2	51		T3	33		T4	195
valid_sources[0x3e]	108630	1			T2	51		T3	39		T4	144
valid_sources[0x3f]	121675	1			T2	42		T3	33		T4	172
valid_sources[0x40]	113853	1			T2	48		T3	51		T4	161
valid_sources[0x41]	107668	1			T2	47		T3	50		T4	231
valid_sources[0x42]	100605	1			T2	45		T3	32		T4	203
valid_sources[0x43]	121324	1			T2	42		T3	48		T4	193
valid_sources[0x44]	101774	1			T2	39		T3	41		T4	155
valid_sources[0x45]	99939	1			T2	35		T3	38		T4	211
valid_sources[0x46]	112052	1			T2	39		T3	22		T4	217
valid_sources[0x47]	107438	1			T2	36		T3	42		T4	188
valid_sources[0x48]	104682	1			T2	37		T3	27		T4	198
valid_sources[0x49]	106992	1			T2	54		T3	30		T4	209
valid_sources[0x4a]	103830	1			T2	66		T3	19		T4	187
valid_sources[0x4b]	103987	1			T2	54		T3	32		T4	190
valid_sources[0x4c]	107611	1			T2	52		T3	23		T4	231
valid_sources[0x4d]	242946	1			T2	48		T3	42		T4	255
valid_sources[0x4e]	104576	1			T2	38		T3	46		T4	230
valid_sources[0x4f]	109355	1			T2	36		T3	48		T4	178
valid_sources[0x50]	100216	1			T2	42		T3	37		T4	174
valid_sources[0x51]	104185	1			T2	54		T3	33		T4	217
valid_sources[0x52]	109350	1			T2	55		T3	34		T4	176
valid_sources[0x53]	120771	1			T2	33		T3	33		T4	209
valid_sources[0x54]	107334	1			T2	54		T3	44		T4	172
valid_sources[0x55]	108348	1			T2	57		T3	31		T4	179
valid_sources[0x56]	114602	1			T2	44		T3	36		T4	193
valid_sources[0x57]	100089	1			T2	63		T3	41		T4	203
valid_sources[0x58]	110358	1			T2	34		T3	43		T4	176
valid_sources[0x59]	108179	1			T2	34		T3	38		T4	185
valid_sources[0x5a]	121325	1			T2	51		T3	36		T4	194
valid_sources[0x5b]	108164	1			T2	54		T3	27		T4	191
valid_sources[0x5c]	116608	1			T2	41		T3	46		T4	184
valid_sources[0x5d]	110111	1			T2	47		T3	54		T4	210
valid_sources[0x5e]	103098	1			T2	38		T3	40		T4	179
valid_sources[0x5f]	112743	1			T2	38		T3	36		T4	210
valid_sources[0x60]	107064	1			T2	42		T3	44		T4	220
valid_sources[0x61]	135073	1			T2	35		T3	38		T4	178
valid_sources[0x62]	187815	1			T2	30		T3	24		T4	196
valid_sources[0x63]	105553	1			T2	44		T3	31		T4	195
valid_sources[0x64]	106347	1			T2	42		T3	37		T4	202
valid_sources[0x65]	108149	1			T2	36		T3	31		T4	204
valid_sources[0x66]	106930	1			T2	42		T3	47		T4	226
valid_sources[0x67]	111541	1			T2	67		T3	27		T4	209
valid_sources[0x68]	105826	1			T2	47		T3	36		T4	200
valid_sources[0x69]	103968	1			T2	48		T3	30		T4	210
valid_sources[0x6a]	106718	1			T2	50		T3	32		T4	217
valid_sources[0x6b]	109021	1			T2	51		T3	37		T4	210
valid_sources[0x6c]	120289	1			T2	41		T3	35		T4	154
valid_sources[0x6d]	111532	1			T2	45		T3	18		T4	203
valid_sources[0x6e]	112345	1			T2	44		T3	26		T4	195
valid_sources[0x6f]	107084	1			T2	54		T3	36		T4	206
valid_sources[0x70]	109729	1			T2	32		T3	21		T4	201
valid_sources[0x71]	102078	1			T2	33		T3	32		T4	162
valid_sources[0x72]	101838	1			T2	65		T3	48		T4	170
valid_sources[0x73]	115632	1			T2	42		T3	36		T4	244
valid_sources[0x74]	103703	1			T2	41		T3	34		T4	223
valid_sources[0x75]	99438	1			T2	53		T3	33		T4	183
valid_sources[0x76]	106271	1			T2	33		T3	36		T4	217
valid_sources[0x77]	113902	1			T2	67		T3	40		T4	179
valid_sources[0x78]	107613	1			T2	46		T3	32		T4	201
valid_sources[0x79]	112582	1			T2	51		T3	42		T4	224
valid_sources[0x7a]	100871	1			T2	45		T3	43		T4	177
valid_sources[0x7b]	113282	1			T2	51		T3	32		T4	173
valid_sources[0x7c]	118035	1			T2	42		T3	31		T4	164
valid_sources[0x7d]	130120	1			T2	44		T3	34		T4	230
valid_sources[0x7e]	132848	1			T2	53		T3	52		T4	203
valid_sources[0x7f]	102361	1			T2	45		T3	53		T4	211
valid_sources[0x80]	105621	1			T2	33		T3	28		T4	178

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5299977

1

T1

231

T2

17

T3

2308

values[0x0]

all_enables

biggest_size

144683

1

T1

73

T2

106

T3

159

values[0x1]

all_enables

biggest_size

104781

1

T1

32

T2

39

T3

146