Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.48	100.00	100.00	93.91			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	256116373	0	0	0
ctrl_rd_A	256116373	3111	0	0
host_fifo_config_rd_A	256116373	4271	0	0
host_nack_handler_timeout_rd_A	256116373	2191	0	0
host_timeout_ctrl_rd_A	256116373	2011	0	0
intr_enable_rd_A	256116373	5493	0	0
ovrd_rd_A	256116373	2857	0	0
target_fifo_config_rd_A	256116373	2450	0	0
target_id_rd_A	256116373	2512	0	0
target_timeout_ctrl_rd_A	256116373	2296	0	0
timeout_ctrl_rd_A	256116373	2583	0	0
timing0_rd_A	256116373	2109	0	0
timing1_rd_A	256116373	2426	0	0
timing2_rd_A	256116373	2302	0	0
timing3_rd_A	256116373	2342	0	0
timing4_rd_A	256116373	2282	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	3111	0	0
T96	7412	27	0	0
T97	5542	10	0	0
T98	25992	260	0	0
T99	8798	168	0	0
T100	3147	12	0	0
T101	6179	13	0	0
T102	11757	271	0	0
T103	12630	34	0	0
T104	6882	11	0	0
T105	8980	16	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	4271	0	0
T106	397887	149	0	0
T107	0	123	0	0
T108	0	235	0	0
T109	0	74	0	0
T110	0	111	0	0
T111	0	223	0	0
T112	0	88	0	0
T113	0	100	0	0
T114	0	119	0	0
T115	0	77	0	0
T116	46023	0	0	0
T117	139990	0	0	0
T118	183063	0	0	0
T119	54279	0	0	0
T120	176721	0	0	0
T121	54117	0	0	0
T122	2396	0	0	0
T123	56391	0	0	0
T124	8131	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	2191	0	0
T96	7412	7	0	0
T97	5542	19	0	0
T98	25992	206	0	0
T99	8798	43	0	0
T100	3147	25	0	0
T102	11757	255	0	0
T103	12630	25	0	0
T104	6882	13	0	0
T105	8980	11	0	0
T125	1698	12	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	2011	0	0
T96	7412	1	0	0
T98	25992	231	0	0
T99	8798	46	0	0
T100	3147	28	0	0
T101	6179	6	0	0
T102	11757	191	0	0
T103	12630	19	0	0
T104	6882	35	0	0
T105	8980	28	0	0
T125	1698	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	5493	0	0
T96	7412	5	0	0
T97	5542	2	0	0
T98	25992	216	0	0
T99	8798	486	0	0
T100	3147	10	0	0
T101	6179	4	0	0
T102	11757	257	0	0
T103	12630	25	0	0
T126	1031	15	0	0
T127	1537	23	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	2857	0	0
T128	1636	67	0	0
T129	0	32	0	0
T130	0	47	0	0
T131	0	55	0	0
T132	0	40	0	0
T133	0	48	0	0
T134	0	24	0	0
T135	0	48	0	0
T136	0	44	0	0
T137	0	49	0	0
T138	13469	0	0	0
T139	19737	0	0	0
T140	3198	0	0	0
T141	50433	0	0	0
T142	171001	0	0	0
T143	13862	0	0	0
T144	149008	0	0	0
T145	21648	0	0	0
T146	225339	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	2450	0	0
T96	7412	10	0	0
T97	5542	14	0	0
T98	25992	200	0	0
T99	8798	63	0	0
T101	6179	10	0	0
T102	11757	271	0	0
T103	12630	19	0	0
T104	6882	38	0	0
T105	8980	20	0	0
T125	1698	3	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	2512	0	0
T96	7412	21	0	0
T97	5542	3	0	0
T98	25992	210	0	0
T99	8798	109	0	0
T100	3147	37	0	0
T101	6179	4	0	0
T102	11757	210	0	0
T103	12630	16	0	0
T104	6882	34	0	0
T105	8980	2	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	2296	0	0
T96	7412	5	0	0
T97	5542	16	0	0
T98	25992	176	0	0
T99	8798	68	0	0
T100	3147	14	0	0
T102	11757	244	0	0
T103	12630	29	0	0
T104	6882	24	0	0
T105	8980	5	0	0
T125	1698	5	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	2583	0	0
T96	7412	12	0	0
T97	5542	15	0	0
T98	25992	232	0	0
T99	8798	73	0	0
T100	3147	29	0	0
T101	6179	24	0	0
T102	11757	225	0	0
T103	12630	31	0	0
T104	6882	11	0	0
T105	8980	12	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	2109	0	0
T97	5542	5	0	0
T98	25992	198	0	0
T99	8798	67	0	0
T100	3147	1	0	0
T102	11757	206	0	0
T103	12630	36	0	0
T104	6882	27	0	0
T125	1698	11	0	0
T147	2248	4	0	0
T148	51582	443	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	2426	0	0
T96	7412	21	0	0
T97	5542	6	0	0
T98	25992	205	0	0
T99	8798	65	0	0
T100	3147	19	0	0
T101	6179	4	0	0
T102	11757	259	0	0
T103	12630	47	0	0
T104	6882	17	0	0
T105	8980	14	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	2302	0	0
T96	7412	4	0	0
T97	5542	1	0	0
T98	25992	226	0	0
T99	8798	26	0	0
T100	3147	13	0	0
T101	6179	5	0	0
T102	11757	232	0	0
T103	12630	51	0	0
T104	6882	32	0	0
T105	8980	9	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	2342	0	0
T96	7412	26	0	0
T98	25992	218	0	0
T99	8798	56	0	0
T100	3147	21	0	0
T101	6179	11	0	0
T102	11757	231	0	0
T103	12630	26	0	0
T104	6882	13	0	0
T125	1698	12	0	0
T147	2248	5	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	256116373	2282	0	0
T96	7412	9	0	0
T97	5542	4	0	0
T98	25992	249	0	0
T99	8798	87	0	0
T100	3147	6	0	0
T101	6179	5	0	0
T102	11757	202	0	0
T103	12630	28	0	0
T104	6882	14	0	0
T105	8980	26	0	0