Unified Coverage Report :: Group :: tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg

Group : tb.dut.u_i2c_protocol_cov::i2c_protocol_cov_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
87.83	87.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_protocol_cov_cg	87.83	1	100	1	64	64

---

Group Instance : i2c_protocol_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.83	1	100	1	64	64

---

Summary for Group Instance i2c_protocol_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	47	7	40	85.11
Crosses	68	7	61	89.71

Variables for Group Instance i2c_protocol_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
RStart_before_read_data_ACK_cp	1	0	1	100.00	100	1	1	0
RStart_during_address_Ack_cp	1	0	1	100.00	100	1	1	0
RStart_during_address_transmission_cp	1	1	0	0.00	100	1	1	0
RStart_during_read_data_cp	1	0	1	100.00	100	1	1	0
RStart_during_rw_bit_cp	1	1	0	0.00	100	1	1	0
RStart_during_write_data_cp	1	0	1	100.00	100	1	1	0
Read_data_ack_before_stop_cp	1	1	0	0.00	100	1	1	0
Rstart_after_Address_Ack_cp	1	0	1	100.00	100	1	1	0
Rstart_after_Address_Nack_cp	1	0	1	100.00	100	1	1	0
Start_followed_by_Rstart_cp	1	1	0	0.00	100	1	1	2
Stop_after_read_data_Nack_cp	1	0	1	100.00	100	1	1	0
Stop_after_read_data_ack_cp	1	1	0	0.00	100	1	1	0
Stop_after_write_data_Nack_cp	1	0	1	100.00	100	1	1	0
Stop_after_write_data_ack_cp	1	0	1	100.00	100	1	1	0
Stop_without_ACK_after_addr_cp	1	0	1	100.00	100	1	1	0
Stop_without_ACK_after_data_cp	1	0	1	100.00	100	1	1	0
Stop_without_ACK_after_read_cp	1	1	0	0.00	100	1	1	0
Stop_without_ACK_after_write_cp	1	1	0	0.00	100	1	1	0
bus_state_cp	17	0	17	100.00	100	1	1	0
ip_mode_cp	2	0	2	100.00	100	1	1	0
num_rd_bytes_cp	5	0	5	100.00	100	1	1	0
num_wr_bytes_cp	5	0	5	100.00	100	1	1	0

Crosses for Group Instance i2c_protocol_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
bus_state_x_ip_mode_cp	34	1	33	97.06	100	1	1	0
num_rd_bytes_x_ip_mode_cp	10	0	10	100.00	100	1	1	0
num_wr_bytes_x_ip_mode_cp	10	0	10	100.00	100	1	1	0
Stop_after_write_data_ack_x_ip_mode_cp	2	0	2	100.00	100	1	1	0
Stop_after_read_data_ack_x_ip_mode_cp	2	2	0	0.00	100	1	1	0
Stop_after_write_data_Nack_x_ip_mode_cp	2	1	1	50.00	100	1	1	0
Stop_after_read_data_Nack_x_ip_mode_cp	2	0	2	100.00	100	1	1	0
Rstart_after_Address_Ack_x_ip_mode_cp	2	1	1	50.00	100	1	1	0
Rstart_after_Address_Nack_x_ip_mode_cp	2	0	2	100.00	100	1	1	0
Start_followed_by_Rstart_cp_x_ip_mode_cp	2	2	0	0.00	100	1	1	0

Summary for Variable RStart_before_read_data_ACK_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for RStart_before_read_data_ACK_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Start_before_read_data_ACK_Nack

6178

1

T1

8

T2

2

T4

33

---

Summary for Variable RStart_during_address_Ack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for RStart_during_address_Ack_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
Start_during_address_Acknowledge	8	1			T45	4		T46	4

---

Summary for Variable RStart_during_address_transmission_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for RStart_during_address_transmission_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
Start_during_address_transmission	0	1	1

---

Summary for Variable RStart_during_read_data_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for RStart_during_read_data_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
Start_during_read_data	24	1			T45	12		T46	12

---

Summary for Variable RStart_during_rw_bit_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for RStart_during_rw_bit_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
Start_during_rw_bit	0	1	1

---

Summary for Variable RStart_during_write_data_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for RStart_during_write_data_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Start_during_write_data

11269

1

T2

1

T3

72

T4

21

---

Summary for Variable Read_data_ack_before_stop_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for Read_data_ack_before_stop_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
Read_data_ack_before_stop	0	1	1

---

Summary for Variable Rstart_after_Address_Ack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for Rstart_after_Address_Ack_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
Rstart_after_Address_Ack	20	1			T45	10		T46	10

---

Summary for Variable Rstart_after_Address_Nack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for Rstart_after_Address_Nack_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Rstart_after_Address_Nack

58

1

T21

1

T22

2

T24

4

---

Summary for Variable Start_followed_by_Rstart_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	1	1	0	0.00

Automatically Generated Bins for Start_followed_by_Rstart_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
unused	0	Excluded
[auto[0]]	0	Excluded

---

Summary for Variable Stop_after_read_data_Nack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for Stop_after_read_data_Nack_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Stop_after_read_data_Nack

7164

1

T4

9

T8

19

T43

12

---

Summary for Variable Stop_after_read_data_ack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for Stop_after_read_data_ack_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
Stop_after_read_data_ack	0	1	1

---

Summary for Variable Stop_after_write_data_Nack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for Stop_after_write_data_Nack_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Stop_after_write_data_Nack

51

1

T24

2

T254

2

T249

2

---

Summary for Variable Stop_after_write_data_ack_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for Stop_after_write_data_ack_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Stop_after_write_data_ack

4939

1

T2

1

T3

4

T4

8

---

Summary for Variable Stop_without_ACK_after_addr_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for Stop_without_ACK_after_addr_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
Stop_without_ACK_after_addr	1	1			T229	1

---

Summary for Variable Stop_without_ACK_after_data_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for Stop_without_ACK_after_data_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Stop_without_ACK_after_data

2215

1

T2

1

T3

4

T4

8

---

Summary for Variable Stop_without_ACK_after_read_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for Stop_without_ACK_after_read_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
Stop_without_ACK_after_read	0	1	1

---

Summary for Variable Stop_without_ACK_after_write_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for Stop_without_ACK_after_write_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
Stop_without_ACK_after_write	0	1	1

---

Summary for Variable bus_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for bus_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
idle	270053	1			T1	1		T2	1		T3	1
stop	13102	1			T2	1		T3	4		T4	17
write_data_nack	25523	1			T9	4		T42	4		T47	4
write_data_ack	857252	1			T2	60		T3	2241		T4	962
read_data_nack	55854	1			T1	28		T2	10		T4	135
read_data_ack	987100	1			T1	190		T2	33		T4	1179
write_data	5781658	1			T2	443		T3	18602		T4	6883
read_data	6979562	1			T1	1320		T2	246		T4	7953
write_addr_nack	24782	1			T11	388		T21	189		T22	1520
write_addr_ack	58813	1			T2	8		T3	224		T4	104
read_addr_nack	71654	1			T11	1890		T21	4580		T22	1118
read_addr_ack	49434	1			T1	31		T2	12		T4	152
write	69638	1			T2	8		T3	308		T4	120
read	42809	1			T1	27		T2	9		T4	126
addr	667713	1			T1	218		T2	103		T3	1694
rstart	46731	1			T1	21		T2	9		T3	144
start	36238	1			T1	2		T2	5		T3	10

---

Summary for Variable ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for ip_mode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

device

6681360

1

T1

1838

T2

948

T3

23228

host

9356556

1

T6

90

T7

8

T11

4968

---

Summary for Variable num_rd_bytes_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for num_rd_bytes_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixtyfour	37177	1			T12	544		T27	490		T40	4
high	1360509	1			T1	147		T4	299		T12	23583
mid	1906906	1			T1	542		T4	1094		T43	648
low	3213507	1			T1	549		T2	176		T4	6169
one	297527	1			T1	112		T2	52		T4	832

---

Summary for Variable num_wr_bytes_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for num_wr_bytes_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sixtyfour	21316	1			T3	84		T9	38		T42	36
high	838850	1			T3	1932		T4	93		T9	1124
mid	1272951	1			T3	3402		T4	1931		T9	1230
low	2771150	1			T2	393		T3	8537		T4	4437
one	332537	1			T2	56		T3	1069		T4	646

---

Summary for Cross bus_state_x_ip_mode_cp

Samples crossed: bus_state_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	34	1	33	97.06	1

Automatically Generated Cross Bins for bus_state_x_ip_mode_cp

Uncovered bins

bus_state_cp	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
[read_addr_nack]	[device]	0	1	1

Covered bins

bus_state_cp	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
idle	device	268248	1			T1	1		T2	1		T3	1
idle	host	1805	1			T6	1		T7	8		T11	1
stop	device	4572	1			T2	1		T3	4		T4	17
stop	host	8530	1			T11	11		T12	151		T27	17
write_data_nack	device	392	1			T9	4		T42	4		T47	4
write_data_nack	host	25131	1			T21	73		T255	3		T24	836
write_data_ack	device	471303	1			T2	60		T3	2241		T4	962
write_data_ack	host	385949	1			T12	5924		T19	222		T39	899
read_data_nack	device	27738	1			T1	28		T2	10		T4	135
read_data_nack	host	28116	1			T6	4		T11	24		T12	496
read_data_ack	device	222554	1			T1	190		T2	33		T4	1179
read_data_ack	host	764546	1			T6	3		T11	283		T12	15178
write_data	device	3465555	1			T2	443		T3	18602		T4	6883
write_data	host	2316103	1			T12	35521		T19	1380		T39	5366
read_data	device	1498441	1			T1	1320		T2	246		T4	7953
read_data	host	5481121	1			T6	54		T11	2073		T12	109108
write_addr_nack	device	28	1			T53	4		T54	4		T55	4
write_addr_nack	host	24754	1			T11	388		T21	189		T22	1520
write_addr_ack	device	47388	1			T2	8		T3	224		T4	104
write_addr_ack	host	11425	1			T12	109		T19	15		T39	4
read_addr_nack	host	71654	1			T11	1890		T21	4580		T22	1118
read_addr_ack	device	29813	1			T1	31		T2	12		T4	152
read_addr_ack	host	19621	1			T6	4		T11	22		T12	430
write	device	55843	1			T2	8		T3	308		T4	120
write	host	13795	1			T11	9		T12	124		T19	20
read	device	25527	1			T1	27		T2	9		T4	126
read	host	17282	1			T6	3		T11	24		T12	372
addr	device	504693	1			T1	218		T2	103		T3	1694
addr	host	163020	1			T6	18		T11	211		T12	2721
rstart	device	45916	1			T1	21		T2	9		T3	144
rstart	host	815	1			T12	6		T19	6		T21	4
start	device	13349	1			T1	2		T2	5		T3	10
start	host	22889	1			T6	3		T11	32		T12	381

---

Summary for Cross num_rd_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_rd_bytes_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for num_rd_bytes_x_ip_mode_cp

Bins

ip_mode_cp	num_rd_bytes_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
device	sixtyfour	1563	1			T214	48		T256	48		T257	24
device	high	58503	1			T1	147		T4	299		T214	1070
device	mid	201191	1			T1	542		T4	1094		T43	648
device	low	1091466	1			T1	549		T2	176		T4	6169
device	one	151944	1			T1	112		T2	52		T4	832
host	sixtyfour	35614	1			T12	544		T27	490		T40	4
host	high	1302006	1			T12	23583		T27	10052		T40	575
host	mid	1705715	1			T11	570		T12	34643		T27	10996
host	low	2122041	1			T6	4		T11	1512		T12	45261
host	one	145583	1			T6	29		T11	151		T12	3151

---

Summary for Cross num_wr_bytes_x_ip_mode_cp

Samples crossed: ip_mode_cp num_wr_bytes_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for num_wr_bytes_x_ip_mode_cp

Bins

ip_mode_cp	num_wr_bytes_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
device	sixtyfour	8700	1			T3	84		T9	38		T42	36
device	high	229262	1			T3	1932		T4	93		T9	1124
device	mid	532265	1			T3	3402		T4	1931		T9	1230
device	low	1876721	1			T2	393		T3	8537		T4	4437
device	one	250315	1			T2	56		T3	1069		T4	646
host	sixtyfour	12616	1			T12	154		T39	24		T141	24
host	high	609588	1			T12	9280		T39	480		T141	490
host	mid	740686	1			T12	10281		T19	504		T39	534
host	low	894429	1			T12	10612		T19	978		T39	488
host	one	82222	1			T12	662		T19	56		T39	22

---

Summary for Cross Stop_after_write_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_ack_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for Stop_after_write_data_ack_x_ip_mode_cp

Bins

Stop_after_write_data_ack_cp

ip_mode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Stop_after_write_data_ack

device

2215

1

T2

1

T3

4

T4

8

Stop_after_write_data_ack

host

2724

1

T12

28

T258

14

T70

14

---

Summary for Cross Stop_after_read_data_ack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_ack_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for Stop_after_read_data_ack_x_ip_mode_cp

Uncovered bins

Stop_after_read_data_ack_cp	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2

---

Summary for Cross Stop_after_write_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_write_data_Nack_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	1	1	50.00	1

Automatically Generated Cross Bins for Stop_after_write_data_Nack_x_ip_mode_cp

Element holes

Stop_after_write_data_Nack_cp	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[device]	0	1	1

Covered bins

Stop_after_write_data_Nack_cp

ip_mode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Stop_after_write_data_Nack

host

51

1

T24

2

T254

2

T249

2

---

Summary for Cross Stop_after_read_data_Nack_x_ip_mode_cp

Samples crossed: Stop_after_read_data_Nack_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for Stop_after_read_data_Nack_x_ip_mode_cp

Bins

Stop_after_read_data_Nack_cp

ip_mode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Stop_after_read_data_Nack

device

1967

1

T4

9

T8

19

T43

12

Stop_after_read_data_Nack

host

5197

1

T11

6

T12

123

T27

17

---

Summary for Cross Rstart_after_Address_Ack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Ack_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	1	1	50.00	1

Automatically Generated Cross Bins for Rstart_after_Address_Ack_x_ip_mode_cp

Element holes

Rstart_after_Address_Ack_cp	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[host]	0	1	1

Covered bins

Rstart_after_Address_Ack_cp	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
Rstart_after_Address_Ack	device	20	1			T45	10		T46	10

---

Summary for Cross Rstart_after_Address_Nack_x_ip_mode_cp

Samples crossed: Rstart_after_Address_Nack_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for Rstart_after_Address_Nack_x_ip_mode_cp

Bins

Rstart_after_Address_Nack_cp

ip_mode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

Rstart_after_Address_Nack

device

8

1

T45

4

T46

4

-

-

Rstart_after_Address_Nack

host

50

1

T21

1

T22

2

T24

4

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Summary for Cross Start_followed_by_Rstart_cp_x_ip_mode_cp

Samples crossed: Start_followed_by_Rstart_cp ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for Start_followed_by_Rstart_cp_x_ip_mode_cp

Uncovered bins

Start_followed_by_Rstart_cp	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2

Excluded/Illegal bins

Start_followed_by_Rstart_cp	ip_mode_cp	COUNT	STATUS
[auto[0]]	[device , host]	--	Excluded	(2 bins)