Unified Coverage Report :: Group :: tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg

Group : tb.dut.u_i2c_protocol_cov::i2c_rd_wr_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.71	85.71	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_sva_0.1/i2c_protocol_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_rd_wr_cg	85.71	1	100	1	64	64

---

Group Instance : i2c_rd_wr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance i2c_rd_wr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	24	4	20	83.33

Variables for Group Instance i2c_rd_wr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
address_match	2	0	2	100.00	100	1	1	2
cp_address_match	4	0	4	100.00	100	1	1	0
cp_read_byte	5	1	4	80.00	100	1	1	0
cp_write_byte	5	1	4	80.00	100	1	1	0
ip_mode_cp	2	0	2	100.00	100	1	1	0

Crosses for Group Instance i2c_rd_wr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_address_match_x_ip_mode	4	0	4	100.00	100	1	1	0
cross_write_byte_x_ip_mode	10	2	8	80.00	100	1	1	0
cross_read_byte_x_ip_mode	10	2	8	80.00	100	1	1	0

Summary for Variable address_match

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for address_match

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6293782

1

T1

80

T2

903

T3

22073

auto[1]

9744134

1

T1

1758

T2

45

T3

1155

---

Summary for Variable cp_address_match

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_address_match

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal	0	Illegal
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_addr_no_match	1865382	1			T1	80		T2	335		T4	10058
read_addr_match	6628297	1			T1	1729		T2	23		T4	564
write_addr_no_match	4119521	1			T2	546		T3	22059		T4	8384
write_addr_match	3089146	1			T2	20		T3	1145		T4	430

---

Summary for Variable cp_read_byte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for cp_read_byte

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_one	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	1716405	1			T1	212		T2	44		T4	2146
med	3288765	1			T1	730		T2	169		T4	4208
low	3390072	1			T1	837		T2	128		T4	4192
all_zero	98437	1			T1	30		T2	17		T4	76

---

Summary for Variable cp_write_byte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for cp_write_byte

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_one	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	1469722	1			T2	124		T3	4369		T4	1932
med	2805575	1			T2	187		T3	8824		T4	3415
low	2860187	1			T2	233		T3	9666		T4	3417
all_zero	73183	1			T2	22		T3	345		T4	50

---

Summary for Variable ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for ip_mode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

device

6681360

1

T1

1838

T2

948

T3

23228

host

9356556

1

T6

90

T7

8

T11

4968

---

Summary for Cross cross_address_match_x_ip_mode

Samples crossed: address_match ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cross_address_match_x_ip_mode

Bins

address_match

ip_mode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

device

6293694

1

T1

80

T2

903

T3

22073

auto[0]

host

88

1

T215

2

T193

7

T194

9

auto[1]

device

387666

1

T1

1758

T2

45

T3

1155

auto[1]

host

9356468

1

T6

90

T7

8

T11

4968

---

Summary for Cross cross_write_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	2	8	80.00	2

Automatically Generated Cross Bins for cross_write_byte_x_ip_mode

Element holes

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
[all_one]	*	--	--	2

Covered bins

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	device	883760	1			T2	124		T3	4369		T4	1932
high	host	585962	1			T11	151		T12	8153		T19	342
med	device	1692646	1			T2	187		T3	8824		T4	3415
med	host	1112929	1			T12	17033		T19	555		T39	2246
low	device	1744707	1			T2	233		T3	9666		T4	3417
low	host	1115480	1			T11	308		T12	16766		T19	790
all_zero	device	43915	1			T2	22		T3	345		T4	50
all_zero	host	29268	1			T12	374		T19	14		T39	94

---

Summary for Cross cross_read_byte_x_ip_mode

Samples crossed: cp_write_byte ip_mode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	2	8	80.00	2

Automatically Generated Cross Bins for cross_read_byte_x_ip_mode

Element holes

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	NUMBER	STATUS
[all_one]	*	--	--	2

Covered bins

cp_write_byte	ip_mode_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
high	device	883760	1			T2	124		T3	4369		T4	1932
high	host	585962	1			T11	151		T12	8153		T19	342
med	device	1692646	1			T2	187		T3	8824		T4	3415
med	host	1112929	1			T12	17033		T19	555		T39	2246
low	device	1744707	1			T2	233		T3	9666		T4	3417
low	host	1115480	1			T11	308		T12	16766		T19	790
all_zero	device	43915	1			T2	22		T3	345		T4	50
all_zero	host	29268	1			T12	374		T19	14		T39	94